From rcrane at stanford.edu Tue Jan 3 15:53:24 2006 From: rcrane at stanford.edu (Dick Crane) Date: Tue, 03 Jan 2006 15:53:24 -0800 Subject: Fab will open 0700 1.4.06 Message-ID: <43BB0E74.7000905@stanford.edu> Good morning lab users, The SNF fab will officially open for use at 0700 tomorrow morning, Wednesday, 1/4/06. Some tools have been rebuilt, modified, or just cleaned. Please check tool status and history before using the tools. Most tools will have been requalified (checked for proper operation) by Wednesday morning. Again, please check tool status prior to use. SVG tracks are working well. Innotec hoist and planetary drive are great. STSetch etch rate be improved. Diffusion is ready. Thanks goes to the maintenance group for their Annual Maintenance Marathon and the process staff for requalifying the tools. Welcome back to another year at SNF, Dick From mtang at stanford.edu Wed Jan 4 10:12:41 2006 From: mtang at stanford.edu (Mary Tang) Date: Wed, 04 Jan 2006 10:12:41 -0800 Subject: Wet benches unavailable Thursday morning Message-ID: <43BC1019.1040103@stanford.edu> Hi everyone -- We're sorry, but due to various issues, relamping of the lab did not occur as usual during the shutdown. Instead, dead light bulbs will be replaced over the next several days. Equipment will be reserved/shutdown to accomodate relamping. As a result, wbdiff, wbnonmetal, and wbsilicide will be unavailable from 8-10 am tomorrow (Thursday) morning to accomodate relamping. We apologize for the incovenience. Please schedule your cleans accordingly. Thanks for your patience -- Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Wed Jan 4 10:37:41 2006 From: mtang at stanford.edu (Mary Tang) Date: Wed, 04 Jan 2006 10:37:41 -0800 Subject: New Year's Housekeeping and Hygiene Message-ID: <43BC15F5.7010609@stanford.edu> Happy new year and welcome back! Just a couple of concerns of note, as you return to the lab... First, if you left any wafers, cassettes, or other personal items in the lab outside of your personal bins, they were removed and placed in the CAD room (CIS 151). These items have been placed in large boxes labeled with the areas in which they were found. If you would like to retrieve your items from these boxes, please do go ahead and do so, but handle the items in these boxes with care (they belong to your fellow labmembers and I'm sure you'd appreciate their careful handling of your belongings) and return them to their original boxes, so that their owners have a chance of finding them. Please note that items that remain unclaimed in the next six months may be recycled or discarded. Second, there have been complaints from some labmembers -- and even our laundry service (??!?) -- about how particularly soiled and smelly some of our bunnysuits are. Please note that the laundry service cannot use conventional detergents for washing -- instead, they use cleanroom-compatible surfactant. Therefore, the laundry cannot remove built-up grime from clothing as well as your own washer can. So please, please, please -- do the laundry sorters and our fellow labmembers a favor and change your bunnysuit every now and then. Hopefully, with our new hanger tagging system, we should be able to cycle bunnysuits through faster, so that there should always be sufficient suits on hand, even in the event of a lab evacuation. Remember, cleaned suits are delivered every Tuesday, so you might schedule your bunnysuit change accordingly. Thanks for your attenion, and please do let us know your comments and concerns... Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mahnaz at snf.stanford.edu Wed Jan 4 15:07:59 2006 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Wed, 04 Jan 2006 15:07:59 -0800 Subject: Ultratech tape Message-ID: <43BC554F.6010906@snf.stanford.edu> Hello all, Sorry for sending this email out to the general mail. I have given the Ultratech tape to some one about two weeks before holiday and I can not remember whom? So if you have it, would you please bring it back as I really need it. You may borrow it again when I am done with it. Two weeks before holiday I lost all my inbox emails that is why I am not sure who has the tape. Thanks mahnaz From skier75 at stanford.edu Wed Jan 4 23:02:27 2006 From: skier75 at stanford.edu (Hyunsoo Yang) Date: Wed, 4 Jan 2006 23:02:27 -0800 Subject: Ph.D. Oral Examination--Hyunsoo Yang Message-ID: <1136444547.43bcc4830f053@webmail.stanford.edu> Special University Ph.D. Oral Examination "Metal spintronics: Tunneling spectroscopy in junctions with magnetic and superconducting electrodes" Hyunsoo Yang Department of Electrical Engineering Advisor: Professor James S. Harris / Dr. Stuart Parkin 3:00 PM, Monday, Jan 9, 2006 Packard 202 (Refreshments served at 2:45 PM) Recent advances in generating, manipulating and detecting spin-polarized electrons and their electrical current make possible entirely new classes of spin-based sensor, logic and storage devices. An important such device is the magnetic tunnel junction (MTJ) which has been under intensive study in recent years: important applications include nonvolatile memory cells for high performance magnetic random access memory (MRAMs), and magnetic field sensors for high density hard disk drive read heads. Many aspects of the tunneling magnetoresistance (TMR) phenomenon are poorly understood although it is clear that the fundamental origin of TMR is the spin-polarization of the tunneling current. Thus, the measurement of the magnitude and sign of the tunneling spin polarization (TSP) is very important to help the further understanding of TMR. Recently, an extremely high TMR value, of up to 350% at room temperature, has been reported in practical MTJ devices. These MTJs are fabricated with highly oriented crystalline MgO(100) tunnel barriers by straightforward magnetron sputter deposition at room temperature. In parallel with this observation, we report extremely high TSP values exceeding 90% from CoFe/MgO tunnel spin injectors (using an aluminum superconducting electrode as a spin detector at 250mK). These TSP values rival the highest polarization values previously reported using exotic half-metallic oxide ferromagnets. The spin polarization of electrons extracted from ferromagnetic films can be probed by a variety of techniques including photoemission, point contact Andreev reflection, and superconducting tunneling spectroscopy (STS). Amongst these techniques, STS is perhaps the most relevant with respect to TMR but until now all measurements have been made with Al superconducting films which have low superconducting transition temperatures (Tc) so that the measurements must be made at temperatures below 400mK. We demonstrate the use of superconducting electrodes formed from NbN which has a much higher Tc (~16K) than Al. The use of NbN allows measurements of TSP at higher temperatures above 1K. We have observed the phenomenon of Kondo-assisted tunneling in planar magnetic tunnel junctions for the first time. We demonstrate not only an increased conductance at low bias (due to the Kondo resonance) but also show that the tunneling magnetoresistance is quenched in the Kondo regime. The Kondo effect may be a useful means of detecting and possibly manipulating the spins of individual electrons in nanodots. From guerra at par.stanford.edu Thu Jan 5 10:58:02 2006 From: guerra at par.stanford.edu (Ann Guerra) Date: Thu, 5 Jan 2006 10:58:02 -0800 (PST) Subject: SPECIAL SEMINAR - 40Gb/s Serial Link, Jan 9, 2006 Message-ID: SPECIAL SEMINAR: "Design of Low-Cost Package for 40-Gb/s Serial Link using Wire-Bonded PBGA" Dong Gun Kam KAIST (Korea Advanced Institute of Science and Technology) Monday, January 9, 2006 11:00 a.m. CISX-338 ABSTRACT Recently the performance of high-speed chip-to-chip serial links has been limited by the bandwidth of a package. A 40 Gb/s packaging solution that uses low-cost wire-bonded plastic ball grid array (WB-PBGA) technology is presented. Since such a high speed is well beyond the reach of conventional package designs, the new design methodologies including the discontinuity cancellation of signal current paths and the supply of low-inductance return current paths are proposed. The design methods of bonding wires, vias, solder ball pads, and power distribution networks are suggested. The proposed design methodologies and packaging solution are verified with simulation and measurement. By avoiding the use of low-loss dielectric materials and/or advanced packaging technology, the result can be the lowest cost packaging solution for future high-speed serial links. Although our consideration in this research is limited to WB-PBGA packages, the proposed design methodologies can be readily applied to advanced packaging technology providing further improvement of channel bandwidth. Mr. Dong Gun Kam will be receiving his doctorate from KAIST in July 2006 on high-speed interconnection and package design with emphasis on signal integrity, power integrity and EMI/EMC, under Prof. Joungho Kim. He will be presenting his work this year at PIERS in Cambridge, MA, in March and at ECTC in San Diego in May. From mtang at stanford.edu Thu Jan 5 13:21:35 2006 From: mtang at stanford.edu (Mary Tang) Date: Thu, 05 Jan 2006 13:21:35 -0800 Subject: Welcome Uija Yoon! Message-ID: <43BD8DDF.7040307@stanford.edu> Greetings everyone! And to start off the new year, I'd like to introduce you all to Uija Yoon, our newest process staff member. Uija comes to us most recently from HP Labs, where she spent many years -- working on many of the very same tools we have at SNF (?!?) Uija has managed to win over hearts (and stomachs) with her great oatmeal cookies. Uija will be starting out working with Mahnaz in the litho area and eventually branch out to work with Nancy in the etch area, too. Uija is sharing office space with Uli and Jeannie. Please do stop by and say "hi"! Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From aeonia at stanford.edu Thu Jan 5 22:22:16 2006 From: aeonia at stanford.edu (Hyeun-Su Kim) Date: Thu, 5 Jan 2006 22:22:16 -0800 Subject: Photoresist spray coater? Message-ID: <000d01c61289$8a601510$afa540ab@interposer> Happy New Year everyone, Do we have a photoresist spray coater in the SNF? I was told there was one but I have never seen one. Has anybody heard about or used this? Is it currently available machine? Your advice will be very helpful to me. Thank you. HyeunSu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mahnaz at snf.stanford.edu Fri Jan 6 16:07:37 2006 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Fri, 06 Jan 2006 16:07:37 -0800 Subject: Yellow flammable cabinets Message-ID: <43BF0649.1030306@snf.stanford.edu> Hello all, Happy new year and welcome to another year, much better and improved. We have purchased a small yellow flammable cabinet which now sits next to the other two big one. I have moved all the nonstandard small chemicals to the little cabinet so look for them there. The two yellow cabinet have been divided and labeled accordingly and I like to keep it that way. It only took pretty much two days of Uli, Uija and My time so be kind and keep it nice and organize.. All the SU8 chemicals are in the secondary container on top shelf of the Right yellow cabinet, I like them there and nothing else in that container . All the Ebeam resist are on the right shelf of the left yellow cabinet. Every thing has been labeled and divided as much as possible so we can supply enough chemicals for evenings and weekends, so please help us. You need to follow the rules and put things were they go, misplaced chemicals were be taken without notification. The rules are still the same, nonstandard chemicals should have the ok from specmatt , the yellow label and the Bar code. You will see a lot more room in the cabinets and that is because Iam not quiet done with it . I think there are few chemicals that I still need to account for. Any suggestion or idea is most welcome. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From donghun.choi at stanford.edu Fri Jan 6 16:17:04 2006 From: donghun.choi at stanford.edu (Donghun Choi) Date: Fri, 6 Jan 2006 16:17:04 -0800 Subject: undoped or high resistivity Si Wafer References: <43BD8DDF.7040307@stanford.edu> Message-ID: <007e01c6131f$b072df30$0100000a@challenger> Hi all I need undoped or high resistivity ( around or larger than 10 K ohm) Si wafer. I just need one or two wafers. If someone has, can I borrow it ? It'll be very helpful for me and MBE machine of Harris group. Thanks Donghun From kevhuang at stanford.edu Mon Jan 9 12:04:11 2006 From: kevhuang at stanford.edu (Huang Kevin) Date: Mon, 9 Jan 2006 12:04:11 -0800 Subject: resistance of Al2O3 to HF Message-ID: <93586f8c0601091204k53fa9609udb4e5b9804d7c5b0@mail.gmail.com> Hi, Does anyone know what the etch rate of aluminum oxide (Al2O3) is in HF solution (BOE or 49% HF)? Does it etch a lot slower than SiO2 does in HF or about the same? Thanks for the help. Kevin -------------- next part -------------- An HTML attachment was scrubbed... URL: From kevhuang at stanford.edu Mon Jan 9 17:12:23 2006 From: kevhuang at stanford.edu (Huang Kevin) Date: Mon, 9 Jan 2006 17:12:23 -0800 Subject: resistance of Al2O3 to HF In-Reply-To: <1136851476.43c2fa14c208b@webmail.stanford.edu> References: <93586f8c0601091204k53fa9609udb4e5b9804d7c5b0@mail.gmail.com> <1136851476.43c2fa14c208b@webmail.stanford.edu> Message-ID: <93586f8c0601091712q629a9efqd39f123c9380dfce@mail.gmail.com> Thanks to everyone who helped out. It seems Al2O3 will not last long in HF. Then, are there any CMOS compatible oxides that can survive the HF etch (besides silicon nitride since my wafer will have Al on it) or are there etchants that attacks SiO2 and not Al2O3? Thanks a lot. Kevin On 1/9/06, Ryan Tu wrote: > > Hi Kevin, > > I am not sure of the exact rate, but the etch is fairly quick. I would > say > at least as fast as SiO2, if not faster. I believe you can find the etch > rate in the literature. There is also a link to some standard etchants on > the CIS website that might have the information you are looking for. > > Ryan > > Quoting Huang Kevin : > > > Hi, > > Does anyone know what the etch rate of aluminum oxide (Al2O3) > > is > > in HF solution (BOE or 49% HF)? Does it etch a lot slower than SiO2 > does > > in > > HF or about the same? > > > > Thanks for the help. > > > > Kevin > > > > > -- ================================== Kevin Huang Ph.D. Student, Peumans Group Stanford Organic Electronics Lab Dept. of Electrical Engineering Email: kevhuang at stanford.edu Phone: (650) 725-6924 ================================== -------------- next part -------------- An HTML attachment was scrubbed... URL: From bongsang at stanford.edu Tue Jan 10 14:42:25 2006 From: bongsang at stanford.edu (Bongsang Kim) Date: Tue, 10 Jan 2006 14:42:25 -0800 Subject: about the binder Message-ID: <200601102242.k0AMgUDl005627@smtp3.Stanford.EDU> Hello, Is there anyone who saw my red binder written "Hotdog 4"? Thanks, Bongsang -------------- next part -------------- An HTML attachment was scrubbed... URL: From enwang at stanford.edu Wed Jan 11 10:26:20 2006 From: enwang at stanford.edu (Evelyn Wang) Date: Wed, 11 Jan 2006 10:26:20 -0800 Subject: Ph.D. Oral Exam Announcement Message-ID: <002401c616dc$85719ef0$b6ac0c80@Chrysanthemum> Ph.D. Oral Examination, Stanford University Characterization of Microfabricated Two-Phase Heat Sinks for IC Cooling Applications Evelyn N. Wang Advisor: Thomas W. Kenny and Kenneth E. Goodson Department of Mechanical Engineering Time: 4:15 P.M. (refreshments will be served at 4:00 P.M.) Date: Tuesday, January 17th, 2006 Location: Building 530, Room 127 The increasing heat generation rates in integrated circuit (IC) chips pose severe thermal management challenges for the semiconductor industry. The cooling capacity of conventional heat sinks will soon reach their limit and novel methods for heat dissipation from ICs need to be developed. Two-phase microchannels and microjets have received attention because they promise compact and efficient cooling solutions. This talk focuses on microchannel cooling technologies during incipient boiling, where bubbles nucleate, grow, and depart from nucleation sites on channel walls. Understanding bubble dynamics and determining departure criteria are critical in these devices such that local dry-out and subsequently poor cooling in regions can be avoided. Silicon microchannels with hydraulic diameters less than 400 um were fabricated with heaters and sensors. When heating power was applied, bubbles formed due to heterogeneous nucleation and grew from the channel side-walls. In order to understand bubble dynamics, micron-resolution particle image velocimetry (uPIV) was used to obtain two-dimensional liquid velocity fields surrounding the nucleating bubbles. However, the limited information from the data requires the development of a hybrid method to reconstruct the three-dimensional geometry and associated three-dimensional velocity field. The combination of experiments and numerical simulations with this methodology yields important information such as bubble geometry, growth rates, contact angles, and forces that contribute towards the understanding of the physical mechanisms behind growth and departure. Some recent efforts on two-phase microjet impingement cooling will also be discussed. In this project, microjet test structures were designed, fabricated, and characterized using a custom heater device. Heat removal of over 90 W/cm^2 using a 4-microjet array was demonstrated, which suggests microjet impingement is a promising cooling solution. Insights into microjet hydrodynamics were also obtained with flow visualizations. These current studies show promise towards developing optimized MEMS two-phase heat sinks for future IC chip cooling. The heat sinks are intended for the eventual integration into a closed-loop electroosmotically pumped cooling system. From nevran at stanford.edu Wed Jan 11 11:44:44 2006 From: nevran at stanford.edu (Nevran Ozguven) Date: Wed, 11 Jan 2006 11:44:44 -0800 Subject: SOI wafers Message-ID: <43C5602C.2090304@stanford.edu> Hi, I am looking for a vendor to order SOI wafers with an SOI thickness of about 20 nm. I had ordered them from ACA technologies but they seem to have a problem with their production line and don't know when it will be fixed. Are there any other vendors that you can recommend? Thanks a lot, Nevran From yamanaka at snowmass.stanford.edu Thu Jan 12 10:17:38 2006 From: yamanaka at snowmass.stanford.edu (Kazuhiko Yamanaka) Date: Thu, 12 Jan 2006 10:17:38 -0800 Subject: SU-8 recipe In-Reply-To: <43C5602C.2090304@stanford.edu> References: <43C5602C.2090304@stanford.edu> Message-ID: <20060112101200.36C0.YAMANAKA@snowmass.stanford.edu> Hi, I am trying to coat SU-8 on SOI wafer to make protect layer. The thickness of SU-8 is from 1um to 5um. Does anyone have the recipe of SU-8? Thanks for your help, Kazuhiko ------- Kazuhiko Yamanaka Harris Group, Solid State & Photonics Lab, Center for Integrated Systems, Stanford University CIS-X Rm 126X, Stanford, CA 94305-4075 Tel : (650)725-6909 Fax: (650)723-4659 E-mail : yamanaka at snowmass.stanford.edu From yzhu at ee.ucr.edu Thu Jan 12 14:39:01 2006 From: yzhu at ee.ucr.edu (Yan Zhu) Date: Thu, 12 Jan 2006 14:39:01 -0800 Subject: Looking for PFA wafer basket information Message-ID: <20060112223901.B275B4ED@post.ee.ucr.edu> Hi, I am so sorry to bother all of you. I really need some help for you. Our group plans to order some wafer basket like http://www.wafercare.com/Default.asp?G=57 ,but this company only provide the order with the minimum quantity for 100. If you know any other company that has this kind of product, please help me out. I will appreciate it a lot. Thanks so much! Thanks Yan Zhu From ebasham32 at earthlink.net Thu Jan 12 14:48:22 2006 From: ebasham32 at earthlink.net (Eric) Date: Thu, 12 Jan 2006 14:48:22 -0800 Subject: SU-8 recipe In-Reply-To: <20060112101200.36C0.YAMANAKA@snowmass.stanford.edu> Message-ID: <001801c617ca$4adedcf0$0400a8c0@newtablet> Attached. I do this all the time. Let me know if you have questions. This mixes very quickly. BTW: I have observed that skipping the 95 degree prebake step and doubling the time of the 65 step on a hotplate gives better and more reliable resolution results. Likely due to the high solvent content. These films take a REALLY long time to fully cure. Microchem recommends a single bake step at 105 C for pre and post bake for thin SU8. Example from Mark Shaw: Eric, In order to dilute the SU-8 2015 you would need to dilute the product with SU-8 2000 Thinner according to the following calculations: Starting solids content of SU-8 2015 = 64% Starting solids content of SU-8 2002 = 29% Volume of SU-8 2015 = 100ml (for example) (64/29) * 100ml = Diluted volume = 220ml Therefore, 220ml - 100ml = amount of SU-8 2000 Thinner required = 120ml Check = 64/220ml = 29% I hope this helps, -----Original Message----- From: Kazuhiko Yamanaka [mailto:yamanaka at snowmass.stanford.edu] Sent: Thursday, January 12, 2006 10:18 AM To: labmembers at snf.stanford.edu Subject: SU-8 recipe Hi, I am trying to coat SU-8 on SOI wafer to make protect layer. The thickness of SU-8 is from 1um to 5um. Does anyone have the recipe of SU-8? Thanks for your help, Kazuhiko ------- Kazuhiko Yamanaka Harris Group, Solid State & Photonics Lab, Center for Integrated Systems, Stanford University CIS-X Rm 126X, Stanford, CA 94305-4075 Tel : (650)725-6909 Fax: (650)723-4659 E-mail : yamanaka at snowmass.stanford.edu -------------- next part -------------- A non-text attachment was scrubbed... Name: SU solids content.doc Type: application/msword Size: 26624 bytes Desc: not available URL: From mtang at stanford.edu Thu Jan 12 17:32:23 2006 From: mtang at stanford.edu (Mary Tang) Date: Thu, 12 Jan 2006 17:32:23 -0800 Subject: EE410 is HERE!! Message-ID: <43C70327.3030906@stanford.edu> Greetings Labmembers: It's that time of year again, when the days begin to get longer and the bulbs start sending shoots up through the ground... and the EE410 students suddenly converge on the lab. For those of you who don't know, EE410 is a very challenging and interesting class in which the students fabricate, model, and test a CMOS device (for more info, check out the class website at http://www.stanford.edu/class/ee410). The schedule for processing this device is aggressive -- and we ask for your patience over the next 8 weeks as priorities and equipment access may be shifted in order to allow full support for this class. You may see some wide-eyed and possibly scared looking students in the lab, who are learning and doing some of their own processing during their lab sessions. The schedule for the lab sections (which will also be posted on the calendar outside the gowning room) is as follows: Tuesday morning, 8-12, Dawson Wong is the TA Wednesday afternoon, 1-5, Dawson is again the TA Thursday morning, 8-12, Serena Koh is the TA Thursday afternoon, 1-5, Donghyun Kim is the TA. If you have any questions about EE410, please contact Gladys (the lead coordinator for the lab portion of this class -- she's at gladys at snf.stanford.edu). Thanks for your attention -- The SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From yhkuo at stanford.edu Thu Jan 12 19:15:44 2006 From: yhkuo at stanford.edu (Yu-Hsuan Kuo) Date: Thu, 12 Jan 2006 19:15:44 -0800 Subject: PhD Oral Exam - Yu-Hsuan Kuo (Jan 17, Tuesday 9:30 AM) Message-ID: <1137122144.43c71b6036274@webmail.stanford.edu> University Ph.D. Oral Examination Yu-Hsuan Kuo Department of Electrical Engineering Stanford University 9:30 AM, Tuesday, January 17, 2006 CIS-X Auditorium (Refreshments served at 9:15 AM) "Germanium-Silicon Electroabsorption Modulators for Optical Interconnects" Optical interconnects between silicon electronics have attracted researchers? attentions for a long time because optical links have potential advantages for higher speed, lower power, and interference-immunity. Successful, monolithic integration of photonics and electronics will significantly reduce the cost of optical components and further combine the functionalities of chips on the same or different boards or systems. Electro-optic and thermo-optic effects have been previously utilized to fabricate modulators - the fundamental building blocks for optical interconnects; however, the inefficiency of these mechanisms in silicon has hampered silicon-based group-IV optical transmitters. Since germanium has a local minimum at the zone center of band structure and a high absorption coefficient, it is possible to realize a strong electroabsorption effect in germanium. In this talk, I will present germanium-silicon electroabsorption modulators for optical interconnects. SiGe p-i-n devices with strained Ge/SiGe multi-quantum-well (MQW) structures in the i-region are grown on relaxed Ge-rich SiGe buffer layers on silicon substrates. The device fabrication is based on processes for standard silicon electronics and is suitable for mass-production with complementary metal-oxide-semiconductor (CMOS) chips. Quantum-confined Stark effect (QCSE) - the strongest electroabsorption effect and optical modulation mechanism - is observed in these Ge MQW devices on silicon. The absorption spectra show clear exciton peaks related to carriers inside the Ge QWs. The exciton peaks are red-shifted and their absorption coefficients are reduced under increased reverse biases. The magnitude of QCSE is comparable to that of III-V materials at similar wavelengths. With proper MQW structure design, we also demonstrated strong QCSE over the entire C-band wavelength region, making these modulators suitable for telecommunications and also compatible with typical CMOS-chip-operational temperatures (~90?C). The electroabsorption devices can also be used as photodetectors under high reverse bias. Germanium-silicon electroabsorption devices will enable efficient high-speed modulators and photodetectors for optical interconnects. From mtang at snf.stanford.edu Fri Jan 13 17:30:20 2006 From: mtang at snf.stanford.edu (Mary Tang) Date: Fri, 13 Jan 2006 17:30:20 -0800 Subject: SU-8 recipe In-Reply-To: <001801c617ca$4adedcf0$0400a8c0@newtablet> References: <001801c617ca$4adedcf0$0400a8c0@newtablet> Message-ID: <43C8542C.6010507@snf.stanford.edu> Hi everyone -- First, thanks Eric, for sharing this info (I KNOW I'm saving this for future reference!) Second, I was asked to clarify some lab procedures regarding SU-8, and so thought I'd take the opportunity to do so here... Although Microchem SU-8 is a wonderfully versatile and useful material, it is also notoriously difficult to remove, once it's cured. And it self-cures quite nicely. In the early days of SU-8, it would get everywhere in the litho area, permanently clogging chucks and drain lines and making a mess of benchtops and wafer cassettes. (Want to know how difficult it is to get rid of cured SU-8? To paraphrase the Microchem website: "SU-8 is a highly functional epoxy and therefore extremely difficult to strip. Conventional stripper solvents... ...will not remove hard baked (cured) SU-8. However, dozens of SU-8 users have successfully developed stripping processes. Techniques include RIE plasma ashing, laser ablation, molten salt baths, CO2 crystal and water jets and pyrolysis, among others." I think they neglected to include heavy artillery...) So... although SU-8 is allowed in the lab, there are certain restrictions of where and how it can be applied and some additional precautions for cleanup. Yes, it's a bit inconvenient, but it certainly helps protect the equipment and other people's work. Therefore, if you'd like to use SU-8 in the lab, you'll have to obtain Mahnaz' seal of approval and get on her list of "qualified SU-8 users". She will show you the tricks of the trade on how to manage and get the most out of your SU-8 process, while keeping the lab clean. Thanks for your attention -- Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu Eric wrote: >Attached. I do this all the time. Let me know if you have questions. This >mixes very quickly. > >BTW: I have observed that skipping the 95 degree prebake step and doubling >the time of the 65 step on a hotplate gives better and more reliable >resolution results. Likely due to the high solvent content. These films >take a REALLY long time to fully cure. > >Microchem recommends a single bake step at 105 C for pre and post bake for >thin SU8. > >Example from Mark Shaw: > >Eric, > >In order to dilute the SU-8 2015 you would need to dilute the product with >SU-8 2000 Thinner according to the following calculations: > >Starting solids content of SU-8 2015 = 64% >Starting solids content of SU-8 2002 = 29% > >Volume of SU-8 2015 = 100ml (for example) > >(64/29) * 100ml = Diluted volume = 220ml > >Therefore, 220ml - 100ml = amount of SU-8 2000 Thinner required = 120ml > >Check = 64/220ml = 29% > >I hope this helps, > >-----Original Message----- >From: Kazuhiko Yamanaka [mailto:yamanaka at snowmass.stanford.edu] >Sent: Thursday, January 12, 2006 10:18 AM >To: labmembers at snf.stanford.edu >Subject: SU-8 recipe > >Hi, > >I am trying to coat SU-8 on SOI wafer to make protect layer. >The thickness of SU-8 is from 1um to 5um. >Does anyone have the recipe of SU-8? > >Thanks for your help, >Kazuhiko > >------- >Kazuhiko Yamanaka >Harris Group, Solid State & Photonics Lab, >Center for Integrated Systems, >Stanford University >CIS-X Rm 126X, >Stanford, CA 94305-4075 >Tel : (650)725-6909 >Fax: (650)723-4659 >E-mail : yamanaka at snowmass.stanford.edu > > From yuhykr at stanford.edu Tue Jan 17 14:02:49 2006 From: yuhykr at stanford.edu (Hyun-Yong Yu) Date: Tue, 17 Jan 2006 14:02:49 -0800 Subject: need PFA wafer basket for small pieces Message-ID: <000001c61bb1$c16dd5c0$626018ac@D6TPV981> Hi, I need some help for you. I want to use clean PFA wafer basket for small pieces such as http://www.wafercare.com/Default.asp?G=57. I tried to buy this wafer basket. However there is nothing left in stock. I want to share or borrow your wafer basket if you have the clean PFA wafer basket or extra PFA wafer basket. I am sorry to bother all of you. Thank You Hyun-Yong Yu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Wed Jan 18 09:31:40 2006 From: mbaran at stanford.edu (Maureen Baran) Date: Wed, 18 Jan 2006 09:31:40 -0800 Subject: Printer outside Mary Tang's Office Message-ID: <200601181731.k0IHVeht029232@smtp1.Stanford.EDU> Good Morning Everyone, Unfortunately, the printer (Bartlett) outside of Mary Tang's office is out of service. We have scheduled a service call and they will be here, tomorrow morning to repair it. We apologize for the inconvenience this might cause you today. Sincerely, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From fely at gloworm.Stanford.EDU Thu Jan 19 14:08:53 2006 From: fely at gloworm.Stanford.EDU (Fely Barrera) Date: Thu, 19 Jan 2006 14:08:53 -0800 Subject: EE 310 Seminar Message-ID: <200601192208.k0JM8rAG011945@gloworm.Stanford.EDU> EE 310 Seminar Date: Jan 24, 2006 Time: 4:15pm - 5:05 pm Place: Hewlett 102 Title: Programmable and Reconfigurable Analog Signal Processing Systems Speaker: Paul Hasler ssociate Professor in the School of Electrical and Computer Engineering Georgia Institute of Technology Abstract: With the need for low-power portable / autonomous sensor systems, getting as much computation for a fixed power budget becomes more and more critical. Analog signal processing can be a factor of 10,000 more efficient, that is power dissipated for given computation bandwidth, than custom digital computation for low to moderate (i.e. 6-12 bit SNR) resolution signals. For these techniques to be viable, these analog techniques must be programmable, and must scale in performance similar or better than digital processing for smaller geometry devices. Analog programmability will also have an impact on the resulting digital signal processing circuits. Further, the potential of large-scale Field Programmable Analog Arrays (FPAA), devices analogous to FPGAs with millions of programmable analog parameters, opens up possibilities for a wide range of applications, and the potential of widely available FPAA ICs makes these approachable for a wide range of applications. Using these analog signal processing techniques for a system design, signal compression is not only essential for efficient transmission from the sensor, but for efficient digital transmission between the ICs for low-power operation. Biography: Paul Hasler is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology. Dr. Hasler received his M.S. and B.S.E. in Electrical Engineering from Arizona State University in 1991, and received his Ph.D. From California Institute of Technology in Computation and Neural Systems in 1997. His current research interests include low power electronics, mixed-signal system ICs, floating-gate MOS transistors, adaptive information processing systems, "smart" interfaces for sensors, cooperative analog-digital signal processing, device physics related to submicron devices or floating-gate devices, and analog VLSI models of on-chip learning and sensory processing in neurobiology. Dr. Hasler received the NSF CAREER Award in 2001, and the ONR YIP award in 2002. Dr. Hasler received the Paul Raphorst Best Paper Award, IEEE Electron Devices Society, 1997, Best Paper at CICC 2005, Best Sensors paper at ISCAS 2005, a Best paper award at SCI 2001. Dr. Hasler is a Senior Member of the IEEE. From aecohen at stanford.edu Fri Jan 20 10:08:48 2006 From: aecohen at stanford.edu (Adam E. Cohen) Date: Fri, 20 Jan 2006 10:08:48 -0800 Subject: Trapping Single Molecules (talk announcement) Message-ID: <1137780528.43d127300f3b9@webmail.stanford.edu> Dear Labmembers, I will be giving a talk on my research in the SNF on Monday, Jan 23. All are welcome to attend. Best wishes, Adam 4:15pm, Monday, January 23, Braun Lecture Hall, Mudd Chemistry Building Title: Trapping and manipulating individual molecules in solution Abstract: The Anti-Brownian Electrokinetic trap (ABEL trap) is a new device that allows a user to trap and manipulate individual fluorescent objects as small as ~10 nm in diameter, in solution, at room temperature. The ABEL trap tracks the Brownian motion of a single object using fluorescence microscopy, and then applies a feedback voltage to the solution to induce an electrokinetic drift that exactly cancels this Brownian motion. The ABEL trap has been used to grab, manipulate, and study individual DNA molecules, proteins, viruses, and nanocrystals. The ABEL trap allows precision single-molecule measurements; I will illustrate this with a study of the conformational dynamics of trapped DNA. Current work focuses on trapping ever smaller objects and on developing statistical techniques to glean information on molecular dynamics from the feedback voltages. From mtang at stanford.edu Fri Jan 20 16:20:22 2006 From: mtang at stanford.edu (Mary Tang) Date: Fri, 20 Jan 2006 16:20:22 -0800 Subject: "Red Phone" PA System is out Message-ID: <43D17E46.6000704@stanford.edu> Labmembers -- Please be aware that the PA system, affectionately known as the "Red Phone", is not working. Repair will commence Monday morning. Our apologies, SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From ndhuang at stanford.edu Mon Jan 23 10:54:01 2006 From: ndhuang at stanford.edu (ndhuang) Date: Mon, 23 Jan 2006 10:54:01 -0800 Subject: Help: wafer bonding Message-ID: <00a901c6204e$604d62a0$a7204f86@win.slac.stanford.edu> Dear labmembers, We have some concerns regarding wafer metal-metal bonding. Does anyone have experience of Au-Au or Au-Al bonding, or Au containing eutectic bond? We are interested to keep the pressure and temperature down, since we have Au fine-structures in the order of 10 um that we don't want to collapse. In particular we are interested in a bonding recepie file for Au-? that presumaby worked for someone, such that we don't have to start editing one from scratch. All suggestions are greatly appreciated. Best Regards, Ningdong Huang From mtang at stanford.edu Mon Jan 23 16:13:38 2006 From: mtang at stanford.edu (Mary Tang) Date: Mon, 23 Jan 2006 16:13:38 -0800 Subject: Weighing scale? Message-ID: <43D57132.4040501@stanford.edu> Hi everyone -- Someone seems to have walked off with our nifty little lab scale. This is the one that usually resides in the wafersaw room, next to the hot plate and drill press. Could you PLEASE return it? (And please leave a note the next time you borrow it?) Thanks, Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From kimsangb at stanford.edu Mon Jan 23 17:01:48 2006 From: kimsangb at stanford.edu (SangBum Kim) Date: Mon, 23 Jan 2006 17:01:48 -0800 Subject: ellipsometer for absorbing films Message-ID: <003f01c62081$c0f17f00$a9b50c80@anavel> Dear labmembers, Does anyone have an experience measuring the film thickness using ellipsometer in SNF? The training staff told me that she never used it for absorbing films, but the manual book says that it should work for thin absorbing films in the range of 50~200nm or even 1000nm depending on their extinction coeffecient. (They even have a routine for it.) I tried my GST(Ge2Sb2Te5) wafer, which has refractive index of 4.45 and extinction coefficient of 1.65 at 632.8nm wavelength but it didn't work very well. First of all, the routine program asks about 'order' instead of the 'expected thickness' and I am not sure what 'order' means. Second, when I put 1 for 'order', it gives a thickness around 400~500A regardless of their actual thickness (25~100nm). Any advice would be appreciated regarding this matter. Thanks in advance. SangBum -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Wed Jan 25 11:12:34 2006 From: mbaran at stanford.edu (Maureen Baran) Date: Wed, 25 Jan 2006 11:12:34 -0800 Subject: Keys Found Outside of Lab Message-ID: <200601251912.k0PJCYZ8007853@smtp3.Stanford.EDU> Good Morning Everyone, A set of keys have been found. They have been sitting outside the lab by the computer, all morning. These keys consist of two key holders, one is a green metal loop and the other one is a black leather strip with a sliver metal flower on it. If these sound like your keys please come to my desk. They will be sitting in my in-basket. Thank you, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From guerra at par.stanford.edu Wed Jan 25 15:37:07 2006 From: guerra at par.stanford.edu (Ann Guerra) Date: Wed, 25 Jan 2006 15:37:07 -0800 (PST) Subject: Special Seminar - Aeluros & UCB ISSCC06 presentation Feb. 1 Message-ID: SPECIAL SEMINAR - 3 ISSCC 2006 PRESENTATIONS Wednesday, February 1, 2006 during the weekly Circuits Meeting 2:30 p.m. Paul G. Allen Center for Integrated Systems CIS-101, the Linvill Room _________________________________________________________________________ "An Integrated VCSEL Driver for 10Gb Ethernet in 0.13um CMOS" (13.8) Presenter: Shwe Verma, Aeluros Co-authors: S. Rabii, P. Chau, J. Dao, A. Feldman, H.-J. Liaw, M. Loinaz, M. Lucchas, A. Salleh, S. Sheth, S. Sidiropoulos, and D. Stark Abstract: A 10.3Gb/s VCSEL driver is integrated with a complete Ethernet transceiver in a standard 0.13um CMOS process. When driving a VCSEL differentially, the resulting optical eye exceeds the 10Gb/s Ethernet mask by 35%. Intended for short-reach applications, the driver dissipates 85mW from 1.2V and occupies 0.15mm^2. _________________________________________________________________________ "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13um CMOS" (31.5) Presenter: Mike Chen, U. C. Berkeley Co-author: R. Brodersen Abstract: A 1.2V 6b ADC using asynchronous processing with dual time interleaving and non-binary successive approximation achieves 600MS/s while dissipating 5.3mW in a 0.13um CMOS process. A capacitive ladder network is used to reduce the input capacitance without compromising matching accuracy. The ADC occupies an active area of 0.12mm^2 and has an input 3dB BW of over 4GHz. _________________________________________________________________________ "An Ultra-Low-Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 130nm CMOS with 400mV Supply and an Integrated Passive RX Front-end" (20.5) Presenter: Ben Cook, U. C. Berkeley Co-authors: A. Berny, A. Molnar, S. Lanzisera, and K. Pister Abstract: A 2.4GHz RF transceiver in 130nm CMOS for sensor networks is presented. The transceiver operates from 400mV to accommodate a single solar cell power supply. The RX dissipates 200 to 750uW and achieves a 6.7dB NF and a -6.2dBm IIP3 at 330uW. At 300uW output power, the PA is 44% efficient and the overall TX is 30% efficient. From guerra at par.stanford.edu Wed Jan 25 15:36:57 2006 From: guerra at par.stanford.edu (Ann Guerra) Date: Wed, 25 Jan 2006 15:36:57 -0800 (PST) Subject: THREE Special Seminars coming up - Mark Your Calendar Message-ID: Please watch for email regarding the following THREE separate Special Seminars focusing on ISSCC06: _________________________________________________________________________ WEDNESDAY, Feb. 1, 2:30 p.m., CIS-101 (weekly Circuits Meeting): Shwe Verma, "An Integrated VCSEL Driver for 10-Gigabit Ethernet in 0.13um CMOS," Aeluros S-W (Michael) Chen, "A 6b 600MS/s 5.3 mW Asynchronous ADC in 0.13um CMOS," U.C. Berkeley Ben Cook, "An Ultra-Low-Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 130nm CMOS with 400mV Supply and an Integrated Passive RX Front-end," U. C. Berkeley _________________________________________________________________________ THURSDAY, Feb. 2, 1:00 p.m., CISX-338 - with PIZZA: Bryan Casper, "A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS," Intel, Hillsboro, OR _________________________________________________________________________ FRIDAY, Feb. 3, 10:30 a.m., CIS-101 - PHILIPS, EINDHOVEN, & DELFT UNIV Four presentations followed by informal discussions with those who wish: "A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction" "A 118dB DR CT IF-to-Baseband __ Modulator for AM/FM/IBOC Radio Receivers" "A 13.56MHz RFID System based on Organic Transponders" "A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs" _________________________________________________________________________ From guerra at par.stanford.edu Wed Jan 25 15:37:15 2006 From: guerra at par.stanford.edu (Ann Guerra) Date: Wed, 25 Jan 2006 15:37:15 -0800 (PST) Subject: Special Seminar - INTEL ISSCC06, Feb. 2, and PIZZA Message-ID: SPECIAL SEMINAR - INTEL, Hillosboro, OR, ISSCC 2006 presentation: "A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS" (4.6) Thursday, February 2, 2006 Paul G. Allen Center for Integrated Systems CISX-338 1:00 p.m. - PIZZA will be served Presenter: Bryan Casper Co-authors: James Jaussi, Frank O'Mahony, Mozhgan Mansuri, Karthisha Canagasaby*, Joe Kennedy, Evelina Yeung*, Randy Mooney *Intel, Santa Clara, CA ABSTRACT: A forwarded clock I/O link in 90nm CMOS is capable of passing data at 20Gb/s over 7-inches of FR4 with 2 sockets and packages at a power dissipation of less than 12mW/Gb/s. Passive distribution and AC coupling of the forwarded clock are used to achieve 820fsrms of sample-time uncertainty. Nyquist rate channel losses in excess of -15dB are compensated using a combination of 4-tap transmit equalization and receiver continuous-time equalization. SPEAKER'S BIOGRAPHY: Bryan Casper received the M.S. degree in electrical engineering from Brigham Young University, Provo UT. He is currently a Circuit Researcher with Intel Labs, based in Hillsboro, Ore. In 1998, he joined the Performance Microprocessor Division of Intel Corporation and worked on the development of the Pentium 4 and Xeon processors. For the last 6 years, he has been with Intel Labs and his responsibilities include research, design, validation and characterization of high-speed mixed signal circuits and I/O systems. He has over 60 patents issued or pending. From guerra at par.stanford.edu Wed Jan 25 15:37:23 2006 From: guerra at par.stanford.edu (Ann Guerra) Date: Wed, 25 Jan 2006 15:37:23 -0800 (PST) Subject: SPECIAL SEMINAR - Philips & Delft ISSCC06 - Feb 3 Message-ID: SPECIAL SEMINAR - Philips Research Labs, Eindhoven, and Delft University Four ISSCC 2006 PRESENTATIONS following which the Philips visitors are very interested in engaging in discussion with students Friday, February 3, 2006 10:30 a.m. Paul G. Allen Center for Integrated Systems CIS-101, the Linvill Room _________________________________________________________________________ "A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction" (27.4) M. Snoeij, A. Theuwissen, K. Makinwa, J. Huijsing Abstract: A CMOS imager with a column-level ADC uses a dynamic column FPN reduction technique. This technique requires 5 extra switches per column and minimal digital overhead at the chip level while reducing the perceptual effect of column FPN. Measurements show that the prototype makes a column FPN of 0.67% nearly invisible. _________________________________________________________________________ "A 118dB DR CT IF-to-Baseband DS Modulator for AM/FM/IBOC Radio Receivers (3.3) P. Silva, L. Breems, K. Makinwa, R. Roovers, J. Huijsing Abstract: A 1b 5th-order complex CT DS modulator with integrated IF mixer for AM/FM/IBOC car radio receivers is presented. The 118dB DR in AM mode enables the realization of the receiver without a VGA and an external AM channel filter. It is fabricated in a 0.18um CMOS process and consumes 210mW from a 1.8V supply. _________________________________________________________________________ "A 13.56MHz RFID System based on Organic Transponders" (15.2) E. Cantatore, T. Geuns, A. Gruijthuijsen, G. Gelinck, S. Drews, D. de Leeuw Abstract: RFID tags using organic transistors are described: Two 8b tags carrying different codes, energized and read out at 13.56MHz, the defacto standard for item-level ID, have been tested and demonstrated to enable multiple-object identification for the first time; A 64b tag, the most complex organic transponder reported to date, operates at 125kHz and employs 1938 transistors. _________________________________________________________________________ "A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs" (29.6) V. Petrescu, M. Pelgrom, H. Veendrick, P. Pavithran, J. Wieling Abstract: A fully integrated signal-integrity self-test concept is implemented in a 90nm CMOS process. The outputs of different analog monitors are locally converted to digital form and then transported through a test-compatible scan chain. The temperature monitor has 4b resolution. The supply-noise monitor detects 10ps-wide pulses of 20mV. The total area overhead is <0.1%. From work at dennisnordlund.com Thu Jan 26 18:39:27 2006 From: work at dennisnordlund.com (work at dennisnordlund.com) Date: Thu, 26 Jan 2006 20:39:27 -0600 Subject: Metalica free Message-ID: <1138329567.43d987dfb52cb@mail.opentransfer.com> Metalica is free. Our samples are not ready for Metallica, so I have just cancelled our reservation tonight. I'm very sorry for those who missed the opportunity to deposit tonight due to our reservation. Best, Dennis Dennis Nordlund Postdoctoral Fellow, SSRL From fely at gloworm.Stanford.EDU Fri Jan 27 10:39:50 2006 From: fely at gloworm.Stanford.EDU (Fely Barrera) Date: Fri, 27 Jan 2006 10:39:50 -0800 Subject: EE 310 seminar, January 31, 2006 Message-ID: <200601271839.k0RIdohM015726@gloworm.Stanford.EDU> Title: "Future Directions of Non-Volatile Memory Technologies" Speaker: Al Fazio Intel Fellow Director, Memory Technology Development Time: 4:15 pm - 5:05pm Date: Jan 31, 2006 (tuesday) Place: Hewlett 102 Abstract: Flash memory technology has followed Moore's Law for nine generations and with the introduction of 90 nm technology, moved into the nanotechnology age. In order to meet technology scaling, the mainstream transistor based flash technologies will start evolving to incorporate material and structural innovations. Based on the introduction of material innovations, it is expected that flash memory cell can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future. Further, more complex, structural innovations will be required to maintain further scaling. New memory concepts, not relying on transistors as a basis of the memory cell, provide new opportunities for future low cost memories. Several of these new concepts will be summarized and contrasted with the mainstream transistor based flash memory technologies. Biography: Albert Fazio is an Intel Fellow and Director of Memory Technology Development in the Technology and Manufacturing Group. In his current position, Fazio is responsible for exploring and developing flash memory and multi-level cell memory technologies as well as novel memory technology ideas. Since joining Intel in 1982, Fazio has been involved in various engineering roles in memory development programs including SRAM, EPROM, E2PROM, NVRAM and Flash Memories. His technical contributions and leadership have helped pioneer new capabilities in the area of Flash, Strata-Flash, and Flash and logic combinations, providing cost and functionality advantages to Intel products. Fazio's technical papers have been published in several publications and at international technical conferences. He received outstanding paper awards at the IEEE International Reliability Physics Symposium and IEEE International Solid-State Circuits Conference. Fazio holds 24 patents and has received three Intel Achievement Awards. He frequently serves as a panelist on international memory panels and gives technical seminars and talks to the industry and universities. He previously served as Technical and General Chairman of the IEEE Non-Volatile Semiconductor Memory Workshop. Fazio received his bachelor's of science in Physics from The State University of New York at Stony Brook in 1982. He was born in New York City in 1961. From maryamzm at stanford.edu Fri Jan 27 13:10:42 2006 From: maryamzm at stanford.edu (Maryam Ziaei-Moayyed) Date: Fri, 27 Jan 2006 13:10:42 -0800 Subject: MEMS seminar TODAY at 3pm CISX Aud Message-ID: <1138396242.43da8c524a483@webmail.stanford.edu> Winter 2006 MEMS Seminar When: Friday 1/27/06 3-4 pm Where: CISX Auditorium TITLE: Stiction Force Estimation from Electrical and Optical Measurements on Cantilever Beams SPEAKER: Enakshi BhattacharyaDepartment of Electrical Engineering, Indian Institute of Technology ABSTRACT: An estimate of stiction force, rather than the more commonly reported surface energy, is necessary to design reliable surface micromachined structures where stiction is a major cause of failure. In this work, we discuss the modeling and estimation of the stiction force from simple I-V measurements on cantilever beams that can be carried out even on packaged devices. We also describe a technique to determine stiction force from a cantilever beam array (CBA) that is normally used to estimate the surface adhesive energy. We have fabricated oxide anchored cantilever beams of polysilicon by surface micromachining and measured the pull-in and pull-out voltages. A model for the stiction force was developed in terms of the pull-in and the pull-out voltages both analytically and empirically using the commercial package CoventorWare. This model can be used to estimate stiction force from measured values of pull-in and pull-out voltages and the beam length and does not require the value of Young?s modulus. We also discuss an analytical model developed to calculate the stiction force from the curvature of long collapsed cantilever beams in a cantilever beam array (CBA) to determine process stiction. This requires the value of Young?s modulus that is determined from pull-in measurements on shorter cantilever beams released in the same process. From mjarrahi at stanford.edu Mon Jan 30 11:44:03 2006 From: mjarrahi at stanford.edu (Mona Jarrahi) Date: Mon, 30 Jan 2006 11:44:03 -0800 Subject: BCB (CYCLOTENE 3022-63) Message-ID: <1138650243.43de6c833e08e@webmail.stanford.edu> Hi, There used to be a .8 kilogram, dark amber bottle of BCB (CYCLOTENE 3022-63) with a white label in the yellow cabinet. Also there was another bottle under John Choi's name with 2:1 BCB:T1100. Has anyone seen or used them recently? Thanks, -Mona From amf at amfitzgerald.com Tue Jan 31 18:05:41 2006 From: amf at amfitzgerald.com (Alissa M. Fitzgerald) Date: Tue, 31 Jan 2006 18:05:41 -0800 Subject: "How To Choose Your Foundry Partner" Feb 9, 7pm, Palo Alto, MIT Club of N. CA Semiconductor Entrepreneurship Message-ID: <005001c626d4$018ae580$6401a8c0@minicat> Dear Labmembers, Please see below for an event of general interest... *this event is open to the public* Best regards, Alissa _____ From: MITCNC [mailto:mitcnc at en25.com] Sent: Saturday, January 28, 2006 11:50 AM To: amf at amfitzgerald.com Subject: MITCNC EVENT: How To Choose Foundry; Feb.09, 7pm, Palo Alto Click here if your email program has trouble displaying this email The MIT Club of Northern California Semiconductor Entrepreneurship Series presents: How to choose your Foundry Partner Date: February 9th, 2006 Thursday Event Time: 7pm (6:30 networking) Venue: Cooley Godward LLP - Hanover St. Campus Location: 3175 Hanover Street, Palo Alto [directions] Cost: $20 preregistration/$30 at the door (includes food/beverage) Online registration at: http://www.mitcnc.org/Events_Single.asp?eventID=1199 Contact: kashyap_sunil at yahoo.com Gone are the days when chip designers could hand over their design to a foundry and expect good yields. Nowadays, to achieve predictable yields, designers must weigh device manufacturability against chip performance. This phenomenon has resulted in multiple collaborations among different sectors of the chip industry. Over the last year we have focused on how EDA tools and services are helping bridge the gap between design and manufacturing. Given the difficulty of changing from one foundry to another, it is all the more important that a fabless semiconductor company choose its partner wisely. This event will feature a panel discussion focusing on how a fabless startup should approach making this critical decision. The panel will consist of people with first-hand experience in selecting a foundry partner and negotiating and implementing such deals. Topics to be examined in more detail include: 7 Key factors in evaluating foundries and picking a partner 7 Things to look for beyond technological capability 7 Given the high switching cost (especially for cutting edge technology), what to do when the relationship with the foundry partner falters 7 Under what circumstances is a US foundry preferable? 7 Do all roads lead to TSMC? Panelists: 1. Rich Redelfs, Venture Partner, Foundation Capital Ex-CEO of Atheros Rich joined Foundation Capital after 20+ years in networking and communications, a combination of start-up entrepreneurial as well as large company intrapreneurial experience. Most recently, he was president and CEO of Atheros Communications (NASDAQ: ATHR) which he joined as a start-up with 21 engineers and an office manager. He built the company into the leading provider of Wi-Fi wireless semiconductors. Rich has an MBA from Harvard Business School and a BSIE from Purdue. 2. Markus Lutz, COO and Executive VP, SiTime Mr. Lutz is the initial inventor of InChipMEMS technology, which allows vacuum-sealed MEMS structures to be manufactured in ultra-pure wafer cavities with integrated CMOS and shipped in low-cost industry standard packages. SiTime is using this key intellectual property to bring to market the lowest cost, high performance resonators and oscillators, which are 1/8th the size of leading-edge competitive timing devices. Mr. Lutz received his Diplom Ingenieur Elektrotechnik at the Technical University of Munich in 1992. He started his career at Robert Bosch GmbH in Reutlingen, Germany, where over 4 years he invented and managed the development of Bosch's first silicon based MEMS gyroscope, now a $200M/year business. Markus holds 35 patents, authored and co-authored 14 publications. 3. Marco Zuniga, Vice President of IC Technology and Process Development, Volterra Marco Zuniga co-founded Volterra and has been Volterras Vice President of IC Technology and Process Development since July 2004. Dr. Zuniga holds a B.S.E.E. from the University of Texas at Austin, and an M.S.E.E. and Ph.D. in electrical engineering from the University of California at Berkeley. 4. Michael Buehler-Garcia, Managing Director, Alanza Technologies Alanza Technologies is a consulting company for semiconductor markets. Michael has worked throughout the semiconductor industry; as an executive at multinational corporations such as Chartered Semiconductor, Cadence Design Systems, and Motorola; in addition to working at emerging companies such as PDF Solutions and iRoC Technologies, one of the leaders in soft error solutions. 5. Dipak Shah, VP of Engineering, Xambala A seasoned entrepreneur and industry veteran with 24+ years of engineering, design, development and general management experience for networking and telecom semiconductor components including high performance switch fabric chip sets, ATM SARs, Mutiport Ethernet switch chip sets and Ethernet PHY products. He was previously founder and CEO of PetaSwitch, a Switch Fabrics solutions startup. He held various senior management positions at HotRail which was subsequently acquired by Connexant and Silicon Dynamics. He holds BSEE, MSEE degrees and multiple patents for various data communication applications. Moderator: Arati Prabhakar, Partner, USVP Arati Prabhakar joined U.S. Venture Partners in 2001 after 15 years of working with world-class engineers and scientists across many fields to brew new technologies. At USVP, her focus is fabless semiconductor and semiconductor manufacturing opportunities. She serves on the boards of Leadis Technology (NASDAQ: LDIS), Kleer, SiBeam, Pivotal Systems, Arradiance, and Kilopass. Arati was a program manager and then director of the Microelectronics Technology Office at DARPA from 1986 to 1993. In 1993, President Clinton appointed Arati Director of the National Institute of Standards and Technology, where she led the 3,000 person staff until 1997. Arati then joined Raychem as Senior Vice President and Chief Technology Officer. Arati serves on advisory committees for Stanford, Berkeley, Caltech, and UC Santa Barbara. She is a Fellow of the IEEE. Arati received her B.S. in Electrical Engineering from Texas Tech University. She received an M.S. in Electrical Engineering and a Ph.D. in Applied Physics from the California Institute of Technology. About the Event Series: The MIT Semiconductor Entrepreneurship Series is a resource for those interested in founding, funding and growing new ventures in the area of semiconductor design and manufacturing. The series provides: - a venue for networking amongst entrepreneurs and other interested professionals - opportunities for entrepreneurs to meet leaders in the industry and learn from their experiences - perspectives from analysts and investors regarding opportunities for starting new ventures Events are normally held at 7pm on the second Thursday of the month at Cooley Godward in Palo Alto, and feature a refreshments and networking session, followed by a panel discussion or keynote presentation. The series is open to the public. Since its founding in 2002, the Semiconductor Entrepreneurship Series has attracted a growing community of attendees drawn from semiconductor design and manufacturing, including independent entrepreneurs and consultants to the industry, as well as legal, investment, and market research professionals. To see descriptions of recent events, please visit: http://www.mitcnc.org/Entrepreneurship_Semiconductor.htm Please click here to unsubscribe -------------- next part -------------- An HTML attachment was scrubbed... URL: