SPECIAL SEMINAR - 40Gb/s Serial Link, Jan 9, 2006

Ann Guerra guerra at par.stanford.edu
Thu Jan 5 10:58:02 PST 2006


"Design of Low-Cost Package for 40-Gb/s Serial Link
using Wire-Bonded PBGA"

Dong Gun Kam
KAIST (Korea Advanced Institute of Science and Technology)

Monday, January 9, 2006
11:00 a.m.


Recently the performance of high-speed chip-to-chip serial links has been
limited by the bandwidth of a package. A 40 Gb/s packaging solution that
uses low-cost wire-bonded plastic ball grid array (WB-PBGA) technology is
presented. Since such a high speed is well beyond the reach of
conventional package designs, the new design methodologies including the
discontinuity cancellation of signal current paths and the supply of
low-inductance return current paths are proposed. The design methods of
bonding wires, vias, solder ball pads, and power distribution networks are
suggested. The proposed design methodologies and packaging solution are
verified with simulation and measurement. By avoiding the use of low-loss
dielectric materials and/or advanced packaging technology, the result can
be the lowest cost packaging solution for future high-speed serial links.
Although our consideration in this research is limited to WB-PBGA
packages, the proposed design methodologies can be readily applied to
advanced packaging technology providing further improvement of channel

Mr. Dong Gun Kam will be receiving his doctorate from KAIST in July 2006
on high-speed interconnection and package design with emphasis on signal
integrity, power integrity and EMI/EMC, under Prof. Joungho Kim.  He will
be presenting his work this year at PIERS in Cambridge, MA, in March and
at ECTC in San Diego in May.

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