Special Seminar - INTEL ISSCC06, Feb. 2, and PIZZA

Ann Guerra guerra at par.stanford.edu
Wed Jan 25 15:37:15 PST 2006

SPECIAL SEMINAR - INTEL, Hillosboro, OR, ISSCC 2006 presentation:

"A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS" (4.6)

Thursday, February 2, 2006
Paul G. Allen Center for Integrated Systems

1:00 p.m. - PIZZA will be served

Presenter:  Bryan Casper
Co-authors:  James Jaussi, Frank O'Mahony, Mozhgan Mansuri, Karthisha
Canagasaby*, Joe Kennedy, Evelina Yeung*, Randy Mooney
*Intel, Santa Clara, CA

A forwarded clock I/O link in 90nm CMOS is capable of passing data at
20Gb/s over 7-inches of FR4 with 2 sockets and packages at a power
dissipation of less than 12mW/Gb/s. Passive distribution and AC coupling
of the forwarded clock are used to achieve 820fsrms of sample-time
uncertainty. Nyquist rate channel losses in excess of -15dB are
compensated using a combination of 4-tap transmit equalization and
receiver continuous-time equalization.

Bryan Casper received the M.S. degree in electrical engineering from
Brigham Young University, Provo UT. He is currently a Circuit Researcher
with Intel Labs, based in Hillsboro, Ore. In 1998, he joined the
Performance Microprocessor Division of Intel Corporation and worked on
the development of the Pentium 4 and Xeon processors. For the last 6
years, he has been with Intel Labs and his responsibilities include
research, design, validation and characterization of high-speed mixed
signal circuits and I/O systems. He has over 60 patents issued or

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