SPECIAL SEMINAR - Philips & Delft ISSCC06 - Feb 3

Ann Guerra guerra at par.stanford.edu
Wed Jan 25 15:37:23 PST 2006


SPECIAL SEMINAR - Philips Research Labs, Eindhoven, and Delft University

Four ISSCC 2006 PRESENTATIONS
following which the Philips visitors are very interested in engaging in
discussion with students

Friday, February 3, 2006
10:30 a.m.
Paul G. Allen Center for Integrated Systems
CIS-101, the Linvill Room

_________________________________________________________________________

"A CMOS Imager with Column-Level ADC Using Dynamic Column FPN
Reduction" (27.4)

M. Snoeij, A. Theuwissen, K. Makinwa, J. Huijsing

Abstract:
A CMOS imager with a column-level ADC uses a dynamic column FPN reduction
technique. This technique requires 5 extra switches per column and minimal
digital overhead at the chip level while reducing the perceptual effect of
column FPN. Measurements show that the prototype makes a column FPN of 0.67%
nearly invisible.
_________________________________________________________________________

"A 118dB DR CT IF-to-Baseband DS Modulator for AM/FM/IBOC Radio
Receivers (3.3)

P. Silva, L. Breems, K. Makinwa, R. Roovers, J. Huijsing

Abstract:
A 1b 5th-order complex CT DS modulator with integrated IF mixer for
AM/FM/IBOC car radio receivers is presented. The 118dB DR in AM mode
enables the realization of the receiver without a VGA and an external AM
channel filter. It is fabricated in a 0.18um CMOS process and consumes
210mW from a 1.8V supply.
_________________________________________________________________________

"A 13.56MHz RFID System based on Organic Transponders" (15.2)

E. Cantatore, T. Geuns, A. Gruijthuijsen, G. Gelinck, S. Drews,
D. de Leeuw

Abstract:
RFID tags using organic transistors are described: Two 8b tags carrying
different codes, energized and read out at 13.56MHz, the defacto standard
for item-level ID, have been tested and demonstrated to enable
multiple-object identification for the first time; A 64b tag, the most
complex organic transponder reported to date, operates at 125kHz and
employs 1938 transistors.
_________________________________________________________________________

"A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs"
(29.6)

V. Petrescu, M. Pelgrom, H. Veendrick, P. Pavithran, J. Wieling

Abstract:
A fully integrated signal-integrity self-test concept is implemented in a
90nm CMOS process. The outputs of different analog monitors are locally
converted to digital form and then transported through a test-compatible
scan chain. The temperature monitor has 4b resolution. The supply-noise
monitor detects 10ps-wide pulses of 20mV. The total area overhead is
<0.1%.




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