EE 310 seminar, January 31, 2006

[Fely Barrera]

Title:
"Future Directions of Non-Volatile Memory Technologies"

Speaker:
Al Fazio
Intel Fellow
Director, Memory Technology Development

Time: 4:15 pm - 5:05pm
Date: Jan 31, 2006 (tuesday)
Place: Hewlett 102

Abstract:
Flash memory technology has followed Moore's Law for nine generations and 
with the introduction of 90 nm technology, moved into the nanotechnology 
age. In order to meet technology scaling, the mainstream transistor based 
flash technologies will start evolving to incorporate material and 
structural innovations. Based on the introduction of material innovations, 
it is expected that flash memory cell can scale through at least the end of 
the decade (2010) using techniques that are available today or projected to 
be available in the near future. Further, more complex, structural 
innovations will be required to maintain further scaling. New memory 
concepts, not relying on transistors as a basis of the memory cell, provide 
new opportunities for future low cost memories. Several of these new 
concepts will be summarized and contrasted with the mainstream transistor 
based flash memory technologies.

Biography:

Albert Fazio is an Intel Fellow and Director of Memory Technology 
Development in the Technology and Manufacturing Group. In his current 
position, Fazio is responsible for exploring and developing flash memory 
and multi-level cell memory technologies as well as novel memory technology 
ideas.

Since joining Intel in 1982, Fazio has been involved in various engineering 
roles in memory development programs including SRAM, EPROM, E2PROM, NVRAM 
and Flash Memories. His technical contributions and leadership have helped 
pioneer new capabilities in the area of Flash, Strata-Flash, and Flash and 
logic combinations, providing cost and functionality advantages to Intel 
products.

Fazio's technical papers have been published in several publications and at 
international technical conferences. He received outstanding paper awards 
at the IEEE International Reliability Physics Symposium and IEEE 
International Solid-State Circuits Conference. Fazio holds 24 patents and 
has received three Intel Achievement Awards. He frequently serves as a 
panelist on international memory panels and gives technical seminars and 
talks to the industry and universities. He previously served as Technical 
and General Chairman of the IEEE Non-Volatile Semiconductor Memory Workshop.
Fazio received his bachelor's of science in Physics from The State 
University of New York at Stony Brook in 1982. He was born in New York City 
in 1961.