From mtang at stanford.edu Wed Jul 5 10:28:43 2006 From: mtang at stanford.edu (Mary Tang) Date: Wed, 05 Jul 2006 10:28:43 -0700 Subject: Nanoimprint Technology Seminar, Friday, July 14, 2 pm Message-ID: <44ABF6CB.5050208@stanford.edu> Greetings labmembers: Theodor Nielson, from NIL Technology, will be presenting a seminar on nanoimprint. His abstract and bio are appended here. The seminar will be held on Friday, July 14, at 2pm in CIS 101 (Linvill Conference Room.) ******************************************************** NIL Technology seminar at SNF July 2004 Nanoimprint lithography (NIL) is a parallel process lithography technique capable of replicating structures with the same precision as electron beam lithography (EBL). NIL is appointed to be a potential candidate for future use in the semiconductor industry. However, many other fields might benefit from NIL already today ? which will be the focus of this seminar. Different NIL approaches are possible (UV-NIL and Thermal NIL) and an overview will be given together with the motivation for these. The latest results and inventions within NIL will be presented with focus on examples of novel applications fabricated/realized by NIL and examples of the use of NIL in volume production. An introduction to the NIL processing understanding will be given, addressing the issues of polymer flow, aligning, stamp bending, choice of stamp material, large area imprinting, imprint materials, etc. Theodor Nielsen has a M. Sc. E. degree in Applied Physics from the Technical University of Denmark (DTU). Theodor has been working with nanoimprint lithography for 5 years. During his masters and PhD studies he had several publications within nanoimprint lithography (NIL) and lab-on-a-chip applications realized by NIL. Theodor has currently take a leave from the PhD studies to start the company NIL Technology. NIL Technology fabricates and sells stamps (templates) for nanoimprint lithography. The stamps can be designed with patterns below 20 nm in various materials, e.g. Silicon, Quartz, Nickel or polymers. NIL Technology comprises a patent pending technology to fabricate Silicon stamps for full wafer scale imprints. Any interested companies are welcome to contact NIL Technology in order to set up a meeting in California 15-19 July or visit us during SEMICON West 11-13 July in Moscone Convention Center, San Francisco, booth number 144. -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From uyoon at stanford.edu Wed Jul 5 15:47:26 2006 From: uyoon at stanford.edu (Uija Yoon) Date: Wed, 5 Jul 2006 15:47:26 -0700 Subject: Missing system disk from Ultratech1 Message-ID: <008b01c6a084$fd16e0a0$0100000a@Mimie> Hi all, Ultratech 1 SYSTEM OPERATING DISK is missing. If anyone has the disk by mistake, please return it. Thank you. Uija -------------- next part -------------- An HTML attachment was scrubbed... URL: From jerabek at snf.stanford.edu Wed Jul 5 16:06:23 2006 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Wed, 5 Jul 2006 16:06:23 -0700 (PDT) Subject: LRS18 Laser mask writer Message-ID: To whom it may concern: Laser mask writer has a severe orthogonality error (~40um across 5"plate) due to mechanical shift of one of the interferometer mirrors. This is a serious problem which may take some time to correct. Masks written in this condition are only useable on a contact printer provided one does only a front side lithography. These mask are not going to align to the masks written before June 23rd 06 or written after a correction is made. I do not know how this effects Nikon or Ultratech masks as I so far did not get any feedback. I believe the Nikon will surely detect this error during initial reticle alignment. People who have masks requests in the que should let me know ASAP if they want me to proceed (with the constrains stated above) and make their masks. Micronic field service has been notified. -Paul P.S. mirror shift happened on June 23rd when field service was changing data cable to the writing head. This operation requires removal of the stage including the mirrors. From pruitt at stanford.edu Wed Jul 5 18:44:33 2006 From: pruitt at stanford.edu (Beth Pruitt) Date: Wed, 5 Jul 2006 18:44:33 -0700 Subject: Fwd: seminar Aaron Partridge of SiTime 7/6 4:30pm Message-ID: > >Dr. Aaron Partridge of SiTime will be speaking tomorrow (Thursday >7/6) on silicon oscillators and their path to commercialization in >ME342 at 4:30 in 530-127. > >next Thursday is Dr. Alissa Fitzgerald of AMF Consulting on MEMS reliability. > >me342.stanford.edu From mager at stanford.edu Wed Jul 5 17:20:24 2006 From: mager at stanford.edu (Morgan Mager) Date: Wed, 5 Jul 2006 17:20:24 -0700 Subject: SU-8 adhesion problems Message-ID: <1152145224.44ac5748d369a@webmail.stanford.edu> Hi, I'm having some problems spinning SU-8 and was hoping someone could offer advice. My surface is SiO2 (thermal oxide) with a few small gold lines. I clean the wafers with a chemical photoresist strip, rinse, 200C dehydration bake, then 20min UV ozone clean. I'm using the 2 micron formulation of SU-8 and spinning at 2500rpm. When I examine the wafer afterward, there are pinholes where the resist has pulled back while drying. Has anyone else experienced this? Is there a better way to prepare the surface? Thanks in advance. -Morgan From mahnaz at snf.stanford.edu Thu Jul 6 09:33:33 2006 From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour) Date: Thu, 06 Jul 2006 09:33:33 -0700 Subject: [Fwd: Bonder/aligner] Message-ID: <44AD3B5D.5030102@snf.stanford.edu> -------- Original Message -------- Subject: Bonder/aligner Date: Fri, 30 Jun 2006 17:24:03 -0700 From: Mahnaz Mansourpour Organization: SNF To: Lab Hello all, There will be a presentation on the EVG bonder on Thursday July 6th given by Chad Brubaker at 10 am in the lab, if you need bond training please attend the session. If you need to discuss your process or have any questions please come by as well. The aligner training will be at 2 pm same day in the lab. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From pickard at stanford.edu Thu Jul 6 11:00:36 2006 From: pickard at stanford.edu (Dan Pickard) Date: Thu, 6 Jul 2006 11:00:36 -0700 Subject: Lost Earphones/plugs Message-ID: <1152208836.44ad4fc4911de@webmail.stanford.edu> If you found a pair of In-Ear Earphones please contact me. They were lost Wednesday afternoon, July 5th. They are an "in the ear" style with beige foam inserts and a clear plastic body. They have black braided wires. Thanks, Dan My appologies to those who are on both mailing lists... From jonroth at stanford.edu Fri Jul 7 03:54:20 2006 From: jonroth at stanford.edu (Jonathan Edgar Roth) Date: Fri, 7 Jul 2006 03:54:20 -0700 Subject: Removal of In from InP? Message-ID: <1152269660.44ae3d5cb3570@webmail.stanford.edu> Dear labmembers, I have an urgent need to evenly remove Indium solder from an InP wafer. I desire an optically flat surface afterwards. I've had some success heating the wafer to ~150'C on a hot plate and wiping the indium off quickly with a wipe, but there's quite a bit of residue left. Perhaps this could be removed with a wet or dry etch, if a selective one exists. Any advice or suggestions would be appreciated. Jon Roth From mtang at stanford.edu Fri Jul 7 12:55:01 2006 From: mtang at stanford.edu (Mary Tang) Date: Fri, 07 Jul 2006 12:55:01 -0700 Subject: Process Grand Rounds #2 Message-ID: <44AEBC15.1070708@stanford.edu> Hi all -- You are invited to the second edition of the Process Grand Rounds, where you get to review other labmembers' process, offer your advice and suggestions, and maybe learn a tip or two along the way. This Process Grand Round is scheduled for next Thursday, July 13 and will be held at noon in CISX-338 (other side of the building, third floor, across from the elevator.) For this session, we have three volunteers from ME342 who would like to test drive their ideas before your very eyes. Please RSVP by 9 am Thursday morning for pizza. Hope to see you there! Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From jerabek at snf.stanford.edu Fri Jul 7 14:44:28 2006 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Fri, 7 Jul 2006 14:44:28 -0700 (PDT) Subject: maskwriter update Message-ID: I have seen misalignment on the mask(s) in question during Karl Suss exposure. It's gross. However I have written a test mask with a large (max.size) cross and tried to measure ortho error using Hitachi ebeam optical comparator (very precise but not too handy for measuring masks). I came up with an error of 1 to 2um at the extremes (as opossed to about 80um on Karl Suss exposure). Big difference. Another user tried a Nikon mask from the same lot and reticle was accepted on a second try(inconclusive, could be Nikon acting up). So I have designed a simple test mask which I'm writing just now and will send it to an outside vendor (probably Compugraphics) to have them measure ortho deviation to find out if we have a problem or not and if so how big. -Paul From vigneshg at stanford.edu Sat Jul 8 12:52:18 2006 From: vigneshg at stanford.edu (Vignesh G) Date: Sat, 08 Jul 2006 12:52:18 -0700 Subject: Dry removal of native oxide (Si) without HF? Message-ID: <6.2.5.6.2.20060708124745.0458d600@stanford.edu> Hi all, Does anybody know how to remove the native oxide off Si (and leave a bare Si surface) using a dry etch? A selective etch is preferable - something that etches the oxide but not Si. A wet etch using HF does not work for me. Thanks. - Vignesh. From jerabek at snf.stanford.edu Mon Jul 10 17:07:51 2006 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Mon, 10 Jul 2006 17:07:51 -0700 (PDT) Subject: mask writer Message-ID: Today I have finished processing of a "ortho test mask" and hand delivered to Compugraphics to measure. Once I get a result back we will know where we stand with the writer. -Paul From rcrane at stanford.edu Tue Jul 11 09:12:07 2006 From: rcrane at stanford.edu (Dick Crane) Date: Tue, 11 Jul 2006 09:12:07 -0700 Subject: Tuesday's fire alarm Message-ID: <44B3CDD7.4090309@stanford.edu> CIS/CISX and lab dwellers, At approximately 0830 this morning, Tuesday, 7/11/06, CIS/CISX experienced a fire/evacuation alarm. This was a false alarm which occurred when an HVAC transfer fan in CISX 2nd was returned to service after maintenance. A smoke detector in the duct tripped for unknown reasons. The detector in being checked presently. All gas systems were reset following the fire department clearing the alarm. Sorry for the false alarm, but thank you for having an orderly evacuation. Dick Crane From rcrane at stanford.edu Tue Jul 11 10:24:47 2006 From: rcrane at stanford.edu (Dick Crane) Date: Tue, 11 Jul 2006 10:24:47 -0700 Subject: HEPA air going down in EPI/Metalica area Message-ID: <44B3DEDF.1000302@stanford.edu> Labusers: The HEPA filter air transfer fan servicing the west end of the L109 aisle (ASM epi, Metalica, AG210s, STSetchers) has suffered a main shaft bearing failure. Fac/ops is shutting it down immediately. The fan should be back on-line within two days. This shutdown will cause poorer temperature control and higher particle counts in the area. Sorry for any inconvenience, Dick From mtang at stanford.edu Tue Jul 11 13:05:27 2006 From: mtang at stanford.edu (Mary Tang) Date: Tue, 11 Jul 2006 13:05:27 -0700 Subject: Reminder: Process Grand Rounds #2 at noon on Thursday, 7/13 Message-ID: <44B40487.5020009@stanford.edu> Hi all -- Just a reminder of the next Process Grand Rounds scheduled for Thursday, July 13 at noon in CISX-338 (other side of the building, third floor, across from the elevator.) For this session, we have three volunteers from ME342 who would like to test drive their ideas before your very eyes. All labmembers are welcome. Please RSVP by 9 am Thursday morning for pizza. Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From andylin at gmail.com Tue Jul 11 16:28:23 2006 From: andylin at gmail.com (Andy Y. Lin) Date: Tue, 11 Jul 2006 16:28:23 -0700 Subject: Vendors for Si3N4-passivated Si wafers? Message-ID: Hi everyone, I'm looking for vendors that sell 3" Si3N4-passivated Si wafers. If you know of any, please let me know. Thanks! -- Andy Y. Lin Stanford Graduate Fellow (Mayfield Fellow), MSE PhD MIT B.S. '05, Materials Science and Engineering -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Wed Jul 12 07:35:37 2006 From: mtang at stanford.edu (Mary Tang) Date: Wed, 12 Jul 2006 07:35:37 -0700 Subject: Coral Down this morning Message-ID: <44B508B9.1040006@stanford.edu> Labmembers -- We're very sorrry to say that Coral is still hicupping from last night (and apologies for not sending an email out last night -- the emailer was also affected at that time.) The lab is otherwise still open for business. Until the Coral team figures out what's wrong, we will be running without Coral. If you need a piece of equipment enabled, please contact Mario, who has the power to enable any tool in the lab. We'll rely on the honor system: do not use any equipment for which you are not already qualified and please try to honor other's reservations as best as you can recall them. Deepest apologies for the inconvenience. Please consider this "free" time in the lab. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Wed Jul 12 09:57:37 2006 From: mtang at stanford.edu (Mary Tang) Date: Wed, 12 Jul 2006 09:57:37 -0700 Subject: Coral is UP!!! Message-ID: <44B52A01.6070602@stanford.edu> Greetings! Coral is back up and running. We deeply apologize for the inconvenience. If there are further disruptions to Coral service, please let a staff member know as soon as possible. If it is after-hours or on a weekend, please send an email to the Coral Development team (coral at snf). Please also copy on the email the following people: Paul Rissman (rissman), Mary Tang (mtang), Dick Crane (dcrane) or Ed Myers (emyers) using the @stanford.edu address (not the snf at stanford.edu address.) Between all of us, we should hopefully be able to respond in a way that should tide us over until John returns. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From jerabek at snf.stanford.edu Thu Jul 13 08:26:55 2006 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Thu, 13 Jul 2006 08:26:55 -0700 (PDT) Subject: mask writer Message-ID: To whom it may concern: we did get results of measurement of "ortho mask" back from an outside company which indicated an ortho error of 3.7urad. Micronic made an adjustment to the ortho parameter in the machine parameter tables. I have written a mask for Steve Zhuang which should align to his previous layers. However he is seeing the same error as before, so right now it's back to square one. -Paul From mcvittie at cis.Stanford.EDU Thu Jul 13 09:17:34 2006 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Thu, 13 Jul 2006 09:17:34 -0700 (PDT) Subject: PEUG July 20, 2006, Meeting Message-ID: You are all invited to the Plasam Users Group Meeting to be held next Thursday afternoon (July 20) in Sunnyvale. It is free. ******************************* NCCAVS PEUG User Groups July Meeting Announcement NO NEED TO REGISTER - JUST SHOW UP!! Session Topic: Frontend Dielectric Etch Sponsored By: Advanced Energy, Inc., www.advanced-energy.com Chair: Shawming Ma, Applied Materials, shawming_ma at amat.com Date: July 20, 2006 Time: 2:00-5:00pm Location: National Semiconductor 955 Kifer Rd. Sunnyvale, CA DIRECTIONS: >From 101: Go south on Lawrence Expressway. Turn right on Kifer Rd. Turn right into the driveway of the National Semiconductor Auditorium (955 Kifer Rd.) and find parking in the rear parking lot. The auditorium is on the West Side of the building and can be entered from the door in the rear next to the company park. >From 280: Go north on Lawrence Expressway. Turn left on Kifer Rd. Follow directions above. AGENDA: 2:00 - 2:20 pm Refreshments 2:20- 2:30 pm PEUG Business Meeting 2:30 - 5:00 pm Presentations 1. "Control of Contact Hole Distortion by Using Polymer Deposition Process (PDP) for sub-65nm Technology and Beyond," Judy Wang, Shing-li Sung, Shawming Ma, Bryan Pu, Brian Shieh Applied Materials Inc., Dielectric Etch Division Contact hole distortion in dielectric etching was investigated and it has been found that the contact hole distortion is mainly caused by low mask selectivity, poor mask surface control (roughness, striation, pitting or pin hole) before and after etching. The surface roughness and mask selectivity have been studied to overcome the problem of pattern deformation of PR and C-rich materials as the mask. By using the polymer deposition process (PDP), the mask degradation is improved and the contact profile is been well controlled. This paper focus on the discussion on PDP chemistry selection, PDP time decision, and PDP used at before or after BARC open step. 2. "Etch Processes for Nano-scale vertical MOS Devices," Hoon Cho, Pawan Kapur and Krishna C. Saraswat Department of Electrical Engineering, Stanford University,CA Vertical double gate and tri gate MOSFETs have been researched aggressively in the recent years as potential candidates for sub 45nm technology nodes. In this talk, we will show etch processes for a spacer process capable of fabricating vertical MOS devices down to thickness as low as 5nm. This spacer process uses silicon-nitride (Si3N4) as the hard mask spacer, which is formed using a polysilicon block. 3. "Integrated CD Shrink Methodologies for Contact Etch," Scott Allen*, Kang-lie Chiang**, Rich Wise*, Nikki Edleman*, TjinTjin Tjoa***, Judy Wang**, Melody Chang** and Shawming Ma** * IBM Systems and Technology, Hopewell Junction, NY ** Etch PBG, Applied Materials, Sunnyvale, CA *** Chartered, Hopewell Junction, NY CD shrink in via etch processes are required to alleviate lithographic limitations in meeting design ground rules for 65nm and beyond by Resist trim techniques and Tapering of a sacrificial masking material. Resist mask thicknesses will be scaled down continually due to reduced depth of field, therefore, requiring Highly selective etch process and Control of micro-loading, Profile, Line edge roughness and Uniformity This talk will focus on different CD reduction methodologies for Contact Etch developed jointly by IBM and Applied Materials. ********************************************************** Future Meetings: October 12-MEMS, submit abstracts to: Lucia Feng, lmfeng at earthlink.net or Jim McVittie, jmcvittie at stanford.edu ********************************************************** NCCAVS User Group website: www.avsusergroups.org Find: Meeting Schedules, Announcements, Call for Papers, Committee Contact Information, Proceedings from monthly meetings and more. Sign up for a User Group: www.avsusergroups.org *********************************************************** __________________________ Heather Korff Events/Office Coordinator AVS 110 Yellowstone Dr., Suite 120 Chico CA 95973 Phone: 530-896-0477 Fax: 530-896-0487 E-mail: heather at avs.org Web: www.avs.org From mtang at stanford.edu Fri Jul 14 11:10:14 2006 From: mtang at stanford.edu (Mary Tang) Date: Fri, 14 Jul 2006 11:10:14 -0700 Subject: Maskmaking outside SNF Message-ID: <44B7DE06.6060503@stanford.edu> Hi everyone -- A number of people have asked about maskmaking services outside of SNF. Here's a webpage which links to descriptions of various internal and external services: http://snf.stanford.edu/Process/Masks/Masks.html Compugraphics provides high precision masks -- services and prices for 2006 have just been posted. For simpler, lower resolution masks with a single or very few layers, you can contact other services listed. (Remember, you pretty much get what you pay for, so it's worthwhile to think about your process resolution needs relative to cost.) If you have any other tips or tricks regarding masks or mask design resources, please do share them! Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Fri Jul 14 12:40:04 2006 From: mtang at stanford.edu (Mary Tang) Date: Fri, 14 Jul 2006 12:40:04 -0700 Subject: Reminder: Nanoimprint seminar: 7/14/06, 2 pm, CIS 101 Message-ID: <44B7F314.1030600@stanford.edu> Hi everyone -- Just a reminder that Theodor Nielsen from NIL Technology will be here at 2 pm for a general technical talk about nanoimprint technologies. This will be in CIS 101 at 2 pm. For abstract and bio, see http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:2306:200607:ffcnpncflfhejhgbkdad Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From lperlson at stanford.edu Fri Jul 14 13:48:37 2006 From: lperlson at stanford.edu (Lisa Perlson) Date: Fri, 14 Jul 2006 13:48:37 -0700 Subject: Si <111> wafers Message-ID: <7.0.1.0.0.20060714134406.01910d60@stanford.edu> Hi, I am in the chemistry department, and I am looking for some Si <111> wafers. I'd rather not buy a whole cassette from a company because I only need 2 or 3. Does anyone have a few wafers around that you would be able to sell or give to me? Thanks! ~Lisa Perlson From beinnmuir at stanford.edu Fri Jul 14 19:01:17 2006 From: beinnmuir at stanford.edu (Beinn Muir) Date: Fri, 14 Jul 2006 19:01:17 -0700 Subject: STS PECVD SiOx Properties Message-ID: <1152928877.44b84c6da1d04@webmail.stanford.edu> Hi Labmembers, Does anyone know approximate values for the heat capacity and thermal conductivity for STS PECVD deposited SiOx films? In particular I am interested in 100-200 nm thick films. Thanks, Beinn... From jerabek at snf.stanford.edu Sat Jul 15 09:23:33 2006 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Sat, 15 Jul 2006 09:23:33 -0700 (PDT) Subject: failure notice (fwd) Message-ID: ---------- Forwarded message ---------- Date: 15 Jul 2006 16:19:33 -0000 From: MAILER-DAEMON at snf.stanford.edu To: jerabek at snf.stanford.edu Subject: failure notice Hi. This is the qmail-send program at snf.stanford.edu. I'm afraid I wasn't able to deliver your message to the following addresses. This is a permanent error; I've given up. Sorry it didn't work out. : 171.67.20.25 does not like recipient. Remote host said: 550 : Recipient address rejected: User unknown in local recipient table Giving up on 171.67.20.25. --- Below this line is a copy of the message. Return-Path: Received: (qmail 14917 invoked by uid 20233); 15 Jul 2006 16:19:28 -0000 Received: from localhost (sendmail-bs at 127.0.0.1) by localhost with SMTP; 15 Jul 2006 16:19:28 -0000 Date: Sat, 15 Jul 2006 09:19:28 -0700 (PDT) From: Paul Jerabek To: labmembers at stanford.edu Subject: mask writer status Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII To whom it may concern: the error in orthogonality turned out to be 1400urad which amounts to 140um over 100000um distance. Very large error. Micronic service tried to plug that number into machine parameter for ortho correction but the value is too large. Maximum correction the machine software will accept is 999urads. With this number in parameters error improved to about 30um which of course doesn't help matters much. It might as well be a 5 miles. What it means is that Micronic field service will have to mechanicaly readjust a position of the interferometer mirror(s) and it looks like the local field service doesn't have an expertise and tools to do that so they will have to bring in someone from homeoffice in Sweden. -Paul From jerabek at snf.stanford.edu Sat Jul 15 10:23:04 2006 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Sat, 15 Jul 2006 10:23:04 -0700 Subject: mask writer Message-ID: <001301c6a833$55301210$916540ab@czech1> To whom it may concern: the error in orthogonality turned out to be 1400urad which amounts to 140um over 100000um distance. Very large error. Micronic service tried to plug that number into machine parameter for ortho correction but the value is too large. Maximum correction the machine software will accept is 999urads. With this number in parameters error improved to about 30um which of course doesn't help matters much. It might as well be a 5 miles. What it means is that Micronic field service will have to mechanicaly readjust a position of the interferometer mirror(s) and it looks like the local field service doesn't have an expertise and tools to do that so they will have to bring in someone from homeoffice in Sweden. -Paul -------------- next part -------------- An HTML attachment was scrubbed... URL: From pruitt at stanford.edu Mon Jul 17 12:49:26 2006 From: pruitt at stanford.edu (Beth Pruitt) Date: Mon, 17 Jul 2006 12:49:26 -0700 Subject: me342 mems seminar thursday Message-ID: Thursday 7/20 at 4:30 in 530-127 Tony Flannery of axept Stanford alum and SNF member Creating a Technical Pheonix Building a Startup from the Ashes of a Startup next thursday, Jeff Sampsell, VP Qualcomm MEMS schedule posted at http://me342.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From tberg at snf.stanford.edu Tue Jul 18 09:53:48 2006 From: tberg at snf.stanford.edu (Ted Berg) Date: Tue, 18 Jul 2006 09:53:48 -0700 Subject: Gas testing for AMAT Epi Message-ID: <44BD121C.1020000@snf.stanford.edu> Hello all, We are going to do gas testing for the AMAT Epi gases next Monday the 24th. This should only affect the epi gases unless we have problems we will begin at 8:30am and go for about 2 hours. Hopefully no evacuations or shutdowns. This should satisfy the gas portion of the permit process. ted From rcrane at stanford.edu Wed Jul 19 14:40:28 2006 From: rcrane at stanford.edu (Dick Crane) Date: Wed, 19 Jul 2006 14:40:28 -0700 Subject: Paint smells today, tomorrow Message-ID: <44BEA6CC.5080504@stanford.edu> Lab users and dwellers of CIS, The floors, of the second floor level mechanical areas of the CIS building, are being cleaned and repainted today and tomorrow. Some cleaning and painting odors are expected. Sorry for any inconvenience, Dick From mtang at stanford.edu Sun Jul 23 08:39:24 2006 From: mtang at stanford.edu (Mary Tang) Date: Sun, 23 Jul 2006 08:39:24 -0700 Subject: Coral Update Message-ID: <44C3982C.9050202@stanford.edu> Labmembers: As of about midnight last night, Coral is now up and running. Please enable and disable equipment as you normally would. Let us know if there are any problems with enabling/disabling. We deeply apologize for the inconvenience, but we are, for the time being, back to normal operations. A word of explanation... The problem was not the Coral system itself, which was running fine and has been for quite some time. Recent problems have been with a computer called "snf" which is used to manage snf emails and to authenticate Coral logins. This is why we haven't been able to initiate new Coral sessions (which require authentication) nor communicate using @snf.stanford.edu emails or anything else that gets routed through "snf." The problem is that the "snf" computer is antiquated (even by University standards) and its hardware has been prone, especially lately, to failures. We've only just acquired a new, updated Dell server, waiting to be put into service, but set up and data transfer have not been performed yet. So, we do have a solution in the works, but it may be a little while before it is put into place, In the meantime, the current "snf" is functioning, but please be aware it is subject to failure until the new system is put into service. So, if you experience Coral problems, first try sending an email to coral at snf.stanford.edu. Since snf email may not be working, please notify a staff member (if during working hours) and/or send an email to: rissman at stanford.edu, shott at stanford.edu, dcrane at stanford.edu, mtang at stanford.edu, bmurray at stanford.edu (apologies for the long list, but between all of us we are all likely to be checking emails at all hours and these addresses bypass "snf".) Again, apologies for the inconvenience, but we trust this will be a short term problem. Thanks for your patience -- Your SNF staff From mbaran at stanford.edu Fri Jul 21 14:41:18 2006 From: mbaran at stanford.edu (Maureen Baran) Date: Fri, 21 Jul 2006 14:41:18 -0700 Subject: Rental Car Keys Found @ coral workstation in front of the Gowning Room Message-ID: <20060721214118.52B554BE48@smtp2.stanford.edu> If anyone has misplaced their car keys to a dodge ram rental car, they were found at the coral workstation in front of the Gowning Room. If these keys are yours, please come to my cubicle. I will place them in my in-basket for you. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From rcrane at stanford.edu Mon Jul 24 16:53:19 2006 From: rcrane at stanford.edu (Dick Crane) Date: Mon, 24 Jul 2006 16:53:19 -0700 Subject: Monday's fire alarm Message-ID: <44C55D6F.5060908@stanford.edu> CIS/CISX dwellers and SNF lab users, At 1533 today, Monday, 7/24, we had a CISX room air toxic gas sensor trip into an alarm condition causing the evacuation of CIS and CIX buildings. No toxic gases were involved. The sensor was defective and is being replaced. The alarm reset time was much longer than usual. Thanks to everyone for an orderly evacuation and sorry for the inconvenience, Dick From mtang at stanford.edu Tue Jul 25 14:08:59 2006 From: mtang at stanford.edu (Mary Tang) Date: Tue, 25 Jul 2006 14:08:59 -0700 Subject: Storage of wafers "WIP" Shelves/CAD Room: Housekeeping Message-ID: <44C6886B.7010000@stanford.edu> Hi all -- It's been brought to our attention that there are boxes of wafers that have been on the "WIP" shelves for a loooong time. "WIP" means "Work In Progress" (not "Work In Perpetuity"). Please remove any wafers/wafer boxes that are not in current use and store them elsewhere for safe-keeping so that others who do need store WIP have space to do so. For your work-in-progress, please make sure all wafer containers are labeled with your name/Coral login and date. There are also a lot of items in the CAD room that appear belong to people who have left and organizations which are long gone. We're also running out of storage space for new labmembers there as well. In the interest of good labmember relations, we should all really clean up. So here's the deal: 1. WIP Shelves: At the end of August (8/31/06), any wafer containers or boxes that are not labeled with Coral login and current date (or with dates older than three months) will be removed from the lab. (And please do not just go through and label everything - everyone knows who does this - please make a genuine effort to prune out stuff you are not currently working on.) 2. CAD Storage: At the end of August, storage bins should be labeled with the Coral login(s) of the owner(s) and the current date. All items should be stored inside storage bins (no loose wafer boxes, etc.) Storage bins without appropriate/current labelling will be removed. Items not stored inside storage bins will also be removed. I know I'm being a nagging mom, but please, let's all contribute to some basic housekeeping around the lab. Thanks, Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From rissman at stanford.edu Wed Jul 26 10:09:12 2006 From: rissman at stanford.edu (Paul Rissman) Date: Wed, 26 Jul 2006 10:09:12 -0700 Subject: Micronic status Message-ID: <7.0.1.0.2.20060726095747.04bca9f8@stanford.edu> As you know, on June 23rd, the Micronic service person damaged our maskmaking system leading to a large non-orthogonality of the x and y axes. At that time, Paul Jerabek indicated that one level masks could be made provided that alignment to wafers with patterns from masks from before 6/23 was not required. Last week Micronic service attempted to fix the non-orthogonality on the instrument, but unfortunately the result of those adjustments is that at present we cannot make any masks. Micronic has contacted their factory, and an engineer from Sweden has arrived today. We will update you as more information becomes available. In the interim, information on using Compugraphics as a mask supplier is available on the SNF website. Other alternatives include Photronics and Toppan (formerly Dupont). In addition, there are a number of low cost (but untried) mask shops. Please see me if you want the list. Paul From nlatta at stanford.edu Wed Jul 26 11:36:24 2006 From: nlatta at stanford.edu (Nancy Latta) Date: Wed, 26 Jul 2006 11:36:24 -0700 Subject: Outside ion milling service? Message-ID: <44C7B628.7050901@stanford.edu> Folks, Have any of you used a ion milling service for metal or dielectric layers? One of our labmembers has asked me and I am stumped. Thanks in advance, -Nancy From pruitt at stanford.edu Wed Jul 26 11:42:08 2006 From: pruitt at stanford.edu (Beth Pruitt) Date: Wed, 26 Jul 2006 11:42:08 -0700 Subject: MEMS seminar Jeff Sampsell, Qualcomm tomorrow Message-ID: you are invited to join us for a talk by Jeff Sampsell, VP Qualcomm MEMS ME342 MEMS seminar series thursday 4:30 530-127 refreshments on the patio following the seminar From mahnaz at stanford.edu Thu Jul 27 16:36:00 2006 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Thu, 27 Jul 2006 16:36:00 -0700 Subject: Resist in the regular trash Message-ID: <44C94DE0.8040805@stanford.edu> Hello all, We have found good amount of wipes contaminated with lots of resist in the regular trash across from solvent bench this morning 7/27/06. The contaminated wipes should have been zip logged bag and stored in the red hazardous bin underneath the solvent bench. This is totally unacceptable . If you have seen some one doing this or you are the one whom done it and not sure about our rules and policy please see me " I LIKE TO EXPLAIN IT TO YOU " no hard feeling. mahnaz From rcrane at stanford.edu Mon Jul 31 07:22:55 2006 From: rcrane at stanford.edu (Dick Crane) Date: Mon, 31 Jul 2006 07:22:55 -0700 Subject: Building cooling back to normal Message-ID: <44CE123F.7060808@stanford.edu> As you may have notice, CIS and CISX inside temperatures are approaching normal levels. Please see attached note from the facilities provost. Thanks for your patience, Dick 7/28/06 Good news! As you've noticed, temperatures have cooled down and recent weather forecasts indicate a temporary reprieve until mid-next week from the extraordinarily hot weather we had been experiencing at Stanford. All buildings at Stanford received chilled water to support research processes and comfort cooling by Thursday morning. We are in the process of fine-tuning the adjustments to the temperature settings in the buildings. Please call MCS at 3-2281 or your Zone Manager if conditions in your building have not improved by now or if further adjustments are needed. With planned improvements to our chilled water capacity happening this weekend and early next week, we do not expect to have such severe curtailment as we experienced earlier even with the expected heat wave that is forecasted for later next week. It is our goal to sustain near-normal building temperatures to minimize impact to research processes. Thank you all for helping us get through this most difficult curtailment period. For more information about Chilled Water Curtailment and planned improvements, please reference the Stanford Report article that came out Wednesday at the URL below. http://news-service.stanford.edu/news/2006/july26/heat-072606.html Sincerely, Chris Christofferson Associate Vice Provost for Facilities -------------- next part -------------- An HTML attachment was scrubbed... URL: From rcrane at stanford.edu Mon Jul 31 11:04:04 2006 From: rcrane at stanford.edu (Dick Crane) Date: Mon, 31 Jul 2006 11:04:04 -0700 Subject: Building cooling back to normal Message-ID: <44CE4614.10608@stanford.edu> As you may have notice, CIS and CISX inside temperatures are approaching normal levels. Please see attached note from the facilities provost. Thanks for your patience, Dick 7/28/06 Good news! As you've noticed, temperatures have cooled down and recent weather forecasts indicate a temporary reprieve until mid-next week from the extraordinarily hot weather we had been experiencing at Stanford. All buildings at Stanford received chilled water to support research processes and comfort cooling by Thursday morning. We are in the process of fine-tuning the adjustments to the temperature settings in the buildings. Please call MCS at 3-2281 or your Zone Manager if conditions in your building have not improved by now or if further adjustments are needed. With planned improvements to our chilled water capacity happening this weekend and early next week, we do not expect to have such severe curtailment as we experienced earlier even with the expected heat wave that is forecasted for later next week. It is our goal to sustain near-normal building temperatures to minimize impact to research processes. Thank you all for helping us get through this most difficult curtailment period. For more information about Chilled Water Curtailment and planned improvements, please reference the Stanford Report article that came out Wednesday at the URL below. http://news-service.stanford.edu/news/2006/july26/heat-072606.html Sincerely, Chris Christofferson Associate Vice Provost for Facilities -------------- next part -------------- An HTML attachment was scrubbed... URL: From jerabek at snf.stanford.edu Mon Jul 31 11:23:49 2006 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Mon, 31 Jul 2006 11:23:49 -0700 (PDT) Subject: mask writer Message-ID: To whom it may concern: this past week Micronic field service flew in an engineer from Sweden to work on the ortho problem. He did make some adjustments to the mirrors using a microcator (???? that's what I was told). They wrote a test mask and today are delivering it to Compugraphics to be measured. As soon as I know more I'll let you all know. -Paul From weixiong at stanford.edu Mon Jul 31 11:22:42 2006 From: weixiong at stanford.edu (Wei Xiong) Date: Mon, 31 Jul 2006 11:22:42 -0700 Subject: Nitrogen storage box in SEM Message-ID: <005701c6b4ce$516935b0$6400a8c0@weixiong> Hi, If you are the owner of the N2 box in SEM room, please let me know whether I can use it to store a box of wafers. thanks! Wei From rcrane at stanford.edu Mon Jul 31 12:57:31 2006 From: rcrane at stanford.edu (Dick Crane) Date: Mon, 31 Jul 2006 12:57:31 -0700 Subject: Building cooling back to normal Message-ID: <44CE60AB.5080100@stanford.edu> As you may have notice, CIS and CISX inside temperatures are approaching normal levels. Please see attached note from the facilities provost. Thanks for your patience, Dick 7/28/06 Good news! As you've noticed, temperatures have cooled down and recent weather forecasts indicate a temporary reprieve until mid-next week from the extraordinarily hot weather we had been experiencing at Stanford. All buildings at Stanford received chilled water to support research processes and comfort cooling by Thursday morning. We are in the process of fine-tuning the adjustments to the temperature settings in the buildings. Please call MCS at 3-2281 or your Zone Manager if conditions in your building have not improved by now or if further adjustments are needed. With planned improvements to our chilled water capacity happening this weekend and early next week, we do not expect to have such severe curtailment as we experienced earlier even with the expected heat wave that is forecasted for later next week. It is our goal to sustain near-normal building temperatures to minimize impact to research processes. Thank you all for helping us get through this most difficult curtailment period. For more information about Chilled Water Curtailment and planned improvements, please reference the Stanford Report article that came out Wednesday at the URL below. http://news-service.stanford.edu/news/2006/july26/heat-072606.html Sincerely, Chris Christofferson Associate Vice Provost for Facilities -------------- next part -------------- An HTML attachment was scrubbed... URL: From eric.pop at intel.com Mon Jul 31 13:28:30 2006 From: eric.pop at intel.com (Pop, Eric) Date: Mon, 31 Jul 2006 13:28:30 -0700 Subject: preparing TiN surface Message-ID: <2BCF8A1CC7A24341BCAA8193857F947E522152@scsmsx413.amr.corp.intel.com> Dear labmembers: We have some blanket TiN films (about 75nm thick) deposited outside SNF. We want to deposit about 200nm Au blanket on top of them and would like a good quality interface (for thermal transport studies). We're not TiN or TiN cleaning experts, so I was wondering what you might recommend for preparing the TiN surface. The surface has been exposed to air, so it's likely got a thin native oxide and airborne organic crud on it. We were thinking of a standard RCA clean followed by a thin (2-3nm) adhesion layer of Ti, then the Au in Innotec. Do you have any advice on preparing the TiN surface, and perhaps for removing any TiN native oxide? We would like to NOT eat too much into the TiN thickness, because we need it to be around 70-75nm. Thanks in advance, -Eric Pop (not Perozziello!) From mahnaz at stanford.edu Mon Jul 31 17:36:25 2006 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Mon, 31 Jul 2006 17:36:25 -0700 Subject: 220-7 Message-ID: <44CEA209.2040202@stanford.edu> Hello all, As you know the controller for 7 um and 3 um is out. So I have put a small bottle of 220-7 on the headway bench, if you need 7 or 10 um , you need to do it manually. The bottle has been labeled. mahnaz