From mtang at stanford.edu  Thu Jun  1 09:58:17 2006
From: mtang at stanford.edu (Mary Tang)
Date: Thu, 01 Jun 2006 09:58:17 -0700
Subject: Brewer Science Presentation today, 10 am, CIS 101
Message-ID: <447F1CA9.2040109@stanford.edu>

Hi everyone --

A reminder that Brewer Science is here (now) to present info about their 
line of MEMS-related chemicals/process modules.  Refreshment/pastries 
served.

For more info, see:
http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:2251:200605:kdfgkimieddadednmodn

Mary

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From scaccag at stanford.edu  Thu Jun  1 15:38:20 2006
From: scaccag at stanford.edu (Luigi Scaccabarozzi)
Date: Thu, 1 Jun 2006 15:38:20 -0700 (PDT)
Subject: silicon index
Message-ID: <Pine.LNX.4.44.0606011535050.14165-100000@vine10.Stanford.EDU>

Hi all,
my friend WahTung works accross the street in Ginzton lab and is
asking about the Refractive index and the absorption of Silicon at High
temperature (say 1000K) in the IR range.
Please, reply directly to him: wlau at stanford.edu
Thanks a lot!
Gigi

---------- Forwarded message ----------
Date: Thu, 1 Jun 2006 14:48:29 -0700 (PDT)
From: Wah Tung Lau <wlau at stanford.edu>
To: Luigi Scaccabarozzi <scaccag at stanford.edu>
Subject: quick question to ask

Hi Gigi,

Do you know anyone in CIS may have a grasp of Refractive index and
absorption index of Silicon at High temperature (say 1000K) at IR range ?

wah tung



From mtang at stanford.edu  Fri Jun  2 08:11:58 2006
From: mtang at stanford.edu (Mary Tang)
Date: Fri, 02 Jun 2006 08:11:58 -0700
Subject: Shallow Junction Characterization Seminar - today
Message-ID: <4480553E.6050208@stanford.edu>

Hi everyone --

Just a reminder that Michael Current, from FSM, will be here today to 
present his work non-contact methods for shallow junction 
characterization.  There is a possibility that we may be able to acquire 
a demo system for our lab, if there is sufficient interest in this from 
our lab community.  For more information, see the attached.  The seminar 
is scheduled for today, at 10 am in CIS 101.  Refreshments will be served.

Mary

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu

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From hesaam at stanford.edu  Fri Jun  2 18:55:24 2006
From: hesaam at stanford.edu (Hesaam Esfandyarpour)
Date: Fri, 02 Jun 2006 18:55:24 -0700
Subject: A droplet of Gallium required (plz)
Message-ID: <7.0.1.0.2.20060602184028.02555ac8@stanford.edu>

Dear all,

Thanks for your attention.
I need a very few droplets of Ga (Gallium) urgently, so would really 
appreciate it if someone can give/borrow it to me.

I ordered it from Sigma, but it will not be received before Tues/Wed.
Thank you very much,
Best regards,
Hesaam




From xzhuang at stanford.edu  Fri Jun  2 18:26:59 2006
From: xzhuang at stanford.edu (Steve Zhuang)
Date: Fri, 2 Jun 2006 18:26:59 -0700
Subject: using SU-8 to fill deep trenches
References: <4480553E.6050208@stanford.edu>
Message-ID: <004a01c686ac$cf3e2090$bb5640ab@pky7>

Hi All,

I'm planning to use SU-8 photoresist to fill trenches that are about 10 um 
wide and 100um deep.  Has anyone used SU-8 for similar applications?  I've 
not worked with SU-8 before so any suggestions on how to use it for thick 
layers will be highly appreciated.

Thanks.

Steve Zhuang
Khuri-Yakub Ultrasonics Group 



From cmgas at stanford.edu  Mon Jun  5 15:27:35 2006
From: cmgas at stanford.edu (Christophe Antoine)
Date: Mon, 5 Jun 2006 15:27:35 -0700
Subject: Looking for SOI vendors
Message-ID: <138e8dd60606051527t751ae911u37a9fdbd3cc5942@mail.gmail.com>

Hi everyone,

I want to buy 4" (1-0-0) SOI wafers with a device layer thickness of
40 microns and a buried oxide (BOX) thickness of 4 microns.

For those of you who ordered SOI wafers before, who did you order them from?

Please let me know.
Thanks.
Christophe
-- 
--------------------------------------------------
Christophe Antoine
PhD Candidate in Electrical Engineering
Email: cmgas at stanford.edu (work)
Antoine-Snowden at stanfordalumni.org (friends)


From sanli at stanford.edu  Tue Jun  6 12:07:46 2006
From: sanli at stanford.edu (Arif Sanli Ergun)
Date: Tue,  6 Jun 2006 12:07:46 -0700
Subject: low-stress silicon nitride
Message-ID: <1149620866.4485d28250a69@webmail.stanford.edu>

Hi lab members,
Does anyone have recent experience in getting
low-stress silicon nitride deposition outside CIS?

Sanli



From nordlund at slac.stanford.edu  Tue Jun  6 15:51:01 2006
From: nordlund at slac.stanford.edu (Dennis Nordlund)
Date: Tue, 6 Jun 2006 15:51:01 -0700
Subject: low-stress silicon nitride
In-Reply-To: <1149620866.4485d28250a69@webmail.stanford.edu>
References: <1149620866.4485d28250a69@webmail.stanford.edu>
Message-ID: <Pine.CYG.4.58.0606061549520.4580@nordlundpc.win.slac.stanford.edu>

Arif,

I have a couple of source since I asked the question some time ago. I'm
off for meetings now, but I can forward a couple of mails later, eg 18:00

/Dennis
On Tue, 6 Jun 2006, Arif Sanli Ergun wrote:

> Hi lab members,
> Does anyone have recent experience in getting
> low-stress silicon nitride deposition outside CIS?
>
> Sanli
>
>


From jwc at snf.stanford.edu  Tue Jun  6 18:50:00 2006
From: jwc at snf.stanford.edu (James Conway)
Date: Tue, 06 Jun 2006 18:50:00 -0700
Subject: Looking for SOI vendors
In-Reply-To: <138e8dd60606051527t751ae911u37a9fdbd3cc5942@mail.gmail.com>
References: <138e8dd60606051527t751ae911u37a9fdbd3cc5942@mail.gmail.com>
Message-ID: <448630C8.8020807@snf.stanford.edu>

I would recommend SOItec in France.

James Conway

Christophe Antoine wrote:

> Hi everyone,
>
> I want to buy 4" (1-0-0) SOI wafers with a device layer thickness of
> 40 microns and a buried oxide (BOX) thickness of 4 microns.
>
> For those of you who ordered SOI wafers before, who did you order them 
> from?
>
> Please let me know.
> Thanks.
> Christophe




From shott at stanford.edu  Wed Jun  7 10:09:54 2006
From: shott at stanford.edu (John Shott)
Date: Wed, 07 Jun 2006 10:09:54 -0700
Subject: Missing coax-to-triax converters ...
Message-ID: <44870862.50504@stanford.edu>

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From beinnmuir at stanford.edu  Wed Jun  7 11:30:09 2006
From: beinnmuir at stanford.edu (Beinn Muir)
Date: Wed,  7 Jun 2006 11:30:09 -0700
Subject: Electrodes
Message-ID: <1149705009.44871b3164af3@webmail.stanford.edu>

Hi all,

I am looking for a counter electrode for an Al anodising experiment that I
am setting up with a summer student.  I am looking for a platinum,
carbon/graphite, or lead electrode (the best would be platinum foil) to use
as the counter electrode.

I intend to order some Pt foil, but it usually takes a few weeks for the
order to be processed and I would like to get started next week. So if
anyone has a suitable electrode that I could borrow, or knows of a group on
campus working on electrochemistry that I could talk to, then I would like
to hear from you.

Thanks for your help!

Cheers,
Beinn...


From rcrane at stanford.edu  Wed Jun  7 15:57:59 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Wed, 07 Jun 2006 15:57:59 -0700
Subject: N2 shutdown 0630-0730 6/19/06
Message-ID: <448759F7.2080600@stanford.edu>

CIS/CISX and SNF fab users,

The house N2 (aka, low purity) gas system will be shutdown for repairs 
from 0630-0730 on Monday, June 19. Leaking gaskets in the main 
distribution line to the building will be replaced. While the work 
should take 15-20 minutes, I'm scheduling for a one hour shutdown to 
cover delays and line purging. High purity N2 will not be lost during 
the repair. House air pressure (aka, CDA) will not be affected.

CISX will lose house N2 pressure during the repair.

SNF fab will lose the ability to operate most of the process tools and 
for all practical purposes, be closed for use during this time. Most 
tools will be reset and ready for operation by 0800.

Why have the gaskets failed? The teflon gaskets were installed in 1983 
and have subjected to numerous temperature cycles. The teflon sealing 
surfaces appear to have cracked after 24 years of service.

Sorry for the inconvenience,

Dick



From cmgas at stanford.edu  Fri Jun  9 11:44:55 2006
From: cmgas at stanford.edu (Christophe Antoine)
Date: Fri, 9 Jun 2006 11:44:55 -0700
Subject: Looking for SOI vendors
In-Reply-To: <138e8dd60606051527t751ae911u37a9fdbd3cc5942@mail.gmail.com>
References: <138e8dd60606051527t751ae911u37a9fdbd3cc5942@mail.gmail.com>
Message-ID: <138e8dd60606091144t1e285a58vee42761c93b56d3c@mail.gmail.com>

Hello everyone,

Thanks to all those who replied to my inquiry about where to get SOI wafers.
Here are the results for those who want to buy SOIs in the future:

1. Recommended by 5 labmembers:
... Ultrasil: http://www.ultrasil.com/cgi-bin/exprocess.cgi

2. Recommended by 4 lab members:
... SOITEC: http://www.soitec.com/

3. Recommended by 1 lab member:
... http://www.siliconquest.com/eng/products/soi.htm (ask for Jennifer Lozada)
... MEMS Engineering www.memsengineering.com
... www.universitywafer.com
... Shin-Etsu Handotai (SEH) http://www.sehamerica.com/


Thanks again for all your inputs.
Christophe



On 6/5/06, Christophe Antoine <cmgas at stanford.edu> wrote:
> Hi everyone,
>
> I want to buy 4" (1-0-0) SOI wafers with a device layer thickness of
> 40 microns and a buried oxide (BOX) thickness of 4 microns.
>
> For those of you who ordered SOI wafers before, who did you order them from?
>
> Please let me know.
> Thanks.
> Christophe
> --
> --------------------------------------------------
> Christophe Antoine
> PhD Candidate in Electrical Engineering
> Email: cmgas at stanford.edu (work)
> Antoine-Snowden at stanfordalumni.org (friends)
>


-- 
--------------------------------------------------
Christophe Antoine
PhD Candidate in Electrical Engineering
Email: cmgas at stanford.edu (work)
Antoine-Snowden at stanfordalumni.org (friends)


From hpbae at stanford.edu  Fri Jun  9 12:37:16 2006
From: hpbae at stanford.edu (HopilBae)
Date: Fri, 09 Jun 2006 12:37:16 -0700
Subject: Anyone with Tesla coil?
In-Reply-To: <138e8dd60606091144t1e285a58vee42761c93b56d3c@mail.gmail.com>
References: <138e8dd60606051527t751ae911u37a9fdbd3cc5942@mail.gmail.com> <138e8dd60606091144t1e285a58vee42761c93b56d3c@mail.gmail.com>
Message-ID: <4489CDEC.6000703@stanford.edu>


Hi, everyone,

I'm sorry for spamming the list..
Does anyone have a tesla coil for lab work or for hobby?
We'd like borrow one for a few days if possible.

Thank you
Hopil


From arguicha at stanford.edu  Fri Jun  9 13:59:46 2006
From: arguicha at stanford.edu (Alex Guichard)
Date: Fri, 9 Jun 2006 13:59:46 -0700
Subject: Looking for ITO, Al2O3 vendors
In-Reply-To: <138e8dd60606091144t1e285a58vee42761c93b56d3c@mail.gmail.com>
References: <138e8dd60606051527t751ae911u37a9fdbd3cc5942@mail.gmail.com> <138e8dd60606091144t1e285a58vee42761c93b56d3c@mail.gmail.com>
Message-ID: <B2475755-A532-49CC-8334-D11233978277@stanford.edu>

Can anyone recommend a vendor for high-quality ITO and Al2O3  
substrates?  Any help would be greatly appreciated!

Sincerely,
Alex




Alex R. Guichard
Ph.D Candidate
Dept. of Mat. Sci. and Eng.
Stanford University
(M)919-434-6906  (F)650-724-9851
(O) 650-723-6352  (L)650-723-6466
http://www.stanford.edu/group/BrongersmaGroup/


On Jun 9, 2006, at 11:44 AM, Christophe Antoine wrote:

> Hello everyone,
>
> Thanks to all those who replied to my inquiry about where to get  
> SOI wafers.
> Here are the results for those who want to buy SOIs in the future:
>
> 1. Recommended by 5 labmembers:
> ... Ultrasil: http://www.ultrasil.com/cgi-bin/exprocess.cgi
>
> 2. Recommended by 4 lab members:
> ... SOITEC: http://www.soitec.com/
>
> 3. Recommended by 1 lab member:
> ... http://www.siliconquest.com/eng/products/soi.htm (ask for  
> Jennifer Lozada)
> ... MEMS Engineering www.memsengineering.com
> ... www.universitywafer.com
> ... Shin-Etsu Handotai (SEH) http://www.sehamerica.com/
>
>
> Thanks again for all your inputs.
> Christophe
>
>
>
> On 6/5/06, Christophe Antoine <cmgas at stanford.edu> wrote:
>> Hi everyone,
>>
>> I want to buy 4" (1-0-0) SOI wafers with a device layer thickness of
>> 40 microns and a buried oxide (BOX) thickness of 4 microns.
>>
>> For those of you who ordered SOI wafers before, who did you order  
>> them from?
>>
>> Please let me know.
>> Thanks.
>> Christophe
>> --
>> --------------------------------------------------
>> Christophe Antoine
>> PhD Candidate in Electrical Engineering
>> Email: cmgas at stanford.edu (work)
>> Antoine-Snowden at stanfordalumni.org (friends)
>>
>
>
> -- 
> --------------------------------------------------
> Christophe Antoine
> PhD Candidate in Electrical Engineering
> Email: cmgas at stanford.edu (work)
> Antoine-Snowden at stanfordalumni.org (friends)



From bli003 at student.ucr.edu  Fri Jun  9 15:22:01 2006
From: bli003 at student.ucr.edu (bli003 at student.ucr.edu)
Date: Fri,  9 Jun 2006 15:22:01 -0700 (PDT)
Subject: Looking for company that can grow III-V quantum
 dots/superlattice
Message-ID: <20060609152201.ABT26114@mh1.ucr.edu>

Dear All,

If you happen to know some company that can grow III-V quantum dots/superlattice, please let me know. Any information is appreciated.

Thanks,
Bei


From auprabhu at yahoo.com  Mon Jun 12 09:12:19 2006
From: auprabhu at yahoo.com (prabhu arumugam)
Date: Mon, 12 Jun 2006 09:12:19 -0700 (PDT)
Subject: vendors for ITO coated glass wafers 
Message-ID: <20060612161219.9561.qmail@web60819.mail.yahoo.com>

Hello everyone,
I want to buy 4 inch borosilicate wafers coated with
ITO. Could anyone please tell me some suppliers.

Thanks
Prabhu



__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 


From jonroth at stanford.edu  Mon Jun 12 18:03:41 2006
From: jonroth at stanford.edu (Jonathan Edgar Roth)
Date: Mon, 12 Jun 2006 18:03:41 -0700
Subject: AuZn electroplate
Message-ID: <1150160621.448e0eedd9c75@webmail.stanford.edu>

Hello labmembers,

I'm looking for a solution to get a low contact resistance P-layer to InGaAs
(on InP).  My InGaAs layer is doped with Zn at 5E18/cm^3, which is giving a
poor contact resistance.

One possible solution is to electroplate with AuZn (or perhaps Zn).  Can
anyone recommend a solution for electroplating, or even have any around
that I might give it a try?

Thanks,
Jon Roth

PhD Candidate, electrical engineering


From kimsangb at stanford.edu  Tue Jun 13 13:54:12 2006
From: kimsangb at stanford.edu (SangBum Kim)
Date: Tue, 13 Jun 2006 13:54:12 -0700
Subject: Wirebond to innotec gold
Message-ID: <007001c68f2b$8627aa70$a9b50c80@anavel>

Dear all,

 We are having problems to wirebond to gold pad (200nm thick, 2nm Cr
underneath for adhesion to 10nm thick SiO2.) which was evaporated at Innotec
and then lift-offed. Here is the description of the problem.

"When I try to bond to the patterned pads, it takes a huge amount of power
and time to even make a mark on the pad compared to what it takes for gold
pads on the chip carrier and other samples. I suspect this is because the
material is very hard."

 Has anyone know why this is happening? Thanks in advance.

SangBum

-----Original Message-----
From: John P. Reifenberg [mailto:jreif at stanford.edu] 
Sent: Monday, June 12, 2006 9:49 PM
To: SangBum Kim
Cc: ankurjn at stanford.edu; 'Yuan Zhang'
Subject: RE: Intel 3w Samples

Hi SangBum,

Thanks for your reply. In the short term I have sent four samples to Pauline
for wire bonding. According to another student in our group, she will be
back tomorrow.

When I try to bond to the patterned pads, it takes a huge amount of power
and time to even make a mark on the pad compared to what it takes for gold
pads on the chip carrier and other samples. I suspect this is because the
material is very hard, but I do not know why it would be so hard. 99% of
the bonds do not stick and those that do are very fragile. I think the
bonds are breaking because the sonication of the tip of the wire is so high
that it is affecting portions of wire up the strand. A better wire bonder
could be the solution if this is the problem, so Pauline may have better
luck than me, but it is still unclear why the gold would be so hard.

My suspicion was that there may be some chemical on top of the gold due to
the processing technique, but based on your description it sounds like this
cannot be the case.

I also do not think it is an oxide because chip carriers would be affected
as well. I thought for a while that it may be the Au and Cr layers are
diffusing to form a very hard alloy, but since Cr is so commonly used as an
adhesion layer for Au, I also doubt this is the case. To be honest I am not
sure what path to pursue other than to ask the other groups using the wire
bonder whether they have any insight. I will start there. If you have other
suggestions, they would be very useful.

Thanks
John



Quoting SangBum Kim <kimsangb at stanford.edu>:

> Dear John,
>
>  I used ebeam evaporator (innotec) to deposit Cr+Au layer. The principle
> is
> to shoot high energy electrons to the chunk(target) of Cr or Au. Then Cr
> or
> Au atoms are evaporated from the target, flies to the wafer and sticks to
> it. The target itself is highly purified (at least 99%). The only
> contamination source I can think of is the case when the ebeam is heating
> the crucible not the target so that you are evaporating the material of
> crucible, not the target. However, since I observed the point where the
> ebeam is heating during the process (It is a very bright spot.) I don't
> expect this to happen so severely. Yuan, any comment?
>
>  By the way, if there is something else on Au, what would it be? Metal?
> Oxide? And why is it a problem for wire-bonding? Let's figure this out.
> Feel
> free to ask any question if you have.
>
> Thanks,
> SangBum
>
> -----Original Message-----
> From: John P. Reifenberg [mailto:jreif at stanford.edu]
> Sent: Monday, June 12, 2006 12:16 PM
> To: kimsangb at stanford.edu
> Cc: ankurjn at stanford.edu
> Subject: Intel 3w Samples
>
> Hi SangBum,
>
> When you process the 3w samples with Au heaters on the Cr adhesion layer,
> is
> there a possibility that there is some material left on the surface of
> the
> Au? It seems that the patterned Au pads are extremely hard. I need to use
> a
> huge power/time setting to even make a dent but the bonds become either
> very
> fragile, or they do not stick at all when I am at this setting.
>
> I'm pretty sure this is not a problem with the wirebonder or what I am
> doing. I can easily bond to the Au on the chip carrier and had no trouble
> with Eric's TiN/TiX samples.
>
> Ankur have you ever had this problem? Alternatively, is there someone in
> CIS
> with more experience that can try the wirebonding?
>
> Thanks,
> John
>
>




From rcrane at stanford.edu  Tue Jun 13 15:53:41 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Tue, 13 Jun 2006 15:53:41 -0700
Subject: Reminder N2 shutdown 6/19
Message-ID: <448F41F5.1030703@stanford.edu>

Kind reminder:

CIS/CISX and SNF fab users,

The house N2 (aka, low purity) gas system will be shutdown for repairs 
from 0630-0730 on Monday, June 19. Leaking gaskets in the main 
distribution line to the building will be replaced. While the work 
should take 15-20 minutes, I'm scheduling for a one hour shutdown to 
cover delays and line purging. High purity N2 will not be lost during 
the repair. House air pressure (aka, CDA) will not be affected.

CISX will lose house N2 pressure during the repair.

SNF fab will lose the ability to operate most of the process tools and 
for all practical purposes, be closed for use during this time. Most 
tools will be reset and ready for operation by 0800.

Why have the gaskets failed? The teflon gaskets were installed in 1983 
and have subjected to numerous temperature cycles. The teflon sealing 
surfaces appear to have cracked after 24 years of service.

Sorry for the inconvenience,

Dick



From levi at snow.stanford.edu  Tue Jun 13 16:25:29 2006
From: levi at snow.stanford.edu (Ofer Levi)
Date: Tue, 13 Jun 2006 16:25:29 -0700
Subject: AZ 9260 photoresist - Clariant
In-Reply-To: <4489CDEC.6000703@stanford.edu>
References: <138e8dd60606051527t751ae911u37a9fdbd3cc5942@mail.gmail.com>
 <138e8dd60606091144t1e285a58vee42761c93b56d3c@mail.gmail.com>
 <4489CDEC.6000703@stanford.edu>
Message-ID: <6.1.2.0.2.20060613162128.05cd5600@snowboard.stanford.edu>

Hi everyone,
I need a bit of a AZ 9260 photoresist (Clariant) for a thick 8 micron Mesa 
side wall coverage step for contacts. We used to have it in the clean room, 
but it got removed during the last cleanup.
If anyone still has it and can give me a bit to use, please let me know.

Many thanks,
Ofer Levi



______________________________________________

Ofer Levi,      Ph.D.
Department of Electrical Engineering, Stanford University
CIS-X Rm 310,  Stanford, CA 94305-4075

Phone:                             (650)723-0464 or 725-6907
Fax:                                              (650)723-4659
Adm. Asst.: Gail Chun-Creech                  Ph:  (650)723-0983
E-Mail:                          levi at snow.stanford.edu
Web page:               http://snow.stanford.edu/~levi/
______________________________________________



From EricS at Bridgewave.com  Wed Jun 14 10:19:57 2006
From: EricS at Bridgewave.com (Eric Sanjuan)
Date: Wed, 14 Jun 2006 10:19:57 -0700
Subject: Wirebond to innotec gold
Message-ID: <C06EC1234EE78D4CB04D5B06AD849AB27BE1A9@paris.bridgewave.local>

I've never heard, or read, of anyone trying to wirebond onto gold so thin, is this typical in some applications? Standard wirebonding occurs onto Au pads that are microns thick, some applications call for a cyanide (hard) Au plating bath, I typically use sulfite (soft) Au plating bath.
eric

-----Original Message-----
From: SangBum Kim [mailto:kimsangb at stanford.edu]
Sent: Tuesday, June 13, 2006 1:54 PM
To: labmembers at snf.stanford.edu
Cc: 'John P. Reifenberg'; 'Yuan Zhang'
Subject: Wirebond to innotec gold


Dear all,

 We are having problems to wirebond to gold pad (200nm thick, 2nm Cr
underneath for adhesion to 10nm thick SiO2.) which was evaporated at Innotec
and then lift-offed. Here is the description of the problem.

"When I try to bond to the patterned pads, it takes a huge amount of power
and time to even make a mark on the pad compared to what it takes for gold
pads on the chip carrier and other samples. I suspect this is because the
material is very hard."

 Has anyone know why this is happening? Thanks in advance.

SangBum

-----Original Message-----
From: John P. Reifenberg [mailto:jreif at stanford.edu] 
Sent: Monday, June 12, 2006 9:49 PM
To: SangBum Kim
Cc: ankurjn at stanford.edu; 'Yuan Zhang'
Subject: RE: Intel 3w Samples

Hi SangBum,

Thanks for your reply. In the short term I have sent four samples to Pauline
for wire bonding. According to another student in our group, she will be
back tomorrow.

When I try to bond to the patterned pads, it takes a huge amount of power
and time to even make a mark on the pad compared to what it takes for gold
pads on the chip carrier and other samples. I suspect this is because the
material is very hard, but I do not know why it would be so hard. 99% of
the bonds do not stick and those that do are very fragile. I think the
bonds are breaking because the sonication of the tip of the wire is so high
that it is affecting portions of wire up the strand. A better wire bonder
could be the solution if this is the problem, so Pauline may have better
luck than me, but it is still unclear why the gold would be so hard.

My suspicion was that there may be some chemical on top of the gold due to
the processing technique, but based on your description it sounds like this
cannot be the case.

I also do not think it is an oxide because chip carriers would be affected
as well. I thought for a while that it may be the Au and Cr layers are
diffusing to form a very hard alloy, but since Cr is so commonly used as an
adhesion layer for Au, I also doubt this is the case. To be honest I am not
sure what path to pursue other than to ask the other groups using the wire
bonder whether they have any insight. I will start there. If you have other
suggestions, they would be very useful.

Thanks
John



Quoting SangBum Kim <kimsangb at stanford.edu>:

> Dear John,
>
>  I used ebeam evaporator (innotec) to deposit Cr+Au layer. The principle
> is
> to shoot high energy electrons to the chunk(target) of Cr or Au. Then Cr
> or
> Au atoms are evaporated from the target, flies to the wafer and sticks to
> it. The target itself is highly purified (at least 99%). The only
> contamination source I can think of is the case when the ebeam is heating
> the crucible not the target so that you are evaporating the material of
> crucible, not the target. However, since I observed the point where the
> ebeam is heating during the process (It is a very bright spot.) I don't
> expect this to happen so severely. Yuan, any comment?
>
>  By the way, if there is something else on Au, what would it be? Metal?
> Oxide? And why is it a problem for wire-bonding? Let's figure this out.
> Feel
> free to ask any question if you have.
>
> Thanks,
> SangBum
>
> -----Original Message-----
> From: John P. Reifenberg [mailto:jreif at stanford.edu]
> Sent: Monday, June 12, 2006 12:16 PM
> To: kimsangb at stanford.edu
> Cc: ankurjn at stanford.edu
> Subject: Intel 3w Samples
>
> Hi SangBum,
>
> When you process the 3w samples with Au heaters on the Cr adhesion layer,
> is
> there a possibility that there is some material left on the surface of
> the
> Au? It seems that the patterned Au pads are extremely hard. I need to use
> a
> huge power/time setting to even make a dent but the bonds become either
> very
> fragile, or they do not stick at all when I am at this setting.
>
> I'm pretty sure this is not a problem with the wirebonder or what I am
> doing. I can easily bond to the Au on the chip carrier and had no trouble
> with Eric's TiN/TiX samples.
>
> Ankur have you ever had this problem? Alternatively, is there someone in
> CIS
> with more experience that can try the wirebonding?
>
> Thanks,
> John
>
>




From lxuwind at stanford.edu  Wed Jun 14 10:32:33 2006
From: lxuwind at stanford.edu (Liang Xu)
Date: Wed, 14 Jun 2006 10:32:33 -0700
Subject: Wirebond to innotec gold
In-Reply-To: <C06EC1234EE78D4CB04D5B06AD849AB27BE1A9@paris.bridgewave.local>
References: <C06EC1234EE78D4CB04D5B06AD849AB27BE1A9@paris.bridgewave.local>
Message-ID: <1150306353.44904831b6dac@webmail.stanford.edu>

I think 200nm is ok. I used 300nm gold, with Ta underneath for adhesion. It
bonds pretty well.

Quoting Eric Sanjuan <EricS at Bridgewave.com>:

> I've never heard, or read, of anyone trying to wirebond onto gold so
> thin, is this typical in some applications? Standard wirebonding occurs
> onto Au pads that are microns thick, some applications call for a cyanide
> (hard) Au plating bath, I typically use sulfite (soft) Au plating bath.
> eric
>
> -----Original Message-----
> From: SangBum Kim [mailto:kimsangb at stanford.edu]
> Sent: Tuesday, June 13, 2006 1:54 PM
> To: labmembers at snf.stanford.edu
> Cc: 'John P. Reifenberg'; 'Yuan Zhang'
> Subject: Wirebond to innotec gold
>
>
> Dear all,
>
>  We are having problems to wirebond to gold pad (200nm thick, 2nm Cr
> underneath for adhesion to 10nm thick SiO2.) which was evaporated at
> Innotec
> and then lift-offed. Here is the description of the problem.
>
> "When I try to bond to the patterned pads, it takes a huge amount of
> power
> and time to even make a mark on the pad compared to what it takes for
> gold
> pads on the chip carrier and other samples. I suspect this is because the
> material is very hard."
>
>  Has anyone know why this is happening? Thanks in advance.
>
> SangBum
>
> -----Original Message-----
> From: John P. Reifenberg [mailto:jreif at stanford.edu]
> Sent: Monday, June 12, 2006 9:49 PM
> To: SangBum Kim
> Cc: ankurjn at stanford.edu; 'Yuan Zhang'
> Subject: RE: Intel 3w Samples
>
> Hi SangBum,
>
> Thanks for your reply. In the short term I have sent four samples to
> Pauline
> for wire bonding. According to another student in our group, she will be
> back tomorrow.
>
> When I try to bond to the patterned pads, it takes a huge amount of power
> and time to even make a mark on the pad compared to what it takes for
> gold
> pads on the chip carrier and other samples. I suspect this is because the
> material is very hard, but I do not know why it would be so hard. 99% of
> the bonds do not stick and those that do are very fragile. I think the
> bonds are breaking because the sonication of the tip of the wire is so
> high
> that it is affecting portions of wire up the strand. A better wire bonder
> could be the solution if this is the problem, so Pauline may have better
> luck than me, but it is still unclear why the gold would be so hard.
>
> My suspicion was that there may be some chemical on top of the gold due
> to
> the processing technique, but based on your description it sounds like
> this
> cannot be the case.
>
> I also do not think it is an oxide because chip carriers would be
> affected
> as well. I thought for a while that it may be the Au and Cr layers are
> diffusing to form a very hard alloy, but since Cr is so commonly used as
> an
> adhesion layer for Au, I also doubt this is the case. To be honest I am
> not
> sure what path to pursue other than to ask the other groups using the
> wire
> bonder whether they have any insight. I will start there. If you have
> other
> suggestions, they would be very useful.
>
> Thanks
> John
>
>
>
> Quoting SangBum Kim <kimsangb at stanford.edu>:
>
> > Dear John,
> >
> >  I used ebeam evaporator (innotec) to deposit Cr+Au layer. The
> principle
> > is
> > to shoot high energy electrons to the chunk(target) of Cr or Au. Then
> Cr
> > or
> > Au atoms are evaporated from the target, flies to the wafer and sticks
> to
> > it. The target itself is highly purified (at least 99%). The only
> > contamination source I can think of is the case when the ebeam is
> heating
> > the crucible not the target so that you are evaporating the material of
> > crucible, not the target. However, since I observed the point where the
> > ebeam is heating during the process (It is a very bright spot.) I don't
> > expect this to happen so severely. Yuan, any comment?
> >
> >  By the way, if there is something else on Au, what would it be? Metal?
> > Oxide? And why is it a problem for wire-bonding? Let's figure this out.
> > Feel
> > free to ask any question if you have.
> >
> > Thanks,
> > SangBum
> >
> > -----Original Message-----
> > From: John P. Reifenberg [mailto:jreif at stanford.edu]
> > Sent: Monday, June 12, 2006 12:16 PM
> > To: kimsangb at stanford.edu
> > Cc: ankurjn at stanford.edu
> > Subject: Intel 3w Samples
> >
> > Hi SangBum,
> >
> > When you process the 3w samples with Au heaters on the Cr adhesion
> layer,
> > is
> > there a possibility that there is some material left on the surface of
> > the
> > Au? It seems that the patterned Au pads are extremely hard. I need to
> use
> > a
> > huge power/time setting to even make a dent but the bonds become either
> > very
> > fragile, or they do not stick at all when I am at this setting.
> >
> > I'm pretty sure this is not a problem with the wirebonder or what I am
> > doing. I can easily bond to the Au on the chip carrier and had no
> trouble
> > with Eric's TiN/TiX samples.
> >
> > Ankur have you ever had this problem? Alternatively, is there someone
> in
> > CIS
> > with more experience that can try the wirebonding?
> >
> > Thanks,
> > John
> >
> >
>
>
>


-- 
Liang Xu
Address: 59, Dudley Lane, Escondido Village, Apt B, Stanford, CA 94305
Tel: 650-497-1934


From vlordi at gmail.com  Wed Jun 14 11:44:51 2006
From: vlordi at gmail.com (Vincenzo Lordi)
Date: Wed, 14 Jun 2006 11:44:51 -0700
Subject: Wirebond to innotec gold
In-Reply-To: <1150306353.44904831b6dac@webmail.stanford.edu>
References: <C06EC1234EE78D4CB04D5B06AD849AB27BE1A9@paris.bridgewave.local>
	 <1150306353.44904831b6dac@webmail.stanford.edu>
Message-ID: <d3b901cf0606141144u55c50fbex5fb7a0b9258d9016@mail.gmail.com>

I agree. 200nm of evaporated Au should be fine and is not unusual.
I've done it successfully many times. Thick electroplated gold is not
required for wirebonding.

-Vince

On 6/14/06, Liang Xu <lxuwind at stanford.edu> wrote:
> I think 200nm is ok. I used 300nm gold, with Ta underneath for adhesion. It
> bonds pretty well.
>
> Quoting Eric Sanjuan <EricS at Bridgewave.com>:
>
> > I've never heard, or read, of anyone trying to wirebond onto gold so
> > thin, is this typical in some applications? Standard wirebonding occurs
> > onto Au pads that are microns thick, some applications call for a cyanide
> > (hard) Au plating bath, I typically use sulfite (soft) Au plating bath.
> > eric
> >
> > -----Original Message-----
> > From: SangBum Kim [mailto:kimsangb at stanford.edu]
> > Sent: Tuesday, June 13, 2006 1:54 PM
> > To: labmembers at snf.stanford.edu
> > Cc: 'John P. Reifenberg'; 'Yuan Zhang'
> > Subject: Wirebond to innotec gold
> >
> >
> > Dear all,
> >
> >  We are having problems to wirebond to gold pad (200nm thick, 2nm Cr
> > underneath for adhesion to 10nm thick SiO2.) which was evaporated at
> > Innotec
> > and then lift-offed. Here is the description of the problem.
> >
> > "When I try to bond to the patterned pads, it takes a huge amount of
> > power
> > and time to even make a mark on the pad compared to what it takes for
> > gold
> > pads on the chip carrier and other samples. I suspect this is because the
> > material is very hard."
> >
> >  Has anyone know why this is happening? Thanks in advance.
> >
> > SangBum
> >
> > -----Original Message-----
> > From: John P. Reifenberg [mailto:jreif at stanford.edu]
> > Sent: Monday, June 12, 2006 9:49 PM
> > To: SangBum Kim
> > Cc: ankurjn at stanford.edu; 'Yuan Zhang'
> > Subject: RE: Intel 3w Samples
> >
> > Hi SangBum,
> >
> > Thanks for your reply. In the short term I have sent four samples to
> > Pauline
> > for wire bonding. According to another student in our group, she will be
> > back tomorrow.
> >
> > When I try to bond to the patterned pads, it takes a huge amount of power
> > and time to even make a mark on the pad compared to what it takes for
> > gold
> > pads on the chip carrier and other samples. I suspect this is because the
> > material is very hard, but I do not know why it would be so hard. 99% of
> > the bonds do not stick and those that do are very fragile. I think the
> > bonds are breaking because the sonication of the tip of the wire is so
> > high
> > that it is affecting portions of wire up the strand. A better wire bonder
> > could be the solution if this is the problem, so Pauline may have better
> > luck than me, but it is still unclear why the gold would be so hard.
> >
> > My suspicion was that there may be some chemical on top of the gold due
> > to
> > the processing technique, but based on your description it sounds like
> > this
> > cannot be the case.
> >
> > I also do not think it is an oxide because chip carriers would be
> > affected
> > as well. I thought for a while that it may be the Au and Cr layers are
> > diffusing to form a very hard alloy, but since Cr is so commonly used as
> > an
> > adhesion layer for Au, I also doubt this is the case. To be honest I am
> > not
> > sure what path to pursue other than to ask the other groups using the
> > wire
> > bonder whether they have any insight. I will start there. If you have
> > other
> > suggestions, they would be very useful.
> >
> > Thanks
> > John
> >
> >
> >
> > Quoting SangBum Kim <kimsangb at stanford.edu>:
> >
> > > Dear John,
> > >
> > >  I used ebeam evaporator (innotec) to deposit Cr+Au layer. The
> > principle
> > > is
> > > to shoot high energy electrons to the chunk(target) of Cr or Au. Then
> > Cr
> > > or
> > > Au atoms are evaporated from the target, flies to the wafer and sticks
> > to
> > > it. The target itself is highly purified (at least 99%). The only
> > > contamination source I can think of is the case when the ebeam is
> > heating
> > > the crucible not the target so that you are evaporating the material of
> > > crucible, not the target. However, since I observed the point where the
> > > ebeam is heating during the process (It is a very bright spot.) I don't
> > > expect this to happen so severely. Yuan, any comment?
> > >
> > >  By the way, if there is something else on Au, what would it be? Metal?
> > > Oxide? And why is it a problem for wire-bonding? Let's figure this out.
> > > Feel
> > > free to ask any question if you have.
> > >
> > > Thanks,
> > > SangBum
> > >
> > > -----Original Message-----
> > > From: John P. Reifenberg [mailto:jreif at stanford.edu]
> > > Sent: Monday, June 12, 2006 12:16 PM
> > > To: kimsangb at stanford.edu
> > > Cc: ankurjn at stanford.edu
> > > Subject: Intel 3w Samples
> > >
> > > Hi SangBum,
> > >
> > > When you process the 3w samples with Au heaters on the Cr adhesion
> > layer,
> > > is
> > > there a possibility that there is some material left on the surface of
> > > the
> > > Au? It seems that the patterned Au pads are extremely hard. I need to
> > use
> > > a
> > > huge power/time setting to even make a dent but the bonds become either
> > > very
> > > fragile, or they do not stick at all when I am at this setting.
> > >
> > > I'm pretty sure this is not a problem with the wirebonder or what I am
> > > doing. I can easily bond to the Au on the chip carrier and had no
> > trouble
> > > with Eric's TiN/TiX samples.
> > >
> > > Ankur have you ever had this problem? Alternatively, is there someone
> > in
> > > CIS
> > > with more experience that can try the wirebonding?
> > >
> > > Thanks,
> > > John
> > >
> > >
> >
> >
> >
>
>
> --
> Liang Xu
> Address: 59, Dudley Lane, Escondido Village, Apt B, Stanford, CA 94305
> Tel: 650-497-1934
>


From sanli at stanford.edu  Wed Jun 14 11:32:42 2006
From: sanli at stanford.edu (Arif Sanli Ergun)
Date: Wed, 14 Jun 2006 11:32:42 -0700
Subject: Wirebond to innotec gold
In-Reply-To: <1150306353.44904831b6dac@webmail.stanford.edu>
References: <C06EC1234EE78D4CB04D5B06AD849AB27BE1A9@paris.bridgewave.local> <1150306353.44904831b6dac@webmail.stanford.edu>
Message-ID: <1150309962.4490564a5856d@webmail.stanford.edu>

As far as I know Au has to be 300+ nm thick for wire bonding.
I always use 300nm (over Ti/Pt) and it bonds very well. 200nm
is very close, I don't know. I suggest you try 300nm or more with
everything else remaining the same.


Quoting Liang Xu <lxuwind at stanford.edu>:

> I think 200nm is ok. I used 300nm gold, with Ta underneath for adhesion.
> It
> bonds pretty well.
>
> Quoting Eric Sanjuan <EricS at Bridgewave.com>:
>
> > I've never heard, or read, of anyone trying to wirebond onto gold so
> > thin, is this typical in some applications? Standard wirebonding occurs
> > onto Au pads that are microns thick, some applications call for a
> cyanide
> > (hard) Au plating bath, I typically use sulfite (soft) Au plating bath.
> > eric
> >
> > -----Original Message-----
> > From: SangBum Kim [mailto:kimsangb at stanford.edu]
> > Sent: Tuesday, June 13, 2006 1:54 PM
> > To: labmembers at snf.stanford.edu
> > Cc: 'John P. Reifenberg'; 'Yuan Zhang'
> > Subject: Wirebond to innotec gold
> >
> >
> > Dear all,
> >
> >  We are having problems to wirebond to gold pad (200nm thick, 2nm Cr
> > underneath for adhesion to 10nm thick SiO2.) which was evaporated at
> > Innotec
> > and then lift-offed. Here is the description of the problem.
> >
> > "When I try to bond to the patterned pads, it takes a huge amount of
> > power
> > and time to even make a mark on the pad compared to what it takes for
> > gold
> > pads on the chip carrier and other samples. I suspect this is because
> the
> > material is very hard."
> >
> >  Has anyone know why this is happening? Thanks in advance.
> >
> > SangBum
> >
> > -----Original Message-----
> > From: John P. Reifenberg [mailto:jreif at stanford.edu]
> > Sent: Monday, June 12, 2006 9:49 PM
> > To: SangBum Kim
> > Cc: ankurjn at stanford.edu; 'Yuan Zhang'
> > Subject: RE: Intel 3w Samples
> >
> > Hi SangBum,
> >
> > Thanks for your reply. In the short term I have sent four samples to
> > Pauline
> > for wire bonding. According to another student in our group, she will
> be
> > back tomorrow.
> >
> > When I try to bond to the patterned pads, it takes a huge amount of
> power
> > and time to even make a mark on the pad compared to what it takes for
> > gold
> > pads on the chip carrier and other samples. I suspect this is because
> the
> > material is very hard, but I do not know why it would be so hard. 99%
> of
> > the bonds do not stick and those that do are very fragile. I think the
> > bonds are breaking because the sonication of the tip of the wire is so
> > high
> > that it is affecting portions of wire up the strand. A better wire
> bonder
> > could be the solution if this is the problem, so Pauline may have
> better
> > luck than me, but it is still unclear why the gold would be so hard.
> >
> > My suspicion was that there may be some chemical on top of the gold due
> > to
> > the processing technique, but based on your description it sounds like
> > this
> > cannot be the case.
> >
> > I also do not think it is an oxide because chip carriers would be
> > affected
> > as well. I thought for a while that it may be the Au and Cr layers are
> > diffusing to form a very hard alloy, but since Cr is so commonly used
> as
> > an
> > adhesion layer for Au, I also doubt this is the case. To be honest I am
> > not
> > sure what path to pursue other than to ask the other groups using the
> > wire
> > bonder whether they have any insight. I will start there. If you have
> > other
> > suggestions, they would be very useful.
> >
> > Thanks
> > John
> >
> >
> >
> > Quoting SangBum Kim <kimsangb at stanford.edu>:
> >
> > > Dear John,
> > >
> > >  I used ebeam evaporator (innotec) to deposit Cr+Au layer. The
> > principle
> > > is
> > > to shoot high energy electrons to the chunk(target) of Cr or Au. Then
> > Cr
> > > or
> > > Au atoms are evaporated from the target, flies to the wafer and
> sticks
> > to
> > > it. The target itself is highly purified (at least 99%). The only
> > > contamination source I can think of is the case when the ebeam is
> > heating
> > > the crucible not the target so that you are evaporating the material
> of
> > > crucible, not the target. However, since I observed the point where
> the
> > > ebeam is heating during the process (It is a very bright spot.) I
> don't
> > > expect this to happen so severely. Yuan, any comment?
> > >
> > >  By the way, if there is something else on Au, what would it be?
> Metal?
> > > Oxide? And why is it a problem for wire-bonding? Let's figure this
> out.
> > > Feel
> > > free to ask any question if you have.
> > >
> > > Thanks,
> > > SangBum
> > >
> > > -----Original Message-----
> > > From: John P. Reifenberg [mailto:jreif at stanford.edu]
> > > Sent: Monday, June 12, 2006 12:16 PM
> > > To: kimsangb at stanford.edu
> > > Cc: ankurjn at stanford.edu
> > > Subject: Intel 3w Samples
> > >
> > > Hi SangBum,
> > >
> > > When you process the 3w samples with Au heaters on the Cr adhesion
> > layer,
> > > is
> > > there a possibility that there is some material left on the surface
> of
> > > the
> > > Au? It seems that the patterned Au pads are extremely hard. I need to
> > use
> > > a
> > > huge power/time setting to even make a dent but the bonds become
> either
> > > very
> > > fragile, or they do not stick at all when I am at this setting.
> > >
> > > I'm pretty sure this is not a problem with the wirebonder or what I
> am
> > > doing. I can easily bond to the Au on the chip carrier and had no
> > trouble
> > > with Eric's TiN/TiX samples.
> > >
> > > Ankur have you ever had this problem? Alternatively, is there someone
> > in
> > > CIS
> > > with more experience that can try the wirebonding?
> > >
> > > Thanks,
> > > John
> > >
> > >
> >
> >
> >
>
>
> --
> Liang Xu
> Address: 59, Dudley Lane, Escondido Village, Apt B, Stanford, CA 94305
> Tel: 650-497-1934
>




From cyril.vancura at rtc.bosch.com  Wed Jun 14 14:26:30 2006
From: cyril.vancura at rtc.bosch.com (Cyril Vancura)
Date: Wed, 14 Jun 2006 14:26:30 -0700
Subject: Wirebond to innotec gold
In-Reply-To: <1150306353.44904831b6dac@webmail.stanford.edu>
Message-ID: <0FA973A02BA84F769BD7D577FA14E7AB@pal.us.bosch.com>

Hi,
I also think that the thickness is not an issue as I have bonded without
problems onto 150 nm gold (5 nm Cr adhesion layer). How rough is the
underlying surface? Might that be a problem?

-----Original Message-----
From: Liang Xu [mailto:lxuwind at stanford.edu] 
Sent: Wednesday, June 14, 2006 10:33 AM
To: Eric Sanjuan
Cc: SangBum Kim; labmembers at snf.stanford.edu; John P. Reifenberg; Yuan
Zhang
Subject: RE: Wirebond to innotec gold


I think 200nm is ok. I used 300nm gold, with Ta underneath for adhesion.
It bonds pretty well.

Quoting Eric Sanjuan <EricS at Bridgewave.com>:

> I've never heard, or read, of anyone trying to wirebond onto gold so 
> thin, is this typical in some applications? Standard wirebonding 
> occurs onto Au pads that are microns thick, some applications call for

> a cyanide
> (hard) Au plating bath, I typically use sulfite (soft) Au plating
bath.
> eric
>
> -----Original Message-----
> From: SangBum Kim [mailto:kimsangb at stanford.edu]
> Sent: Tuesday, June 13, 2006 1:54 PM
> To: labmembers at snf.stanford.edu
> Cc: 'John P. Reifenberg'; 'Yuan Zhang'
> Subject: Wirebond to innotec gold
>
>
> Dear all,
>
>  We are having problems to wirebond to gold pad (200nm thick, 2nm Cr 
> underneath for adhesion to 10nm thick SiO2.) which was evaporated at 
> Innotec and then lift-offed. Here is the description of the problem.
>
> "When I try to bond to the patterned pads, it takes a huge amount of 
> power and time to even make a mark on the pad compared to what it 
> takes for gold
> pads on the chip carrier and other samples. I suspect this is because
the
> material is very hard."
>
>  Has anyone know why this is happening? Thanks in advance.
>
> SangBum
>
> -----Original Message-----
> From: John P. Reifenberg [mailto:jreif at stanford.edu]
> Sent: Monday, June 12, 2006 9:49 PM
> To: SangBum Kim
> Cc: ankurjn at stanford.edu; 'Yuan Zhang'
> Subject: RE: Intel 3w Samples
>
> Hi SangBum,
>
> Thanks for your reply. In the short term I have sent four samples to 
> Pauline for wire bonding. According to another student in our group, 
> she will be back tomorrow.
>
> When I try to bond to the patterned pads, it takes a huge amount of 
> power and time to even make a mark on the pad compared to what it 
> takes for gold pads on the chip carrier and other samples. I suspect 
> this is because the material is very hard, but I do not know why it 
> would be so hard. 99% of the bonds do not stick and those that do are 
> very fragile. I think the bonds are breaking because the sonication of

> the tip of the wire is so high
> that it is affecting portions of wire up the strand. A better wire
bonder
> could be the solution if this is the problem, so Pauline may have
better
> luck than me, but it is still unclear why the gold would be so hard.
>
> My suspicion was that there may be some chemical on top of the gold 
> due to the processing technique, but based on your description it 
> sounds like this
> cannot be the case.
>
> I also do not think it is an oxide because chip carriers would be 
> affected as well. I thought for a while that it may be the Au and Cr 
> layers are diffusing to form a very hard alloy, but since Cr is so 
> commonly used as an
> adhesion layer for Au, I also doubt this is the case. To be honest I
am
> not
> sure what path to pursue other than to ask the other groups using the
> wire
> bonder whether they have any insight. I will start there. If you have
> other
> suggestions, they would be very useful.
>
> Thanks
> John
>
>
>
> Quoting SangBum Kim <kimsangb at stanford.edu>:
>
> > Dear John,
> >
> >  I used ebeam evaporator (innotec) to deposit Cr+Au layer. The
> principle
> > is
> > to shoot high energy electrons to the chunk(target) of Cr or Au. 
> > Then
> Cr
> > or
> > Au atoms are evaporated from the target, flies to the wafer and 
> > sticks
> to
> > it. The target itself is highly purified (at least 99%). The only 
> > contamination source I can think of is the case when the ebeam is
> heating
> > the crucible not the target so that you are evaporating the material

> > of crucible, not the target. However, since I observed the point 
> > where the ebeam is heating during the process (It is a very bright 
> > spot.) I don't expect this to happen so severely. Yuan, any comment?
> >
> >  By the way, if there is something else on Au, what would it be? 
> > Metal? Oxide? And why is it a problem for wire-bonding? Let's figure

> > this out. Feel free to ask any question if you have.
> >
> > Thanks,
> > SangBum
> >
> > -----Original Message-----
> > From: John P. Reifenberg [mailto:jreif at stanford.edu]
> > Sent: Monday, June 12, 2006 12:16 PM
> > To: kimsangb at stanford.edu
> > Cc: ankurjn at stanford.edu
> > Subject: Intel 3w Samples
> >
> > Hi SangBum,
> >
> > When you process the 3w samples with Au heaters on the Cr adhesion
> layer,
> > is
> > there a possibility that there is some material left on the surface 
> > of the Au? It seems that the patterned Au pads are extremely hard. I

> > need to
> use
> > a
> > huge power/time setting to even make a dent but the bonds become 
> > either very fragile, or they do not stick at all when I am at this 
> > setting.
> >
> > I'm pretty sure this is not a problem with the wirebonder or what I 
> > am doing. I can easily bond to the Au on the chip carrier and had no
> trouble
> > with Eric's TiN/TiX samples.
> >
> > Ankur have you ever had this problem? Alternatively, is there 
> > someone
> in
> > CIS
> > with more experience that can try the wirebonding?
> >
> > Thanks,
> > John
> >
> >
>
>
>


-- 
Liang Xu
Address: 59, Dudley Lane, Escondido Village, Apt B, Stanford, CA 94305
Tel: 650-497-1934




From mzi9890 at att.net  Wed Jun 14 14:22:58 2006
From: mzi9890 at att.net (mzi9890 at att.net)
Date: Wed, 14 Jun 2006 21:22:58 +0000
Subject: Wirebond to innotec gold
Message-ID: <061420062122.9318.44907E32000570CE000024662160376316CFC7C8C7079603@att.net>

I have done 120nm Au on Cr adhesion layer many times and they bonded
fine. It is not required to have 300+ nm Au for bonding, that is just
waste of Au. Innotec has a big chamber and you are evaporating lot
of costly metal to get 300+nm. 

 
 -------------- Original message ----------------------
From: Arif Sanli Ergun <sanli at stanford.edu>
> As far as I know Au has to be 300+ nm thick for wire bonding.
> I always use 300nm (over Ti/Pt) and it bonds very well. 200nm
> is very close, I don't know. I suggest you try 300nm or more with
> everything else remaining the same.
> 
> 
> Quoting Liang Xu <lxuwind at stanford.edu>:
> 
> > I think 200nm is ok. I used 300nm gold, with Ta underneath for adhesion.
> > It
> > bonds pretty well.
> >
> > Quoting Eric Sanjuan <EricS at Bridgewave.com>:
> >
> > > I've never heard, or read, of anyone trying to wirebond onto gold so
> > > thin, is this typical in some applications? Standard wirebonding occurs
> > > onto Au pads that are microns thick, some applications call for a
> > cyanide
> > > (hard) Au plating bath, I typically use sulfite (soft) Au plating bath.
> > > eric
> > >
> > > -----Original Message-----
> > > From: SangBum Kim [mailto:kimsangb at stanford.edu]
> > > Sent: Tuesday, June 13, 2006 1:54 PM
> > > To: labmembers at snf.stanford.edu
> > > Cc: 'John P. Reifenberg'; 'Yuan Zhang'
> > > Subject: Wirebond to innotec gold
> > >
> > >
> > > Dear all,
> > >
> > >  We are having problems to wirebond to gold pad (200nm thick, 2nm Cr
> > > underneath for adhesion to 10nm thick SiO2.) which was evaporated at
> > > Innotec
> > > and then lift-offed. Here is the description of the problem.
> > >
> > > "When I try to bond to the patterned pads, it takes a huge amount of
> > > power
> > > and time to even make a mark on the pad compared to what it takes for
> > > gold
> > > pads on the chip carrier and other samples. I suspect this is because
> > the
> > > material is very hard."
> > >
> > >  Has anyone know why this is happening? Thanks in advance.
> > >
> > > SangBum
> > >
> > > -----Original Message-----
> > > From: John P. Reifenberg [mailto:jreif at stanford.edu]
> > > Sent: Monday, June 12, 2006 9:49 PM
> > > To: SangBum Kim
> > > Cc: ankurjn at stanford.edu; 'Yuan Zhang'
> > > Subject: RE: Intel 3w Samples
> > >
> > > Hi SangBum,
> > >
> > > Thanks for your reply. In the short term I have sent four samples to
> > > Pauline
> > > for wire bonding. According to another student in our group, she will
> > be
> > > back tomorrow.
> > >
> > > When I try to bond to the patterned pads, it takes a huge amount of
> > power
> > > and time to even make a mark on the pad compared to what it takes for
> > > gold
> > > pads on the chip carrier and other samples. I suspect this is because
> > the
> > > material is very hard, but I do not know why it would be so hard. 99%
> > of
> > > the bonds do not stick and those that do are very fragile. I think the
> > > bonds are breaking because the sonication of the tip of the wire is so
> > > high
> > > that it is affecting portions of wire up the strand. A better wire
> > bonder
> > > could be the solution if this is the problem, so Pauline may have
> > better
> > > luck than me, but it is still unclear why the gold would be so hard.
> > >
> > > My suspicion was that there may be some chemical on top of the gold due
> > > to
> > > the processing technique, but based on your description it sounds like
> > > this
> > > cannot be the case.
> > >
> > > I also do not think it is an oxide because chip carriers would be
> > > affected
> > > as well. I thought for a while that it may be the Au and Cr layers are
> > > diffusing to form a very hard alloy, but since Cr is so commonly used
> > as
> > > an
> > > adhesion layer for Au, I also doubt this is the case. To be honest I am
> > > not
> > > sure what path to pursue other than to ask the other groups using the
> > > wire
> > > bonder whether they have any insight. I will start there. If you have
> > > other
> > > suggestions, they would be very useful.
> > >
> > > Thanks
> > > John
> > >
> > >
> > >
> > > Quoting SangBum Kim <kimsangb at stanford.edu>:
> > >
> > > > Dear John,
> > > >
> > > >  I used ebeam evaporator (innotec) to deposit Cr+Au layer. The
> > > principle
> > > > is
> > > > to shoot high energy electrons to the chunk(target) of Cr or Au. Then
> > > Cr
> > > > or
> > > > Au atoms are evaporated from the target, flies to the wafer and
> > sticks
> > > to
> > > > it. The target itself is highly purified (at least 99%). The only
> > > > contamination source I can think of is the case when the ebeam is
> > > heating
> > > > the crucible not the target so that you are evaporating the material
> > of
> > > > crucible, not the target. However, since I observed the point where
> > the
> > > > ebeam is heating during the process (It is a very bright spot.) I
> > don't
> > > > expect this to happen so severely. Yuan, any comment?
> > > >
> > > >  By the way, if there is something else on Au, what would it be?
> > Metal?
> > > > Oxide? And why is it a problem for wire-bonding? Let's figure this
> > out.
> > > > Feel
> > > > free to ask any question if you have.
> > > >
> > > > Thanks,
> > > > SangBum
> > > >
> > > > -----Original Message-----
> > > > From: John P. Reifenberg [mailto:jreif at stanford.edu]
> > > > Sent: Monday, June 12, 2006 12:16 PM
> > > > To: kimsangb at stanford.edu
> > > > Cc: ankurjn at stanford.edu
> > > > Subject: Intel 3w Samples
> > > >
> > > > Hi SangBum,
> > > >
> > > > When you process the 3w samples with Au heaters on the Cr adhesion
> > > layer,
> > > > is
> > > > there a possibility that there is some material left on the surface
> > of
> > > > the
> > > > Au? It seems that the patterned Au pads are extremely hard. I need to
> > > use
> > > > a
> > > > huge power/time setting to even make a dent but the bonds become
> > either
> > > > very
> > > > fragile, or they do not stick at all when I am at this setting.
> > > >
> > > > I'm pretty sure this is not a problem with the wirebonder or what I
> > am
> > > > doing. I can easily bond to the Au on the chip carrier and had no
> > > trouble
> > > > with Eric's TiN/TiX samples.
> > > >
> > > > Ankur have you ever had this problem? Alternatively, is there someone
> > > in
> > > > CIS
> > > > with more experience that can try the wirebonding?
> > > >
> > > > Thanks,
> > > > John
> > > >
> > > >
> > >
> > >
> > >
> >
> >
> > --
> > Liang Xu
> > Address: 59, Dudley Lane, Escondido Village, Apt B, Stanford, CA 94305
> > Tel: 650-497-1934
> >
> 
> 




From shott at stanford.edu  Thu Jun 15 06:28:35 2006
From: shott at stanford.edu (John Shott)
Date: Thu, 15 Jun 2006 06:28:35 -0700
Subject: Minor chance when logging in/out of Sunrays ...
Message-ID: <44916083.2070600@stanford.edu>

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From lscjblue at yahoo.com  Thu Jun 15 08:42:39 2006
From: lscjblue at yahoo.com (Ping Zhang)
Date: Thu, 15 Jun 2006 10:42:39 -0500
Subject: Wirebond to platinum substrate
Message-ID: <mailman.18.1356287134.5865.labmembers@snf.stanford.edu>

Dear all:

  I wonder if gold wire can be bonded to titanium and platinum pad.

Thanks.

Best regards, 
  
Ping 




From sergei at scipp.ucsc.edu  Thu Jun 15 12:15:13 2006
From: sergei at scipp.ucsc.edu (Sergei Kachiguin)
Date: Thu, 15 Jun 2006 12:15:13 -0700
Subject: Wirebond to platinum substrate
In-Reply-To: <20060615162838.C1CC24C472@smtp3.stanford.edu>
References: <20060615162838.C1CC24C472@smtp3.stanford.edu>
Message-ID: <4491B1C1.4060707@scipp.ucsc.edu>

Hi Ping,

I've never tried gold wire bonding to titanium, but aluminum wire
bonding to titanium pads works really well. I had to wirebond several
samples (titanium on silicon) couple months ago and got respectful
12-14g in pullout test.

Sergei

Ping Zhang wrote:

>Dear all:
>
>  I wonder if gold wire can be bonded to titanium and platinum pad.
>
>Thanks.
>
>Best regards, 
>  
>Ping
>  
>



From alex at teloptics.com  Thu Jun 15 14:06:01 2006
From: alex at teloptics.com (Alexander Romanovsky)
Date: Thu, 15 Jun 2006 14:06:01 -0700
Subject: Wirebond to platinum substrate
In-Reply-To: <20060615154933.99D9C4C346@smtp3.stanford.edu>
Message-ID: <NLEAKGMMPBLFJOMIKGAKEEJICOAA.alex@teloptics.com>

To Ping,
	Gold wire can be bonded to platinum or platinum on titanium. But not on
titanium directly. If you wish to try bonding gold on platinum e-mail Hybrid
Circuits Inc. at info at hybridcircuits.com or call (408)744-9080. Ask for
Mike.

Regards,

Alex

-----Original Message-----
From: Ping Zhang [mailto:lscjblue at yahoo.com]
Sent: Thursday, June 15, 2006 8:43 AM
To: labmembers at snf.stanford.edu
Subject: Wirebond to platinum substrate


Dear all:

  I wonder if gold wire can be bonded to titanium and platinum pad.

Thanks.

Best regards,

Ping





From rcrane at stanford.edu  Mon Jun 19 13:46:51 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Mon, 19 Jun 2006 13:46:51 -0700
Subject: No hot water 6/19-6/20
Message-ID: <44970D3B.4000207@stanford.edu>

Domestic hot water users of CIS/CISX buildings,

The domestic hot water system pump for the building has a leak and is 
being repaired. Building restroom sinks and showers will not have hot 
water service for the rest of today and tomorrow until  late afternoon. 
Tempered water for the emergency eyewashes and showers will be also be 
affected. Cold water only will be supplied.

Sorry for the inconvenience,

Dick



From rcrane at stanford.edu  Mon Jun 19 15:35:20 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Mon, 19 Jun 2006 15:35:20 -0700
Subject: Reduced cooling in office area
Message-ID: <449726A8.3070408@stanford.edu>

CIS and CISX dwellers,

Due to problems at the steam plant (cogen next door), chilled water 
supply has been reduced throughout campus today. This curtailment may 
last into next week if hot weather continues to increase chilled water 
demand. CIS/CISX building office areas will be warmer than normal during 
this time. The SNF lab and equipment will not be affected by this action.

Sorry for the inconvenience,

Dick



From akamath at kovio.com  Tue Jun 20 10:30:13 2006
From: akamath at kovio.com (Arvind Kamath)
Date: Tue, 20 Jun 2006 10:30:13 -0700
Subject: Wirebonding Services
Message-ID: <17AB8DED04002F4E803EE9A3E29ECFA8599D5E@koviomail.print-this.com>

Hi,

     We are looking to find reliable wirebonding services with quick
turnaround. I did see an earlier post mentioning a company called Hybrid
Circuits.
	If you could send me contact information for any others it would
be much appreciated.
			Thanks,
					Arvind Kamath




From rcrane at stanford.edu  Tue Jun 20 10:49:00 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Tue, 20 Jun 2006 10:49:00 -0700
Subject: Hot water Cold water
Message-ID: <4498350C.2030904@stanford.edu>

CIS/CISX building and SNF fab people,

The domestic hot water system is back up. Restroom sinks and showers now 
have hot water available. Emergency eyewashes and showers have water 
tempering restored. (They always had water available is case of an 
emergency.)

The chilled water system is now providing chilled water for office area 
cooling. We may experience additional curtailments in the next few days 
if the weather stays hot.

Thanks for your patience,

Dick



From dwlee at stanford.edu  Tue Jun 20 14:51:40 2006
From: dwlee at stanford.edu (Dok Won Lee)
Date: Tue, 20 Jun 2006 14:51:40 -0700
Subject: Polyimide planarization
Message-ID: <1150840300.44986dec250ed@webmail.stanford.edu>

Hello,

I have 4" wafers with the Cu bar patterns having depth (or height) of 10 um.
They will be spin-coated with PI-2611 polyimide. Even though the polyimide
coating will do some planarization, I expect to have remaining step heights
(2~5 um) due to the Cu bar patterns. I would like to have the polyimide
layer planarized (either CMP or mechanical polishing) to obtain the smooth
surface with the final step height below 0.5 um and the remaining polyimide
thickness of 1~2 um above the Cu patterns. Do you know any facilities at
Stanford or outside vendors that can handle this work?

Thank you in advance.


Regards,

Dok Won


From mtang at stanford.edu  Wed Jun 21 09:47:03 2006
From: mtang at stanford.edu (Mary Tang)
Date: Wed, 21 Jun 2006 09:47:03 -0700
Subject: Find the PERFECT Safety Glasses for you - today!
Message-ID: <44997807.3070908@stanford.edu>

Hi everyone --

This is a public service announcement. 

Safety glasses have come a long way from the heavy, 
one-size-one-style-fits-all that us old-timers used to have to live 
with...  Nowadays, they come in styles to fit all face and nose shapes 
and are even fashionable. 

Jackie Chan, Health & Safety Specialist from the School of Engineering, 
will be in the CIS breakroom today from 11:30-12:30, with a collection 
of sample non-prescription safety glasses that you can try on.  It can 
make a world of difference in your ability to work productively in the 
lab when your ears don't ache and you don't have to worry about your 
safety glasses slipping off your nose into equipment or onto your 
samples...  and you can make a bold fashion statement as well as protect 
your vision...  all for less than $6.  So, come on by and see if there's 
something there for you.

Your SNF Safety Committee (safety at snf)

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From jerabek at snf.stanford.edu  Wed Jun 21 15:32:35 2006
From: jerabek at snf.stanford.edu (Paul Jerabek)
Date: Wed, 21 Jun 2006 15:32:35 -0700 (PDT)
Subject: mask writer
Message-ID: <Pine.LNX.4.04.10606211530390.26490-100000@snf.stanford.edu>

 To whom it may concern:
our Laser mask writer is down due to poor stage tracking.
Field service has been called to address the problem.
-Paul



From mtang at stanford.edu  Wed Jun 21 15:38:55 2006
From: mtang at stanford.edu (Mary Tang)
Date: Wed, 21 Jun 2006 15:38:55 -0700
Subject: Seminar:  Avanced Packaging for Optical & Electronic Applications,
 June 30
Message-ID: <4499CA7F.9090407@stanford.edu>

Labmembers:

Fellow labmember, Ofer Levi, is hosting a visit and seminar by Dr. Ruth 
Houbertz and invites labmembers to attend. Dr. Houbertz' seminar will be 
on Friday, June 30, at 2 pm in the CISX Auditorium. She will be 
available for individual discussions following her seminar. Her abstract 
and bio follow:
**

********************************************************************************
*

*Advanced packaging materials for optical and electronic application - 
bridging the gap between nm-size structures and large-area panel processing*

Ruth Houbertz, Fraunhofer ISC, Neunerplatz 2, 97089 W?rzburg, Germany

Houbertz at isc.fhg.de

Integrated passive and active devices are the key components in current 
and future information technology. In order to fulfill requirements in 
miniaturization for (integrated) optical or electronic devices, 
nano-scaled materials with a good compatibility to conventional 
processing techniques are searched for. As the range of applications has 
been increased, the requirements on the materials were significantly 
increased as well. Not only excellent optical and electrical properties, 
but also very good thermal, mechanical and chemical stability are required.

Building materials from the bottom-up is complementary to conventional 
top-down materials processing. Both approaches require a fundamental 
understanding of the individual processes, for example of the chemical 
synthesis of tailored materials, and their technological processing. A 
particular class of nanoscale materials are inorganic-organic hybrid 
polymers (ORMOCER^? s). The material class will be described and 
selected application examples will be given.


        Short CV

*Ruth Houbertz *has studied physics at the Saarland University, and 
received her diploma in 1989. She received her PhD in physical chemistry 
from the University of Ulm (both Germany), in J?rgen Behm?s group in 
1993. Since her return (2000) from the Sandia National Laboratories (Ca, 
USA), where she worked in the Dept. of Materials Physics (Chemical 
Engineering and Interfaces) with Bob Hwang, she works at the 
Fraunhofer-ISC in W?rzburg (Germany), managing the Competence Team 
?Hybrid Polymers for Microsystems? since 2002. She is specialized in 
surface physics, electrochemistry, materials engineering, and technology.

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From izuleta at stanford.edu  Thu Jun 22 15:15:33 2006
From: izuleta at stanford.edu (Ignacio A. Zuleta)
Date: Thu, 22 Jun 2006 15:15:33 -0700
Subject: FW: MICROFABRICATED FLOW CELL - NEED HELP
Message-ID: <000e01c69649$613ffbc0$23bff340$@edu>

Dear Labmembers,

A member of my research group and I are looking to find a flow cell for our
setups. Is any of you aware of a company that sells transparent
micro-fabricated flow cells or a lab on campus that would be willing to
share one with us? We are in the search of a square channel with transparent
walls made of pyrex or even better quartz. Side walls could be made of
silicon, but top and bottom walls should be transparent. Also the cross
section should be in the 50x50um to 100x100um range and interfacing would be
trough ports in the surface, not in the edges. Also, I am looking for other
geometries, like mixers and splitters. Thanks in advance for your insight
and/or comments.

-ignacio a. zuleta

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From mtang at stanford.edu  Thu Jun 22 15:55:04 2006
From: mtang at stanford.edu (Mary Tang)
Date: Thu, 22 Jun 2006 15:55:04 -0700
Subject: Brewer Products/Contact Planarization Method
Message-ID: <449B1FC8.2010401@stanford.edu>

Hi all --

Just following up on the presentation that Brewer Science made to us a 
few weeks ago....

First, they have offered to provide us with some "samples" of their 
materials.  There is a very limited shelf life for most of the 
materials.  So, if you are interested, we should try to coordinate this.

Second, there is a possibility we may be able to gain access to a 
contact planarization system.  Basically, this "consists of an optical 
flat to press planarity into a malleable substrate that has been placed 
over topography"  and has been demonstrated to effectively planarize 
trench structures up to 70 microns deep.  If you're interested, let me 
know and I can send you more detailed info.  The system is from Brewer 
Science and the description can be found here: 
http://www.brewerscience.com/products/con-tact/
and here:
http://www.brewerscience.com/fileadmin/bsi/home/products/CON-TACT/cp_and_barc_06.pdf


Mary

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From rcrane at stanford.edu  Fri Jun 23 08:31:35 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Fri, 23 Jun 2006 08:31:35 -0700
Subject: Chilled water information
Message-ID: <449C0957.2020807@stanford.edu>

Cooling relief is on the way.

Dick

> ----- Original Message -----
> From: Chris Christofferson <mailto:chrisc at bonair.stanford.edu>
> To: The University Cabinet <mailto:The%20University%20Cabinet>
> Sent: Thursday, June 22, 2006 5:05 PM
> Subject: Cooling curtailment
>
> Colleagues,
>
> I'm sending this message to you at Bob Reidy's request.
>
> As you may be aware, the University has had a shortage of chilled water
> since the start of the heat wave last Friday, June 16th.  We implemented a
> Chilled Water curtailment over Commencement weekend while being sensitive
> to Commencement-related activities.  Chilled Water capacity remains
> extremely limited because of a continuing construction project in the 
> Central Energy Facility.
>
> What we've done so far:
>
> In order to meet critical peak demands, chilled water temperatures have
> been slightly elevated throughout campus during the week, heating systems
> have been turned off, and comfort cooling has been reduced where possible
> to save chilled water for critical processes and hospital use. As a 
> result of curtailing building preheating in the early morning hours, 
> some areas may actually be colder than usual early in the morning and 
> warmer in the afternoon.
>
> Next steps:
>
> We expect some relief from the hot weather this weekend and possibly next
> week.  In the meantime, we have arranged for the installation of 
> supplemental cooling in the form of a temporary chilled water plant on 
> Roble Field. Our plan is to have an additional 1,000 tons of cooling 
> in place by Monday morning, and an additional 2,000 tons in place by 
> next Friday. As this additional cooling becomes available and 
> temperatures stabilize, we will gradually phase out of the 
> curtailment.  We have a committment from the vendor that this 
> equipment will remain in place as long as it is needed.
>
> In the meantime, Facility Operations Zone Management staff will stay 
> in regular communications with your building managers, addressing 
> their concerns as they arise and continuing to be sensitive to both 
> research requirements and scheduled events in the buildings.
>
> Thank you for your patience and understanding.
>
> Chris Christofferson
> Associate Vice Provost for Facilities

                                                                   
George E. Sandoval         Phone: (650) 725-3670
Fac. Ops. Zone A / Zone Engineering Mgr.
Stanford University           
333 Bonair Siding
Stanford, CA 94305-7273

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From mbaran at stanford.edu  Fri Jun 23 09:51:13 2006
From: mbaran at stanford.edu (Maureen Baran)
Date: Fri, 23 Jun 2006 09:51:13 -0700
Subject: Lost Earring found in the Lab
Message-ID: <20060623165113.BE5B14CACA@smtp2.stanford.edu>

Some kind labmember found a lone earring in the lab.  It is set in gold with
a blue background and a light blue, burgundy, and lilac bird on it.  If I
have described your lost earring, please come to cubicle 41 and claim it.

 

Maureen

 

Maureen Baran

Stanford Nanofabrication Facility

Lab Services Administrator

mbaran at stanford.edu

650-725-3664

 

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From rcrane at stanford.edu  Fri Jun 23 11:02:24 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Fri, 23 Jun 2006 11:02:24 -0700
Subject: Campus heating/cooling facts
Message-ID: <449C2CB0.8020403@stanford.edu>

Building dwellers:

A number of questions have arisen as to why other areas/buildings are 
cooler (or hotter) than CIS/CISX. The following is a brief tutorial on 
how the campus heating/cooling system functions.

Where it all starts:

The prime mover of the heating/cooling system are the natural gas fired 
steam boilers located next door (to the west) at the Cardinal Cogen 
Plant. This plant produces steam with electricity as a byproduct (60MW). 
Surplus electricity is sold to PG&E. The steam is fed to the Center 
Energy Facility (next to Cogen) to power absorption chillers which 
produces chilled water (you add heat to make ice!). Steam is also used 
heat the campus buildings. Chilled water is stored as ice in a million 
gallon, underground reservoir located beneath the parking lot north of 
Pine Hall. By day, the campus is cooled by a combination of chilled 
water from the ice reservoir and directly from the chillers. At night, 
the extra chiller capacity is used to make make ice for the next day's 
needs.

What is not working?

The cogen plant has recently completed a major boiler upgrade and is up. 
The Central Energy Plant is currently upgrading its chillers. Of the 
three, 3,000 ton chillers, only one is operational at this time. The 
heat wave is adding load on the chilled water system at a time when the 
system capacity is down by two-thirds, hence the stage two curtailment 
and the warm offices.

Why are some areas cooler than others?

The campus has over 1,000 buildings with most connected the campus 
heating/cooling system. The Energy Management Computer System (EMCS) is 
reducing cooling loads by increasing the set point temperature in 
non-critical spaces (offices, meeting rooms, classrooms, etc.) and 
shutting down steam heating. In general, the air in a building's 
heating/cooling system is over-cooled and then locally reheated to meet 
a particular room's temperature setpoint. With the steam heating reduced 
or shutdown, the hot weather heat load, and reduced chiller capacity, 
the whole system is out of balance. The result is wacky temperatures 
within the same building and differences between buildings.

Thanks for your time,

Dick



From jerabek at snf.stanford.edu  Fri Jun 23 14:02:31 2006
From: jerabek at snf.stanford.edu (Paul Jerabek)
Date: Fri, 23 Jun 2006 14:02:31 -0700 (PDT)
Subject: Laser mask writer
Message-ID: <Pine.LNX.4.04.10606231400390.22363-100000@snf.stanford.edu>

 Laser mask writer is back on line. Micronic field service replaced
demaged optical head cable.
-Paul



From organizer at nanotech.net  Wed Jun 28 17:06:58 2006
From: organizer at nanotech.net (NTNE Organizer)
Date: Thu, 29 Jun 2006 03:06:58 +0300
Subject: Nanotech Northern Europe, 27-29 March 2007, Helsinki - Mark your
 calendar
Message-ID: <SPINSRV8g4RMqgryA2T00003351@spinsrv.spinverse.local>

 - This mail is a HTML mail. Not all elements could be shown in plain text mode. -

Mark your calendar now!
Nanotech Northern Europe 2007
27-29 March,
Helsinki
,
Finland
www.nanotech.net

Building partnerships to create new business
NTNE2007 is the largest nanotechnology event in
Northern Europe
bringing together top scientists, innovative companies, investors, policy makers and service providers.

In 2007, Nanotech Northern Europe is held in parallel with ChemBio
Finland
07, combining the region?s most significant events in nanotechnology, biotechnology and chemistry. These exciting new synergies are expected to attract close to 10000 visitors!

Key themes for NTNE2007 are application driven, focusing on
Electronics and photonics solutions
Diagnostics and biomaterials
Nanotechnology instruments and tools

In addition, the congress includes special program on
Business development and strategy
IPR questions
Safety of nanotechnology
National initiatives and regional networks
Education and everyday nano
Jobs in nanotechnology

Key objective is to create new partnerships between:
Leading nanotechnology research organisations
Innovative small and medium-size enterprises
Large companies
Instrument manufacturers
Investor
s
Funding organisations and policy makers

Download NTNE2006 presentations
NTNE 2006 attracted over 650 experts from 25 countries. More than 100 companies participated in the exhibition and surrounding events! For more information on NTNE2007 and to download presentations, visit:
www.nanotech.net


Lead organizer :
Spinverse Consulting


If you do not wish to receive any further information from NTNE 2007
database
, please send an email to
unsubscribe at nanotech.net
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From auprabhu at yahoo.com  Thu Jun 29 12:44:13 2006
From: auprabhu at yahoo.com (prabhu arumugam)
Date: Thu, 29 Jun 2006 12:44:13 -0700 (PDT)
Subject: wafersaw
Message-ID: <20060629194413.28130.qmail@web60821.mail.yahoo.com>

Dear labmembers,
if anyone is using wafersaw in the coming days, please
let me know. i would like to get familiar with the
process.

Thanks
Prabhu

__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 


From mtang at stanford.edu  Fri Jun 30 10:01:42 2006
From: mtang at stanford.edu (Mary Tang)
Date: Fri, 30 Jun 2006 10:01:42 -0700
Subject: Reminder Seminar today: Avanced Packaging for Optical & Electronic
 Applications, 2 pm
Message-ID: <44A558F6.2070308@stanford.edu>

Labmembers:

Fellow labmember, Ofer Levi, is hosting a visit and seminar by Dr. Ruth 
Houbertz and invites labmembers to attend. Dr. Houbertz' seminar will be 
on Friday, June 30, at 2 pm in the CISX Auditorium. She will be 
available for individual discussions following her seminar. Her abstract 
and bio follow:
**

********************************************************************************
*

*Advanced packaging materials for optical and electronic application - 
bridging the gap between nm-size structures and large-area panel processing*

Ruth Houbertz, Fraunhofer ISC, Neunerplatz 2, 97089 W?rzburg, Germany

Houbertz at isc.fhg.de

Integrated passive and active devices are the key components in current 
and future information technology. In order to fulfill requirements in 
miniaturization for (integrated) optical or electronic devices, 
nano-scaled materials with a good compatibility to conventional 
processing techniques are searched for. As the range of applications has 
been increased, the requirements on the materials were significantly 
increased as well. Not only excellent optical and electrical properties, 
but also very good thermal, mechanical and chemical stability are required.

Building materials from the bottom-up is complementary to conventional 
top-down materials processing. Both approaches require a fundamental 
understanding of the individual processes, for example of the chemical 
synthesis of tailored materials, and their technological processing. A 
particular class of nanoscale materials are inorganic-organic hybrid 
polymers (ORMOCER^? s). The material class will be described and 
selected application examples will be given.


        Short CV

*Ruth Houbertz *has studied physics at the Saarland University, and 
received her diploma in 1989. She received her PhD in physical chemistry 
from the University of Ulm (both Germany), in J?rgen Behm?s group in 
1993. Since her return (2000) from the Sandia National Laboratories (Ca, 
USA), where she worked in the Dept. of Materials Physics (Chemical 
Engineering and Interfaces) with Bob Hwang, she works at the 
Fraunhofer-ISC in W?rzburg (Germany), managing the Competence Team 
?Hybrid Polymers for Microsystems? since 2002. She is specialized in 
surface physics, electrochemistry, materials engineering, and technology.

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From mtang at stanford.edu  Fri Jun 30 13:04:28 2006
From: mtang at stanford.edu (Mary Tang)
Date: Fri, 30 Jun 2006 13:04:28 -0700
Subject: Cell phone found...
Message-ID: <44A583CC.6020803@stanford.edu>

Hi!

Someone left a cell phone in the Shipping & Receiving area.  If this is 
yours, please go to S&R or contact David Cala.

Mary

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From mahnaz at snf.stanford.edu  Fri Jun 30 17:24:03 2006
From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour)
Date: Fri, 30 Jun 2006 17:24:03 -0700
Subject: Bonder/aligner
Message-ID: <44A5C0A3.2070706@snf.stanford.edu>

Hello all,

There will be a presentation on the EVG  bonder on Thursday July 6th  
given by Chad Brubaker at
 10 am in the lab, if you need bond training  please attend the session. 
If you need to discuss your process or have any questions please come by 
as well.
The aligner training will be at 2 pm same day in the lab.

mahnaz
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