From rohank at stanford.edu  Wed Nov  1 20:57:36 2006
From: rohank at stanford.edu (Rohan D Kekatpure)
Date: Wed, 01 Nov 2006 20:57:36 -0800
Subject: Absorption measurement: Options
Message-ID: <45497AC0.3080600@stanford.edu>

Dear all,

I have a silicon rich oxide film and I am looking to measure its 
absorption coefficient (in the units of (length)^-1).  Recently I tried 
spectroscopic Ellipsometry to get the values of 'k' (and hence alpha) 
but the technique is not sensitive enough to provide the values of 'k' 
in the wavelength range I want (~750 nm). I expect the value of 
absorption coefficient to be around 50 cm^-1 (@750 nm) and the 
corresponding 'k' is ~ 1.0E-4. The ellipsometric technique I used was 
sensitive only upto k>1.0E-3.

Therefore, I am on the lookout for other options for the measurement of 
alpha. I am able to fabricate my film on transparent as well as opaque 
substrates. Moreover, I know the refractive index of my film at various 
wavelengths with reasonable accuracy.

It would be great if you could share your insights and experiences 
related to this type of measurement or point me toward 
commercial/academic equipments.

Thanks in advance for your help and suggestions.

-rohan

-- 
Rohan D. Kekatpure
Ph.D. Candidate (Electrical Engg)
Geballe Laboratory of Advanced Materials
Stanford University, Stanford, CA 94305
Work: (650)723-4874
Cell: (650)387-7968





From rcrane at stanford.edu  Fri Nov  3 08:29:28 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Fri, 03 Nov 2006 08:29:28 -0800
Subject: [Fwd: CISX Solvent Fan Shutdown]
Message-ID: <454B6E68.3040808@stanford.edu>

All, a quick clarification:

The CISX solvent exhaust shut down does not affect the SNF fab area. SNF 
is open for normal operation at this time.

Thanks,

Dick

-------- Original Message --------
Subject: 	CISX Solvent Fan Shutdown
Date: 	Fri, 03 Nov 2006 07:37:36 -0800
From: 	Leonard Chan <leonardc at bonair.stanford.edu>
To: 	cis-building at cis.stanford.edu



CISX Lab User,

We are shutting down the CISX solvent fan this morning for repair. We have 
to dismantle the fan to find out the problem, so
we don't know how long it is going to be down. Please refrain from using 
any solvent while we are doing the repair. We will
keep you updated on the development of the repair.

Sorry for the inconvenience, thank you for your patience.

Thanks,

Leonard


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From rcrane at stanford.edu  Fri Nov  3 13:35:47 2006
From: rcrane at stanford.edu (Dick Crane)
Date: Fri, 03 Nov 2006 13:35:47 -0800
Subject: Building alarm, 11/2
Message-ID: <454BB633.8030701@stanford.edu>

All,

On Thursday, November 2, at 0814, the CIS and CISX buildings were 
evacuated due to a building wide alarm. A toxic gas sensor in a CISX lab 
failed in an alarm mode and triggered the evacuation. The lab was 
checked, found to be gas free, and the fire department reset the 
building alarms. The buildings were reopened by 0840.

Sorry for the inconvenience,

Dick



From mtang at stanford.edu  Mon Nov  6 06:52:36 2006
From: mtang at stanford.edu (Mary Tang)
Date: Mon, 06 Nov 2006 06:52:36 -0800
Subject: Annual Lab Shutdown/Startup
Message-ID: <454F4C34.1070100@stanford.edu>

Labmembers --

The annual lab shutdown schedule has been finalized and is as follows:

Monday, December 18 at 7 am:  All processing must stop in the lab.  
Staff begins equipment shutdown.
Wednesday, January 3 at 7 am:  Labmembers are welcome back into the lab.

Please note the following:

1.  For safety reasons, NO labmembers are allowed in the lab for any 
reason during shutdown from Dec. 18 through 7 am Jan.  As work will be 
done on the Facilities in the lab, some safety measures (such as 
exhaust) may not be fully operational at all times. 

2.  Be aware that all personal materials (wafers, wafer boxes, WIP, 
labware) that are outside of personal storage bins will be removed from 
the lab during the shutdown.  Please make sure to remove your materials 
or place them inside your personal bin before then.

3.  There will be specific equipment which will be shutdown before Dec. 
18 or kept shutdown after Jan. 3.  Stay tuned for announcements and 
check Coral for planned shutdowns.



Your SNF staff

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From patlu at Stanford.EDU  Mon Nov  6 12:56:49 2006
From: patlu at Stanford.EDU (Patrick Lu)
Date: Mon, 6 Nov 2006 12:56:49 -0800
Subject: is there an alcohol-soluble spin-on layer?
Message-ID: <5ef4413c0611061256p6ce35b7cm6ea3f796b660cb4e@mail.gmail.com>

Hello everybody,

I have features in ebeam resist that I want to keep clean during a wafersaw
dicing process. With other types of structures, I could use a layer of
photoresist as a barrier during dicing and strip it off afterwards, but
there isn't a way that I know of to strip only photoresist while leaving my
ebeam resist unscathed. So...anyone know of another spin-on layer I can use?
Something that won't wash off in water as the wafersaw sprays it rather
copiously? I thought a coating that I could later remove with isopropanol
might work.

thanks for any info!
Patrick
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From jimkruger at yahoo.com  Mon Nov  6 19:03:05 2006
From: jimkruger at yahoo.com (jim kruger)
Date: Mon, 6 Nov 2006 19:03:05 -0800 (PST)
Subject: is there an alcohol-soluble spin-on layer?
In-Reply-To: <5ef4413c0611061256p6ce35b7cm6ea3f796b660cb4e@mail.gmail.com>
Message-ID: <20061107030305.43082.qmail@web38906.mail.mud.yahoo.com>

PMMA developer (MIBK:IPA  1:3) can be used to strip
photoresist while leaving PMMA.  It does ammount to an
extra development and there seems to be a "mixed
layer" so the PMMA measures thicker than before.  I
have been sawing PMMA parts this way for some time. 
It is critcal to have the parts very dry (I do a ~ 100
C bake in the Mahnaz oven after saw but before the
"developer-strip". I do a light plams descum after.
 I am happy to talk with you.

jimkruger

--- Patrick Lu <patlu at Stanford.EDU> wrote:

> Hello everybody,
> 
> I have features in ebeam resist that I want to keep
> clean during a wafersaw
> dicing process. With other types of structures, I
> could use a layer of
> photoresist as a barrier during dicing and strip it
> off afterwards, but
> there isn't a way that I know of to strip only
> photoresist while leaving my
> ebeam resist unscathed. So...anyone know of another
> spin-on layer I can use?
> Something that won't wash off in water as the
> wafersaw sprays it rather
> copiously? I thought a coating that I could later
> remove with isopropanol
> might work.
> 
> thanks for any info!
> Patrick
> 




 
____________________________________________________________________________________
Do you Yahoo!?
Everyone is raving about the all-new Yahoo! Mail.
http://new.mail.yahoo.com


From jwc at snf.stanford.edu  Tue Nov  7 09:31:10 2006
From: jwc at snf.stanford.edu (James Conway)
Date: Tue, 07 Nov 2006 09:31:10 -0800
Subject: SPECIAL EBEAM LAB EVENT:"'3D EBL applications for UV Nano Imprint
 Lithography"  Guido  Piaszenski, Raith GmbH, Dortmund, DE. MONDAY NOV. 13
 from 2 - 3 PM in CIS 101
Message-ID: <4550C2DE.7050608@snf.stanford.edu>

*ANNOUNCEMENT OF A SPECIAL EBEAM LAB EVENT*

*Monday November 13, 2006 2 - 3 PM CIS 101:*

*"3D EBL Applications for UV Nano Imprint Lithography." *

Guido Piaszenski from Raith GmbH in Dortmund, Germany has graciously 
offered to visit the Stanford Nanofabrication Facility and present his 
group's work which he will also be presenting at the NNT2006 conference 
in San Francisco later that week.

He received his PhD in 2002 at the Ruhr-University of Bochum, Germany 
working with Professor U.K. K?hler.
In 2003 he started working in the application department at Raith GmbH 
in Dortmund Germany developing, testing, and supporting Users working on 
the Raith Electron Beam Lithography Software applications.

This meeting is open to Everyone whom wishes to attend:

    2 - 3 PM     CIS 101:     Presentation followed by Q&A from attendees.
    3 - 4:30 PM CIS 201:     Technical Discussion on NIL and Ebeam 
Lithography topics.

Abstract:

Please feel free to forward this email to people of interest within the 
Stanford Community.

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From caleb3 at stanford.edu  Tue Nov  7 09:31:11 2006
From: caleb3 at stanford.edu (Caleb B. Bell III)
Date: Tue, 7 Nov 2006 09:31:11 -0800
Subject: Seminar: Prof.DeGrado - De Novo Design of Metalloproteins and Membrane Proteins
References: <03d801c6f6ef$129d8e90$0100000a@galvani>
Message-ID: <008801c70292$84984180$de7d40ab@cid>

Stanford University Chemistry Department 
Student Hosted Colloquium

"De Novo Design of Metalloproteins and Membrane Proteins"
William DeGrado, 
George W. Raiziss Professor of Biochemistry and Biophysics 
Univeristy of Pennsylvania

4:15PM Thursday, November 9th, 2006 
Braun Auditorium (Mudd Chemistry Building)
About DeGrado: 
William DeGrado received his Ph.D. in Chemistry from the University of Chicago in 1981 and now holds the position of Professor of Biochemistry and Biophysics at the University of Pennsylvania. His research group focused on protein design as an approach to understanding macromolecule structure and function. Thus their primary research interest is in the de novo design of proteins, in which one attempts to design proteins from first principals. This approach critically tests his understanding of protein folding and function, while also laying the groundwork for the design of proteins with properties not precedented in nature. Before his academic appointment, DeGrado spent 14 years with DuPont, eventually serving as Senior Director of Medicinal Chemistry. DeGrado has authored over 250 publications in various journals, holds 5 US patents, sits on a variety of editorial boards and has received numerous awards. These include; Du Vigneaud Award for Young Investigators in Peptide Research, Protein Society Young Investigator Award, Eli Lilly Award in Biological Chemistry, DuPont Merck Summit Award, Fellow, American Association for the Advancement of Science, Member of the National Academy of Sciences and the Merrifield Award, Peptide Society. 

Questions
Please contact Patricia Dwyer at 650-723-4770. 
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From edmyers at stanford.edu  Tue Nov  7 15:23:56 2006
From: edmyers at stanford.edu (Ed Myers)
Date: Tue, 07 Nov 2006 15:23:56 -0800
Subject: Spectral Ellipsometer Arrival Plans
Message-ID: <6.2.5.6.2.20061107145824.0480f6d0@stanford.edu>

All,

I received confirmation SNF's new spectral 
ellipsometer is close to shipping.  JA Woollam 
will be here on Thursday and Friday Nov. 16th and 
17th to do the installation and training.

The training will be structured in the following way:

Thursday Nov. 16th, 1:30-3:30 an open 
presentation on how to make measurements using 
the M2000.  I have asked the presentation not 
cover the fundamentals of ellipsometry.  I will 
announce the conference room once I have it 
booked.  The presentation is open to all.

On Friday we will focus on establishing a group 
of power users and training the SNF staff.  This 
will be more individual or very small group 
training.  I am hoping we can identify one user 
per research group for this training.  It will be 
someone who has a vested interest in making 
measurements, who can interface with their group 
members, help establish measurement routines and 
is not planning on making a measurement, grabbing their diploma and leaving.

If you are interested in supporting your groups 
measurements or becoming a skilled user, please 
send me an email.  Include your advisor's group 
and the type of measurements you 
need.  Hopefully, we will have time to analyze 
one of your samples during the training.  Please 
reserve Friday for the training.  Training will 
not take all day, but I don't have a firm schedule for Friday.

The tool has a lot of capability, but it should 
also provide a "one click" approach for measurements of routine films.

General information on the JA Woollam M2000 system SNF purchased:

M-2000 Automated Angle
Wavelength package X (480 wavelengths from 210 nm to 1000 nm)
M-2000 Systems Feature
? Advanced Rotating Compensator (RCE) design.
? Auto angle from 40? to 90?, featuring horizontal sample stage.
? Collimated Light beam (diameter varies with model: 2-5 mm).
? 3 copies of WVASE32? software for data acquisition/analysis.
? Operator Computer: Pentium-4, 512Mb RAM, 80Gb hard drive,
CD-RW or better, 17? FPD monitor and Windows XP Pro.
System Table/Cabinet- Customized table to mount ellipsometer
system, control boxes, computer & flat panel display monitor(s).
Automated Sample Translation Upgrade -200mm XY Mapping
Focusing Upgrade -Focused beam diameter depends on the M-2000 Model:
o X wavelengths: 150 um over all 
wavelengths.  (*Focusing optics detach for 
measurement with standard spot size.*)
VASEManager Software- Automates the routine data acquisition
and analysis procedures.






From shott at stanford.edu  Tue Nov  7 17:40:08 2006
From: shott at stanford.edu (John Shott)
Date: Tue, 07 Nov 2006 17:40:08 -0800
Subject: Minor water leak in litho aisle ...
Message-ID: <45513578.9030207@stanford.edu>

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From barlian at stanford.edu  Tue Nov  7 20:25:48 2006
From: barlian at stanford.edu (A. Alvin Barlian)
Date: Tue, 7 Nov 2006 20:25:48 -0800 (PST)
Subject: Polytec Demo
Message-ID: <Pine.GSO.4.44.0611072022430.21152-100000@elaine15.Stanford.EDU>


if you're interested in MEMS characterization techniques:



	Presentation Day at Stanford University


	Polytec presents its latest technology for dynamic and static
characterization of MEMS.    Please join us for a one-hour technical
seminar on campus at Stanford University to learn about the new
advances in our measurement technology.  To exemplify the use of this
technology, Polytec presents characterization measurements on a
variety MEMS structures including actuators, optical mirrors, inertial
sensors, accelerometers, switches and magnetometers.

	Presenting our Latest Micro System Analyzer
	Measurement Technology for
	Microstructure Dynamics and Topography:
	Micro System Analyzer

	When:  Wednesday, Nov.  8th from 4:00 - 5:00 PM
	Where : MERL (Mechanical Engineering Research Laboratory)
Conference Room (on the 2nd floor).

	I look forward to meeting with you and discussing any
measurement applications you may have.

Thanks





From lwchang at stanford.edu  Wed Nov  8 15:25:13 2006
From: lwchang at stanford.edu (Li-Wen Chang)
Date: Wed, 8 Nov 2006 15:25:13 -0800
Subject: innotec free this Thur(11/9) 5-8:30pm
Message-ID: <20061108232517.0BD334CCE2@smtp1.stanford.edu>






From makarova at stanford.edu  Wed Nov  8 17:16:21 2006
From: makarova at stanford.edu (Maria Makarova)
Date: Wed, 8 Nov 2006 17:16:21 -0800
Subject: GaP processing experience?
Message-ID: <9101E522-E379-47F2-A40A-FF40CCC8DE00@stanford.edu>

Hello everybody,

We are looking into using Gallium Phosphide for some photonic crystal  
devices.
Does anyone have any processing experience with it?
We need to know how difficult it is to etch.  Can you share any dry  
or wet etching recipes?

Any advice will be appreciated.

Thank you,


Maria Makarova
Edward L. Ginzton Laboratory
Stanford University
(650) 723-2279




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From jwc at snf.stanford.edu  Fri Nov 10 08:32:44 2006
From: jwc at snf.stanford.edu (James Conway)
Date: Fri, 10 Nov 2006 08:32:44 -0800
Subject: REMINDER MONDAY NOV. 13 from 2 - 3 PM in CIS 101:  EBEAM LAB EVENT:"'3D
 EBL applications for UV Nano Imprint Lithography"  Guido  Piaszenski, Raith
 GmbH, Dortmund, DE. 
Message-ID: <4554A9AC.4090308@snf.stanford.edu>

*ANNOUNCEMENT OF A SPECIAL EBEAM LAB EVENT*

*Monday November 13, 2006 2 - 3 PM CIS 101:*

*"3D EBL Applications for UV Nano Imprint Lithography." *

Guido Piaszenski from Raith GmbH in Dortmund, Germany has graciously 
offered to visit the Stanford Nanofabrication Facility and present his 
group's work which he will also be presenting at the NNT2006 conference 
in San Francisco later that week.

He received his PhD in 2002 at the Ruhr-University of Bochum, Germany 
working with Professor U.K. K?hler.
In 2003 he started working in the application department at Raith GmbH 
in Dortmund Germany developing, testing, and supporting Users working on 
the Raith Electron Beam Lithography Software applications.

This meeting is open to Everyone whom wishes to attend:

    2 - 3 PM     CIS 101:     Presentation followed by Q&A from attendees.
    3 - 4:30 PM CIS 201:     Technical Discussion on NIL and Ebeam 
Lithography topics.

Abstract:

Please feel free to forward this email to people of interest within the 
Stanford Community.

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From shwong at gmail.com  Fri Nov 10 11:52:17 2006
From: shwong at gmail.com (Serena Wong)
Date: Fri, 10 Nov 2006 11:52:17 -0800
Subject: cleaning small pieces
Message-ID: <2e2208d70611101152o5dcaf22flaf5c088d189878b7@mail.gmail.com>

Hi,

I need one of those small baskets for holding small pieces (6 by 15 mm
pieces) for cleaning at wbmetal.  Does anyone know where i can purchase such
a basket?  Also, does anyone have one I can borrow on Monday?

Thanks so much!
Serena
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From rostam at stanford.edu  Fri Nov 10 15:38:44 2006
From: rostam at stanford.edu (Rostam Dinyari)
Date: Fri, 10 Nov 2006 15:38:44 -0800
Subject: SU-8 photoresist
Message-ID: <1163201924.45550d8455b23@webmail.stanford.edu>

Hi,

I was wondering if anyone can spare about 100 mL of SU-8 or any other thick
photoresist?

Thanks,
Rostam




From edmyers at stanford.edu  Mon Nov 13 14:53:55 2006
From: edmyers at stanford.edu (Ed Myers)
Date: Mon, 13 Nov 2006 14:53:55 -0800
Subject: Nitrile Gloves, Nov. 15th
Message-ID: <6.2.5.6.2.20061113144643.026cbbb0@stanford.edu>

All,

This Wednesday, Nov. 15th from 1-3 pm Kimberly-Clark will be at the 
fab entrance to demonstrate and pass out their Nitrile Gloves.  You 
will be able to wear these gloves into the clean room for 
evaluation.  Rumor has it there might even be something to eat.


Please stop by ask questions about the Nitrile Class 100 clean room
gloves manufactured by Kimberly-Clark that will you will be wearing and
testing.    Subjects to be covered:

- Sizing and characteristics of the Nitrile gloves.
- Differences between Latex and Nitrile
- Fit & Feel, Chemical resistance, etc.
- Double donning (double gloving)

Regards,

Glenn Witkoski
Scientific & Technical Sales
Kimberly - Clark Professional
Cell: (415) 516-9370
Fax:  (415) 341-0085
Customer Service: (800) 255-6401
www.kc-safety.com
www.kcprofessional.com




From mbaran at stanford.edu  Tue Nov 14 09:10:03 2006
From: mbaran at stanford.edu (Maureen Baran)
Date: Tue, 14 Nov 2006 09:10:03 -0800
Subject: SanDisk found in the Lab
Message-ID: <20061114171004.CE0584CDB1@smtp2.stanford.edu>

Good Morning Labmembers,

 

If this SanDisk is your, please come by and claim it.

 

Maureen

 

Maureen Baran

Stanford Nanofabrication Facility

Lab Services Administrator

mbaran at stanford.edu

650-725-3664

 

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From edmyers at stanford.edu  Tue Nov 14 16:31:00 2006
From: edmyers at stanford.edu (Ed Myers)
Date: Tue, 14 Nov 2006 16:31:00 -0800
Subject: Spectral Ellipsometer Presentation
Message-ID: <6.2.5.6.2.20061114162757.03e9e490@stanford.edu>

All,

I have reserved the auditorium, CISX-101 for the 
JA Woollam presentation on our new M2000 spectral 
ellipsometer.  The talk will begin at 1:30pm on 
Thursday, Nov. 16th.  This is an open invitation 
to all users who are interested in the system.

Regards,
Ed


>To: labmembers at snf.stanford.edu
>From: Ed Myers <edmyers at stanford.edu>
>Subject: Spectral Ellipsometer Arrival Plans
>
>All,
>
>I received confirmation SNF's new spectral 
>ellipsometer is close to shipping.  JA Woollam 
>will be here on Thursday and Friday Nov. 16th 
>and 17th to do the installation and training.
>
>The training will be structured in the following way:
>
>Thursday Nov. 16th, 1:30-3:30 an open 
>presentation on how to make measurements using 
>the M2000.  I have asked the presentation not 
>cover the fundamentals of ellipsometry.  I will 
>announce the conference room once I have it 
>booked.  The presentation is open to all.
>
>On Friday we will focus on establishing a group 
>of power users and training the SNF staff.  This 
>will be more individual or very small group 
>training.  I am hoping we can identify one user 
>per research group for this training.  It will 
>be someone who has a vested interest in making 
>measurements, who can interface with their group 
>members, help establish measurement routines and 
>is not planning on making a measurement, grabbing their diploma and leaving.
>
>If you are interested in supporting your groups 
>measurements or becoming a skilled user, please 
>send me an email.  Include your advisor's group 
>and the type of measurements you 
>need.  Hopefully, we will have time to analyze 
>one of your samples during the training.  Please 
>reserve Friday for the training.  Training will 
>not take all day, but I don't have a firm schedule for Friday.
>
>The tool has a lot of capability, but it should 
>also provide a "one click" approach for measurements of routine films.
>
>General information on the JA Woollam M2000 system SNF purchased:
>
>M-2000 Automated Angle
>Wavelength package X (480 wavelengths from 210 nm to 1000 nm)
>M-2000 Systems Feature
>? Advanced Rotating Compensator (RCE) design.
>? Auto angle from 40? to 90?, featuring horizontal sample stage.
>? Collimated Light beam (diameter varies with model: 2-5 mm).
>? 3 copies of WVASE32? software for data acquisition/analysis.
>? Operator Computer: Pentium-4, 512Mb RAM, 80Gb hard drive,
>CD-RW or better, 17? FPD monitor and Windows XP Pro.
>System Table/Cabinet- Customized table to mount ellipsometer
>system, control boxes, computer & flat panel display monitor(s).
>Automated Sample Translation Upgrade -200mm XY Mapping
>Focusing Upgrade -Focused beam diameter depends on the M-2000 Model:
>o X wavelengths: 150 um over all 
>wavelengths.  (*Focusing optics detach for 
>measurement with standard spot size.*)
>VASEManager Software- Automates the routine data acquisition
>and analysis procedures.
>
>
>





From edmyers at stanford.edu  Wed Nov 15 10:58:20 2006
From: edmyers at stanford.edu (Ed Myers)
Date: Wed, 15 Nov 2006 10:58:20 -0800
Subject: Litho Area Activities Starting Sunday
Message-ID: <6.2.5.6.2.20061115104556.03b5be78@stanford.edu>

All,

Many of you have heard the rumors about the 6" litho equipment.  Some 
of this becomes reality starting this Sunday, Nov. 19th and running 
through Tuesday, Nov. 21st.  Beginning on Sunday there will be a team 
of engineers in the fab prepping the Nikon Body9 and DNS resist track 
for removal.  The big move will be on Tuesday, Nov. 21st.

On Tuesday morning a construction crew will come in to wall off the 
area and enlarge the door opening near the YES oven.  The plan is to 
have the equipment rolled out and the wall repaired by the end of the 
day on Tuesday.

The disruptions in the Litho area will include increased activity in 
the area and the shutdown of the YES oven either late Monday or early 
Tuesday.  The YES HMDS oven will not be available until 
Wednesday.  The personnel storage bins will be relocated, somewhere close by.

With the increased activity, please try and avoid the corner of the 
fab where the DNS, Nikon Body9 are located during the Sunday to 
Tuesday time period.  This will include planning your wafer 
processing accordingly.





From raghavs at stanford.edu  Wed Nov 15 12:53:55 2006
From: raghavs at stanford.edu (Raghav Sreenivasan)
Date: Wed, 15 Nov 2006 12:53:55 -0800
Subject: Ph.D. Dissertation Defense (Nov 20th) -- Raghav Sreenivasan
Message-ID: <6.2.5.6.2.20061115124720.03a4ac50@stanford.edu>


"Metal-gate/High-k Dielectric Stack Engineering 
by Atomic Layer Deposition : Materials Issues and Electrical Properties"

Raghavasimhan Sreenivasan
Department of Materials Science and Engineering

Advisor : Professor Paul McIntyre
Co-Advisor : Professor Krishna Saraswat

Date :    Monday, November 20th, 2006
Time :    2PM (Refreshments served at 1:45 PM)
Place :   CISX 101 (Auditorium)


Abstract

Scaling of silicon devices has resulted in a gate 
oxide that is only a few monolayers thick. This 
has led to an increase in the standby power of 
devices due to direct tunneling through the 
dielectric. Replacing the thin SiO2 gate 
dielectric with a thicker film having a higher 
dielectric constant can reduce the off-state 
leakage current without compromising the device 
performance. Hafnium based oxides and silicates 
have been identified as potential high-k 
candidates due to their thermodynamic stability 
and compatibility with silicon processing. The 
introduction of high-k dielectrics necessitates 
the replacement of poly-Si gates with metal gate 
electrodes. Poly-Si electrodes have been shown to 
be incompatible with HfO2 films, apparently 
because of the formation of defects in the 
dielectric layer or its interface with the 
electrode under typical poly-Si growth conditions.

In this study, we have evaluated HfO2 as the gate 
dielectric material and TaN as the metal gate 
electrode deposited using the Atomic Layer 
Deposition (ALD) technique. ALD provides us with 
the unique capability of growing high quality 
thin films with excellent control over the film 
thickness, stoichiometry and conformality. 
Nanoscale HfO2 films were deposited by ALD on Si 
substrates using two different precursor 
chemistries ? HfCl4 and 
Tetrakis(Diethylamido)Hafnium (TDEAH) with H2O as 
the oxidant. A systematic study of the physical 
and electrical properties of the HfO2 films 
derived using the two different chemistries 
revealed a positive fixed charge for the 
amide-HfO2 whereas a negative fixed charge was 
estimated for the chloride-HfO2. Further analysis 
of the chloride-HfO2 showed that preferential 
segregation of Cl to the HfO2 /SiO2 interface 
significantly altered both the magnitude and sign 
of the fixed charge in the gate stack.

Tantalum nitride thin films were deposited at 
425?C by a remote plasma-enhanced ALD (PEALD) 
method using a novel metal organic precursor ? 
isopropylimino tris(ethylmethylamino) tantalum 
(IPTEMT). An Ar/N2/H2 mixture was flowed through 
a remote plasma system to generate NH* and H* 
free radicals needed for the nitridation process 
as observed by optical emission spectroscopy 
(OES) measurements. High resolution XPS studies 
of the as-deposited film revealed it to be the 
dielectric Ta3N5 phase. High temperature in-situ 
anneals performed in the TEM column crystallized 
the ALD tantalum nitride film at 850?C into the 
stoichiometric cubic TaN phase. The phase 
transformation from dielectric Ta3N5 to metallic 
TaN is achieved by out-diffusion of excess 
nitrogen atoms from the Ta3N5 film during the 
high temperature anneal. The resistivity of the 
annealed TaN films was estimated to be
650? ohm-cm by four point probe measurements. TaN 
was evaluated as a potential gate electrode 
material both on SiO2 and HfO2 gate dielectrics. 
The impact of high temperature anneals on the 
mobility of hydroxyl and oxygen impurities in the 
stack and its effect on the thickness of the 
interfacial layer will be discussed. A novel low 
temperature process was identified to engineer 
the TaN/HfO2 gate stack using a reactive titanium metal overlayer.



From mbaran at stanford.edu  Wed Nov 15 13:58:20 2006
From: mbaran at stanford.edu (Maureen Baran)
Date: Wed, 15 Nov 2006 13:58:20 -0800
Subject: Flash Memory Stick Found Near SNF
Message-ID: <20061115215820.EEA494CFB1@smtp1.stanford.edu>

A flash memory stick has just been turned in to me.  If this is yours,
please come by and claim it.

 

I'm in cubicle 41, which is closest to the doors facing the Applied Physics
building.

 

Thank you,

 

Maureen

 

Maureen Baran

Stanford Nanofabrication Facility

Lab Services Administrator

mbaran at stanford.edu

650-725-3664

 

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From saraswat at cis.stanford.edu  Wed Nov 15 15:11:49 2006
From: saraswat at cis.stanford.edu (Krishna Saraswat)
Date: Wed, 15 Nov 2006 15:11:49 -0800
Subject: Special seminar on NBTI in p-MOSFETs
Message-ID: <4885BAA8-E8EA-4AFD-8F48-8DC00E02DD32@cis.stanford.edu>

Title: Electrical Characterization and Modeling of NBTI in p-MOSFET  
Devices

Time: Thursday, November 16, 4:00pm
Place: CIS 101

Speaker: Prof. Souvik Mahapatra
Department of Electrical Engineering, Indian Institute of Technology  
Bombay, Mumbai, India
(presently - Visiting Faculty Fellow, Applied Materials, Santa Clara,  
CA)


Abstract:

Negative Bias Temperature Instability (NBTI) is a serious reliability  
concern for p-MOSFETs having ultrathin silicon oxynitride gate  
dielectrics. This talk will focus on electrical characterization and  
modeling of defects created during NBTI stress. After a brief  
introduction, proper choice of stress bias will be discussed such  
that unwanted bulk-trap generation is avoided during accelerated  
stress testing. Various types of interface defects will be discussed  
and the one associated with NBTI will be identified. The importance  
of measurement delay and its severe impact on NBTI time evolution  
will be specially highlighted. NBTI generation and recovery results  
obtained using a delay-free measurement respectively during stress  
and post-stress will be presented for a wide range of samples, ie.  
different EOT, nitridation type, and dose. It will be shown that NBTI  
generation and recovery in properly optimized films can be fully  
explained using the well-known Reaction-Diffusion model for interface- 
traps. The impact of NBTI recovery on DC versus AC lifetimes will  
also be discussed.


Biography:

Souvik Mahapatra received his PhD in Electrical Engineering from the  
Indian Institute of Technology, Bombay (IITB), India in 1999. From  
2000 to 2001 he was at Bell Laboratories, Lucent Technologies, in  
Murray Hill, NJ, USA. Since 2002 he is with the Department of  
Electrical Engineering, IITB, where he is presently an Associate  
Professor. In 2006, he is a Visiting Fellow at Applied Materials in  
Santa Clara, CA. His research interests are electrical  
characterization of defects in dielectric-semiconductor interfaces,  
hot-carrier and bias temperature instability in CMOS devices, high-k  
and novel dielectrics for CMOS, and Flash EEPROMs. He has published  
more than 60 papers in refereed international journals and  
conferences, was invited to speak at several major international  
conferences including the IEEE IEDM, was a tutorial speaker at the  
IEEE IRPS, and has worked as a reviewer for many international  
journals and conferences.



From mtang at stanford.edu  Wed Nov 15 15:18:34 2006
From: mtang at stanford.edu (Mary Tang)
Date: Wed, 15 Nov 2006 15:18:34 -0800
Subject: Annual Cleanup!!
Message-ID: <455BA04A.9080304@stanford.edu>

Greetings labmembers!

As we approach the holidays, it?s time to think about beginning the new 
year with a fresh start....

Please take time to check the following:

   1. The CAD room.
         1. All personal items should be stored inside plastic bins, on
            the metal shelves, or in designated rollaround carts.
         2. All plastic bins and rollaround should be labeled with your
            Coral login and the current date.
   2. In the lab.
         1. All personal items should be stored inside personal lab bins.
         2. Personal lab bins should be labeled with your Coral login.
         3. In preparation for the annual lab shutdown, remove materials
            that you are not currently working on from the WIP racks.

Please note that starting on Monday, December 11, we?ll begin cleanup of 
the CAD room: any items that are not stored in labeled, personal storage 
bins will be removed and reclaimed. This includes wafer boxes, plastic 
bags, and cardboard boxes with items. No items may be stored on the floor.

Starting Monday, December 18, we?ll be cleaning up the lab. Any personal 
items not stored in labeled, personal storage bins will be removed. This 
includes materials on WIP shelves.

Please do take a moment to walk around the CAD room and the lab and 
check for your belongings!

Thanks!

Your SNF Staff

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From jqguo at stanford.edu  Wed Nov 15 16:05:06 2006
From: jqguo at stanford.edu (Jiquan Guo)
Date: Wed, 15 Nov 2006 16:05:06 -0800
Subject: Drilling holes on silicon wafer
In-Reply-To: <5ef4413c0611061256p6ce35b7cm6ea3f796b660cb4e@mail.gmail.com>
Message-ID: <000c01c70912$df9a4840$a4884f86@win.slac.stanford.edu>

Hello, everyone:

I'm going to make a 1-3mm diameter hole in the center of a silicon
wafer(with or without oxide on top). Are there any companies around doing
it, mechanically or with laser? 

Thanks a lot.

Jiquan



From mahnaz at stanford.edu  Thu Nov 16 14:08:25 2006
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Thu, 16 Nov 2006 14:08:25 -0800
Subject: Evacuation
Message-ID: <455CE159.5040006@stanford.edu>


Hello all,

There has been a little spill ( HMDS)  in the litho area,  Litho will be 
open around 2:40.

mahnaz


From mahnaz at stanford.edu  Fri Nov 17 09:43:02 2006
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Fri, 17 Nov 2006 09:43:02 -0800
Subject: YES OVEN
Message-ID: <455DF4A6.2080308@stanford.edu>


Hello all,

As you know,  there will be a little disturbance in the litho area next 
Tuesday especially where  the YES oven is. The use of YES oven will be 
limited on that day.
I will ask Uli and see to it to see if we have an extra yes cassette so 
you can use the YES oven all the way up to Tuesday morning.
Remember when the wafers goes to YES oven is good for up to 4 days, 
meaning that the wafers can go through spin later.
 We will bring the yes oven up as soon as we can.
Yes oven can handle about 6 cassettes at the time so share the ride with 
each other.

mahnaz



From mtang at stanford.edu  Fri Nov 17 15:25:38 2006
From: mtang at stanford.edu (Mary Tang)
Date: Fri, 17 Nov 2006 15:25:38 -0800
Subject: Work in litho:  Sunday, Nov. 19
Message-ID: <455E44F2.4040202@stanford.edu>

Greetings labmembers --

We would like you to be aware of some unusual activity in the lab in the 
coming week.  Several engineers from Apex Engineering will be working in 
the litho area Sunday morning, Nov. 19, from about 9 to noon.  They will 
be decommissioning the DNS and Nikon B9 systems which will then be 
removed from the lab.  Depending on what they are doing, we may require 
labmembers to leave the litho area during some or all of this time.  
Please honor their requests to leave, if asked.  Jim Haydon and a couple 
other staff members will be on hand or nearby during this time.

Please stay tuned for updates on their replacements!

Your SNF Staff

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From mtang at stanford.edu  Fri Nov 17 17:00:01 2006
From: mtang at stanford.edu (Mary Tang)
Date: Fri, 17 Nov 2006 17:00:01 -0800
Subject: Unknown Chemical?!??
Message-ID: <455E5B11.4030801@stanford.edu>

Labmembers --

There's a waste bottle on top of the Flammables cabinet in the service 
area of the lab.  It clearly contains waste chemical, but there is no 
hazardous waste tag.  Whoever left this, please do the responsible thing 
and label it with the appropriate waste tag so that we can dispose of it 
properly.  And don't do this again.

Mary

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu




From rissman at stanford.edu  Mon Nov 20 08:22:43 2006
From: rissman at stanford.edu (Paul Rissman)
Date: Mon, 20 Nov 2006 08:22:43 -0800
Subject: equipment performance improvement teams
Message-ID: <7.0.1.0.2.20061120081558.035b8fe0@stanford.edu>

Labmembers:

Equipment uptime and process performance is the lifeblood of 
SNF.  Simply put, if the equipment isn't working, or isn't performing 
to expected specifications, the users of the lab cannot do effective 
experiments.  As a consequence, the student and faculty research 
suffers and the industrial users cannot make progress on their 
product development.

As you probably know, over the past few months the availability for a 
number of key pieces of equipment has been poor.  In some cases, this 
has been the result of old equipment which is difficult to maintain, 
but in other cases, SNF has not had the resources to keep the 
equipment performing to specification.  In some specific cases, we 
have not set specifications for the equipment.

Over the past few weeks, with Professor Nishi's encouragement, SNF 
management has launched several initiatives to improve key equipment 
performance in the lab.  In particular, the program we are announcing 
today are teams of one or two each of labmembers, equipment and 
process representatives for each of several critical tools.  These 
teams will meet with the goal of improving communication by pooling 
the knowledge of the different groups.  The  first set of equipment 
teams will focus on stsetch, tylan2, tylannitride, ASM epi, svgcoat, 
Nikon body4, AG4108, and the Micronics maskmaking system.   At 
present, we are still looking for a few more volunteers from students 
and industrial users of the lab, and we will be publishing the full 
list of team members shortly.  The teams will begin meeting over the 
next few weeks.

These groups we will focus on (as appropriate for the particular equipment):

1. Performance trend chart or charts of a key critical process or processes.
2. Expected performance specifications.  Guidelines for when a tool 
is down due to lack of process performance.
3. Uptime of the equipment.  Chronic issues which need to be addressed.
4. Uptime improvement plans.
5. Preventive maintenance schedules and checklists.
6. Post maintenance (scheduled/unscheduled) qualification.
7. Troubleshooting guides and problem paretos.
8. Labmember communication of tool status.
9. Process improvements if appropriate.
10. Is it time to replace this tool with newer technology?
11. Other items specific to the equipment which the team may deem important.

As we succeed with the first set of tools, we will be pushing this 
methodology on to the next set of equipment.

SNF succeeds when we all pull in the same direction - process, 
maintenance AND labmembers.  With the support and help of all of you, 
we can make this a better, more successful facility.

Paul Rissman



From raghavs at stanford.edu  Mon Nov 20 09:30:57 2006
From: raghavs at stanford.edu (Raghav Sreenivasan)
Date: Mon, 20 Nov 2006 09:30:57 -0800
Subject: Reminder: Ph.D. Dissertation Defense (Today, Nov 20th - 2PM)
  -- Raghav Sreenivasan
Message-ID: <6.2.5.6.2.20061120092706.03298d50@stanford.edu>


"Metal-gate/High-k Dielectric Stack Engineering 
by Atomic Layer Deposition : Materials Issues and Electrical Properties"

Raghavasimhan Sreenivasan
Department of Materials Science and Engineering

Advisor : Professor Paul McIntyre
Co-Advisor : Professor Krishna Saraswat

Date :    Monday, November 20th, 2006
Time :    2PM (Refreshments served at 1:45 PM)
Place :   CISX 101 (Auditorium)


Abstract

Scaling of silicon devices has resulted in a gate 
oxide that is only a few monolayers thick. This 
has led to an increase in the standby power of 
devices due to direct tunneling through the 
dielectric. Replacing the thin SiO2 gate 
dielectric with a thicker film having a higher 
dielectric constant can reduce the off-state 
leakage current without compromising the device 
performance. Hafnium based oxides and silicates 
have been identified as potential high-k 
candidates due to their thermodynamic stability 
and compatibility with silicon processing. The 
introduction of high-k dielectrics necessitates 
the replacement of poly-Si gates with metal gate 
electrodes. Poly-Si electrodes have been shown to 
be incompatible with HfO2 films, apparently 
because of the formation of defects in the 
dielectric layer or its interface with the 
electrode under typical poly-Si growth conditions.

In this study, we have evaluated HfO2 as the gate 
dielectric material and TaN as the metal gate 
electrode deposited using the Atomic Layer 
Deposition (ALD) technique. ALD provides us with 
the unique capability of growing high quality 
thin films with excellent control over the film 
thickness, stoichiometry and conformality. 
Nanoscale HfO2 films were deposited by ALD on Si 
substrates using two different precursor 
chemistries ? HfCl4 and 
Tetrakis(Diethylamido)Hafnium (TDEAH) with H2O as 
the oxidant. A systematic study of the physical 
and electrical properties of the HfO2 films 
derived using the two different chemistries 
revealed a positive fixed charge for the 
amide-HfO2 whereas a negative fixed charge was 
estimated for the chloride-HfO2. Further analysis 
of the chloride-HfO2 showed that preferential 
segregation of Cl to the HfO2 /SiO2 interface 
significantly altered both the magnitude and sign 
of the fixed charge in the gate stack.

Tantalum nitride thin films were deposited at 
425?C by a remote plasma-enhanced ALD (PEALD) 
method using a novel metal organic precursor ? 
isopropylimino tris(ethylmethylamino) tantalum 
(IPTEMT). An Ar/N2/H2 mixture was flowed through 
a remote plasma system to generate NH* and H* 
free radicals needed for the nitridation process 
as observed by optical emission spectroscopy 
(OES) measurements. High resolution XPS studies 
of the as-deposited film revealed it to be the 
dielectric Ta3N5 phase. High temperature in-situ 
anneals performed in the TEM column crystallized 
the ALD tantalum nitride film at 850?C into the 
stoichiometric cubic TaN phase. The phase 
transformation from dielectric Ta3N5 to metallic 
TaN is achieved by out-diffusion of excess 
nitrogen atoms from the Ta3N5 film during the 
high temperature anneal. The resistivity of the 
annealed TaN films was estimated to be
650? ohm-cm by four point probe measurements. TaN 
was evaluated as a potential gate electrode 
material both on SiO2 and HfO2 gate dielectrics. 
The impact of high temperature anneals on the 
mobility of hydroxyl and oxygen impurities in the 
stack and its effect on the thickness of the 
interfacial layer will be discussed. A novel low 
temperature process was identified to engineer 
the TaN/HfO2 gate stack using a reactive titanium metal overlayer.



From atomada at leland.stanford.edu  Tue Nov 21 09:52:15 2006
From: atomada at leland.stanford.edu (Astrid Tomada)
Date: Tue, 21 Nov 2006 09:52:15 -0800
Subject: Found Mask
In-Reply-To: <000c01c70912$df9a4840$a4884f86@win.slac.stanford.edu>
References: <000c01c70912$df9a4840$a4884f86@win.slac.stanford.edu>
Message-ID: <63200360818b1715f7d0b4febba6b81d@leland.stanford.edu>

Dear Labmembers,
my group started some Xmas clean up and we found a mask  from 
Compugraphics labeled: LV sensors, Sep 28th 2005, with UCB authors. 
Through the microscope it shows a ying-yang symbol and  what looks like 
an array of little pcb circuit boards.
If it is yours please let me know and I will give it back to you.

Thank you.

Astrid

_____-----_____-----_____
Astrid Tomada
Stanford University
atomada at stanford.edu
_____-----_____-----_____



From mahnaz at stanford.edu  Tue Nov 21 16:43:45 2006
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Tue, 21 Nov 2006 16:43:45 -0800
Subject: YES oven
Message-ID: <45639D41.1010902@stanford.edu>


Hello all,

Uija , Dick and I vacuumed the  big , empty isle and wiped down all the 
equipments.  Mario programmed the YES oven  before going home. Before 
coming out of the lab, I noticed that the temperature over shot to
170 C.
I think needs time to establish the correct temp.

Mahnaz


From mahnaz at stanford.edu  Wed Nov 22 14:18:53 2006
From: mahnaz at stanford.edu (Mahnaz Mansourpour)
Date: Wed, 22 Nov 2006 14:18:53 -0800
Subject: Litho up
Message-ID: <4564CCCD.5030401@stanford.edu>


Hello all,

I like to let you all know that the litho area is up and running.

There is a tile in  Karlsuss isle with lots of dry resist on it ( almost 
in the middle of the room) , it can not be cleaned so during shut down 
will be replaced.  I am trying very hard to convince Dick that it is a 
good opportunity to change all the tiles on that half of the isle so if 
you feel the same put a good word for me.

Have a safe and happy long weekend.

mahnaz


From mahnaz at snf.stanford.edu  Wed Nov 22 13:48:38 2006
From: mahnaz at snf.stanford.edu (Mahnaz Mansourpour)
Date: Wed, 22 Nov 2006 13:48:38 -0800
Subject: Chemical usage
Message-ID: <4564C5B6.7040909@snf.stanford.edu>


Hello all,

I am sending this email from Dick's  behalf
Please help to conserve chemicals by observing the bath changeout 
schedules.   Before changing the chemicals, make sure there are enough 
chemicals in the passthru.
Dave will  restock the chemicals on Friday or Saturday morning.

Have a safe and  happy long weekend.

Mahnaz



From robinhmb at yahoo.com  Wed Nov 22 23:55:41 2006
From: robinhmb at yahoo.com (Robin King)
Date: Wed, 22 Nov 2006 23:55:41 -0800 (PST)
Subject: Chemical usage- Out of 50:1 HF Wednesday eve
In-Reply-To: <4564C5B6.7040909@snf.stanford.edu>
Message-ID: <987908.37207.qm@web58707.mail.re1.yahoo.com>


The chemical passthrough cabinet has no 50:1 HF as of Wednesday
evening.






--- Mahnaz Mansourpour <mahnaz at snf.stanford.edu> wrote:

> 
> Hello all,
> 
> I am sending this email from Dick's  behalf
> Please help to conserve chemicals by observing the bath changeout 
> schedules.   Before changing the chemicals, make sure there are
> enough 
> chemicals in the passthru.
> Dave will  restock the chemicals on Friday or Saturday morning.
> 
> Have a safe and  happy long weekend.
> 
> Mahnaz
> 
> 



 
____________________________________________________________________________________
Do you Yahoo!?
Everyone is raving about the all-new Yahoo! Mail beta.
http://new.mail.yahoo.com


From shott at stanford.edu  Thu Nov 23 09:27:29 2006
From: shott at stanford.edu (John Shott)
Date: Thu, 23 Nov 2006 09:27:29 -0800
Subject: 50:1 HF outage ...
Message-ID: <4565DA01.6010800@stanford.edu>

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From shott at stanford.edu  Fri Nov 24 08:48:08 2006
From: shott at stanford.edu (John Shott)
Date: Fri, 24 Nov 2006 08:48:08 -0800
Subject: Temporary supply of 50:1 HF dip ...
Message-ID: <45672248.3030000@stanford.edu>

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From altug at stanford.edu  Fri Nov 24 13:52:16 2006
From: altug at stanford.edu (Hatice Altug)
Date: Fri, 24 Nov 2006 13:52:16 -0800
Subject: Hatice Altug's University PhD Dissertation Defense (this Monday)
Message-ID: <JEEGIDNCJLPDAJGEIGFMCEMMDDAA.altug@stanford.edu>

Re: Hatice Altug's University PhD Dissertation Defense


DEPARTMENT OF APPLIED PHYSICS
UNIVERSITY PhD DISSERTATION DEFENSE


Hatice Altug
Research Advisor: Professor Jelena Vuckovic


Physics and Applications of Photonic Crystal Nanocavities


Monday, 27 November 2006 at 4:15 p.m.
(Refreshment will start at 4:00 p.m.)


Applied Physics Building, Room AP200




ABSTRACT
Photonic crystal nanostructures open unprecedented opportunities for
construction of novel photonic devices and integrated nanophotonic systems,
due to their unique capability to manipulate light at sub-wavelength scales.
In this talk, I will present my recent work on photonic crystals and their
applications. I will show ultra-fast photonic crystal nanocavity lasers that
can be modulated at speeds far exceeding today's state of the art
semiconductor lasers. The ultra-fast speeds are due to the use of cavity
quantum electrodynamics effects such as spontaneous emission rate
enhancement. I will then introduce two dimensional coupled photonic crystal
nanocavity arrays and show that they can reduce the group velocity of light
by many orders of magnitude. In addition, I will show the implementation of
these structures in active media composed of multiple quantum wells for low
threshold and high power nano-lasers. These coherently coupled nanocavity
lasers achieve dramatically higher power conversion efficiency with respect
to other nanocavity lasers. Finally, I will present photonic crystal
nanocavity sensors and discuss their integration with microfluidic systems
for sensitive detection.




--
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From altug at stanford.edu  Mon Nov 27 01:37:28 2006
From: altug at stanford.edu (Hatice Altug)
Date: Mon, 27 Nov 2006 01:37:28 -0800
Subject: REMINDER-- PhD Dissertation Defense: Hatice Altug (Today 4pm, AP200)
In-Reply-To: <p0623090bc1890d9aba2e@[171.64.84.39]>
Message-ID: <JEEGIDNCJLPDAJGEIGFMOEOBDDAA.altug@stanford.edu>

Re: Hatice Altug's University PhD Dissertation DefenseDEPARTMENT OF APPLIED
PHYSICS
  UNIVERSITY PhD DISSERTATION DEFENSE

  Hatice Altug
  Research Advisor: Professor Jelena Vuckovic

  Physics and Applications of Photonic Crystal Nanocavities

  Monday, 27 November 2006 at 4:15 p.m.
  (Refreshment will start at 4:00 p.m.)

  Applied Physics Building, Room AP200




  ABSTRACT

  Photonic crystal nanostructures open unprecedented opportunities for
construction of novel photonic devices and integrated nanophotonic systems,
due to their unique capability to manipulate light at sub-wavelength scales.
In this talk, I will present my recent work on photonic crystals and their
applications. I will show ultra-fast photonic crystal nanocavity lasers that
can be modulated at speeds far exceeding today's state of the art
semiconductor lasers. The ultra-fast speeds are due to the use of cavity
quantum electrodynamics effects such as spontaneous emission rate
enhancement. I will then introduce two dimensional coupled photonic crystal
nanocavity arrays and show that they can reduce the group velocity of light
by many orders of magnitude. In addition, I will show the implementation of
these structures in active media composed of multiple quantum wells for low
threshold and high power nano-lasers. These coherently coupled nanocavity
lasers achieve dramatically higher power conversion efficiency with respect
to other nanocavity lasers. Finally, I will present photonic crystal
nanocavity sensors and discuss their integration with microfluidic systems
for sensitive detection.
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From pruitt at stanford.edu  Mon Nov 27 17:03:11 2006
From: pruitt at stanford.edu (Beth Pruitt)
Date: Mon, 27 Nov 2006 17:03:11 -0800
Subject: MEMS seminar friday 11am, 300-300
Message-ID: <p06230969c1913a4c6df4@[192.168.0.108]>

you are invited to a special seminar by Prof. Reza Ghodssi of UMD

this Friday Dec 1 at 11am, room 300-300:

MEMS and Microsystems: Future Tools for Nano Devices
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From hycho at stanford.edu  Wed Nov 29 23:18:18 2006
From: hycho at stanford.edu (Hoyeol Cho)
Date: Wed, 29 Nov 2006 23:18:18 -0800
Subject: Ph.D. Oral Defense Announcement - Dec. 7, 2006 - Hoyeol Cho
Message-ID: <001001c7144f$b8e6e4e0$b36418ac@CISHYCHO>

Performance Comparison between Cu/low-K, Carbon Nanotube, and Optics for
Inter-chip and On-chip Interconnects

 

Ph.D. Candidate: Hoyeol Cho

Advisor: Krishna C. Saraswat

Co-advisor: David A. B. Miller

 

Date: Thursday, Dec. 7, 2006 10:00 am

Location: Packard 101 (Refreshment will be served at 9:45 am)

 

Abstract - For more than 30 years, the performance of silicon integrated
circuits has improved at an astonishing rate. The number of functions per
chip has grown exponentially, dramatically bringing down the cost per
function. However, for the first time the relentless scaling paradigm is
threatened by fundamental limits including excessive power dissipation,
insufficient communication bandwidth and signal latency. Many of these
obstacles stem from the physical limitation of Cu-based electrical wires,
making it imperative to examine alternate interconnect schemes for future
ICs. The two most important novel potential candidates are optical and
carbon nanotube (CNT)-based interconnects. 

Optical interconnect due to its high bandwidth, low signal attenuation and
cross talk, is an ideal candidate to tackle the challenges imposed by
electrical wiring for both off-chip and possibly on-chip application.
Because the modern ICs require an ever-increasing system bandwidth and have
a large power density, a realistic study of performance comparison between
electrical and optical interconnects is of paramount importance. In
addition, such a comparison framework aids in setting clear goals on the
requirements of opto-electronic devices to deliver a superior performance
than their electrical counterparts. For on-chip application, optical
interconnects can potentially reduce latency, provide high-bandwidth at
relatively low power. However, an optical waveguide, has a relatively larger
size (pitch~0.6mm), making it difficult to provide high bandwidth density.
This can be mitigated using wavelength division multiplexing (WDM). CNT
interconnects, on the other hand, have the flexibility of being implemented
in the same size scale as the existing Cu on-chip wires, hence possibly can
provide high bandwidth density. In addition they have the advantage of
having a large electron mean free path, hence low resistance. This can
result in low latency compared to Cu/low-K counterpart. 

In this talk, for on-chip application, we compare CNT and optical
interconnects with Cu interconnects using both commonly used metrics:
latency and power and a compound metric which captures system requirements
more efficiently. The necessity of compound metrics is motivated by the fact
that larger bandwidth and a smaller latency can be obtained using more area
resources. Hence area normalization is necessary. In addition, the total
power budget can also be used to increase the aggregate bandwidth, making
power normalization also imperative. Hence, we use bandwidth
density/latency/power as our compound metric. In the future, because of
multi-core architecture, the designers care about the bandwidth density,
latency and power dissipation of global communication. We extensively
examine the impact of device parameters-modulator and detector capacitances
for optics, materials parameters-mean free path and packing density for
CNTs, and system parameters-global clock frequency and switching activity on
both commonly used and the compound metrics. We find that at 22nm technology
node small detector and modulator capacitances for optical interconnects
(~10fF) yields superior, at least comparable, performance with CNTs
(practical, electron mean free path of 0.9mm) and Cu for greater than 35%
and 20% switching activity, respectively. However, improving mean free path
of CNTs (~2.8mm) increases this crossover switching activity to 80%.  

Finally, for off-chip application, we compare high speed optical and
electrical interconnect using power vs. bandwidth. We find that beyond
critical length, power optimized optical interconnects dissipates lower
power compared to high-speed electrical signaling scheme. Beyond 32nm
technology node with its commensurate bandwidth, optical interconnect
becomes favorable for the distance less than 10cm correspondent to
inter-chip communication. This analysis of the impacts of device/system
parameters on critical length gives system/device designer the evaluation
framework of the performance of the system.

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From shott at stanford.edu  Thu Nov 30 13:36:27 2006
From: shott at stanford.edu (John Shott)
Date: Thu, 30 Nov 2006 13:36:27 -0800
Subject: Stock of 50:1 HF has arrived ....
Message-ID: <456F4EDB.4060301@stanford.edu>

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From junewang at ee.stanford.edu  Thu Nov 30 14:43:17 2006
From: junewang at ee.stanford.edu (junewang)
Date: Thu, 30 Nov 2006 14:43:17 -0800
Subject: Ph.D. Oral Defense Announcement - Dec. 1, 2006 - Michael Mulligan
Message-ID: <456F5E85.8050403@ee.stanford.edu>

Special University Oral Exam

"High Efficiency Gate Drivers for Low-Voltage CMOS DC-DC Converters"

Michael D. Mulligan
Department of Electrical Engineering

Advisor : Professor Thomas Lee

Date :    Friday, December 1st, 2006
Time :    1PM (Refreshments served at 12:45 PM)
Place :   CISX 101 (Auditorium)

Abstract:

The growth of the portable electronics industry has demanded 
improvements in dc-dc converter technology in order to increase battery 
lifetime and enable smaller, less expensive systems. For example, 
brighter, full-color displays and a demand for increased talk-time in 
cellular phones has placed power consumption at a premium. Since many 
portable devices operate in low-power standby modes for a majority of 
the time they are on, increasing light-load converter efficiency can 
significantly increase battery lifetime.  Additionally, better 
light-load efficiency also increases converter power density by enabling 
the use of smaller passive filter components.

In this work, we have developed two gate-drive techniques that can be 
used either alone or in tandem to improve the light-load efficiency of 
switchmode power converters. The first technique exploits the 
second-order overshoot of an underdamped RLC network to store and reuse 
a significant portion of the power MOSFET gate charge. Passive devices 
that are used in the charge recycling network can either be integrated 
or discrete components. A calibration step, which can be performed at 
system start-up, is implemented to maximize the amount of charge recycled.

In the second method we aim to optimize the trade-off between gate-drive 
loss and conduction loss in order to more efficiently actuate the power 
devices.  We show that the optimal gate swing value scales with the 
load, and introduce straight-forward control methods for achieving 
autonomous operation with near-optimum performance. We also discuss the 
combined operation of these two gate drive methods, including key 
changes to the control and calibration subsystems.

To verify these concepts, a synchronous buck dc-dc converter was 
designed in a 0.5um CMOS technology. The chip was tested over various 
conditions of switching frequency, input voltage, output voltage, and 
load. Converter power loss at light loads is shown to be significantly 
reduced, sometimes by as much as 30%, with efficiency improvements of 
nearly 8% for nominal conditions.