Reminder: PEUG Meeting--October 12, 2006

Jim McVittie mcvittie at cis.Stanford.EDU
Tue Oct 10 09:08:46 PDT 2006


NCCAVS PEUG User Group
October Meeting Announcement

NO NEED TO REGISTER - JUST SHOW UP!!

Session Topic:  MEMS

Co-Chairs:  Lucia Feng, lmfeng at earthlink.net and Jim McVittie, Stanford
University, jmcvittie at stanford.edu,

Date:  October 12, 2006

TIME:   2:00-5:00pm  (TALKS WILL BEGIN @ 2:15 PM SO PLEASE BE ON TIME!)

Location:  National Semiconductor
                 955 Kifer Rd.
                 Sunnyvale, CA

DIRECTIONS:

>From 101: Go south on Lawrence Expressway. Turn right on Kifer Rd. Turn
>right into the driveway of the National Semiconductor Auditorium (955
>Kifer Rd.) and find parking in the rear parking lot. The auditorium is on
>the West Side of the building and can be entered from the door in the
>rear next to the company park.

>From 280: Go north on Lawrence Expressway. Turn left on Kifer Rd. Follow directions above.

AGENDA:
2:00 - 2:15 pm Refreshments/PEUG Business Meeting
2:15 - 5:00 pm Presentations

1. "Global MEMS Markets and Opportunities", Doug McKesson, SEMI,
dmckesson at semi.org <mailto:dmckesson at semi.org>

This talk will give a brief overview and forecast for MEMS devices, MEMS
equipment and MEMS materials markets.  MEMS applications trends and
developments in process technologies will also be discussed.

2. "Optical MEMS platform for low cost on-chip integration of planar light
circuits and optical switching", Joel Kubby, UCSC, jkubby at soe.ucsc.edu

This talk will review a technology platform for on-chip integration of
latching MEMS optical waveguide switches and Planar Light Circuit (PLC)
components using a Silicon On Insulator (SOI) based process. To illustrate
the current state of this new technology platform, working prototypes of a
Reconfigurable Optical Add/Drop Multiplexer (ROADM) and a l-router will be
presented along with details of the integrated latching MEMS optical
switches.

3. "Nanophotonic devices and their on-chip integration with Silicon,
Indium Phosphide and Gallium Arsenide", Hatice Altug and Jelena Vuckovic,
Stanford University, altug at stanford.edu

ABSTRACT TBD 

4. "MEMS Production Processes Development Using STS VPX DRIE", Yaqiang
Wang, Quanbo Zou, Dino Lei, Uppili Sridhar, and Tito Chowdhury, Dallas
Semiconductor-Maxim, Yaqiang.Wang at misnts1.dalsemi.com

Deep Reactive Ion Etch (DRIE) processes are critical to bring MEMS devices
into production for varied applications based on silicon and
silicon-on-insulator (SOI) substrates. Production requires stable,
repeatable, and highly selective etch process with good throughput to meet
design specifications. This talk will focus on MEMS product development at
Dallas Semiconductor-Maxim using a recently released STS VPX DRIE
platform. We have achieved etch rate of 12 um/min, 89-degree slope angle,
and scalloping feature size 210 nm for varied devices.

5. "Enabling DRIE processes for high potential MEMS products", 
Michel Puech, Alcatel Micro Machining Systems, Michel.PUECH at adixen.fr

Deep Reaction Ion Etching (DRIE) technology using inductively coupled
plasma (ICP) has proven to be one of the key steps for the fabrication of
Silicon based MEMS devices.

Principal advantages of this technology include higher etching rates,
compatibility with photo resist masks, and the ability to produce vertical
side-walls on silicon substrates of any crystal orientation, which allows
the fabrication of 3D high aspect ratio structures.

Thanks to this technique, MEMS products are gaining interest and being
integrated into the every day life products (accelerometers, ink jet
heads, silicon microphones,...).  Equipment Manufacturers have then to
address the related processing challenges and anticipate the mass
production needs by developing advanced cost-effective processes and
tools.

MEMS industry is looking for much higher aspect ratio trenches, capability
to minimize the ARDE effect while increasing the throughput with higher
etch rate.

After introducing the latest developments toward higher etch rate, we
discuss about a new technique for more than tripling the state-of-the-art
trench aspect ratio from 30 to 100. Results are presented showing
sub-micron 0.4 µm wide trenches etched down to a depth of 40 µm. In a
second part, a method for reducing the ARDE effect, also called RIE lag,
is being discussed.

Results are presented showing less than 1% etch depth variation between 10
µm and 200 µm width silicon features while maintaining excellent
uniformity.
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Future Meetings:

Nov. 12-17-AVS 53rd International Symposium, San Francisco, CA.  For
details visit www.avs.org <http://www.avs.org/>

December 14-Nanointegration, Submit abstracts to:  Brett Cruden,
bcruden at arc.nasa.gov; Ramas Raman, ramas at surmet.com; Halbert Tam,
htam at jsrmicro.com; and Kapila Wijekoon, kapila_wijekoon at amat.com
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NCCAVS User Group website: www.avsusergroups.org <http://www.avsusergroups.org/>  
Find: Meeting Schedules, Announcements, Call for Papers, Committee Contact
Information, Proceedings from monthly meetings and more.

Sign up for a User Group: www.avsusergroups.org <http://www.avsusergroups.org/> 

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