From goldhaber-gordon at stanford.edu Thu Feb 1 09:37:40 2007 From: goldhaber-gordon at stanford.edu (David Goldhaber-Gordon) Date: Thu, 1 Feb 2007 09:37:40 -0800 Subject: Thermal evaporator available? Message-ID: Hi all, I would like to deposit gold with 1% antimony for ohmic contacts to an n-Si/SiGe heterostructure. I have this material in the form of a thin wire. Does anyone have a thermal evaporator in which I could do two or three evaporations of this material over the coming month (or other suggestions)? Note that antimony has extremely low vapor pressure, so it is unlikely to contaminate other materials used in the evaporator, provided different boats are used of course. Thanks in advance, David -- ----------------------------------------------------------------- David Goldhaber-Gordon goldhaber-gordon at stanford.edu Assistant Professor of Physics davidg at post.harvard.edu and Deputy Director, (permanent forwarding) Center for Probing the Nanoscale www.goldhaber-gordon.com Stanford University www.stanford.edu/group/cpn/ (650) 725-2047 (lab) (650) 724-3709 (office) Address for letters or packages: Administrative Associate: David Goldhaber-Gordon Roberta Edwards Geballe Laboratory for Advanced Materials McCullough, Rm. 338 McCullough Building, Room 346 Phone: (650) 723-8028 476 Lomita Mall Fax: (650) 724-3681 Stanford, CA 94305-4045 email: redward at stanford.edu From hansj at stanford.edu Thu Feb 1 12:25:02 2007 From: hansj at stanford.edu (Shu-Jen Han) Date: Thu, 1 Feb 2007 12:25:02 -0800 Subject: Reminder: Ph.D. Oral Examination - Shu-Jen Han - Feb. 2, 2007 Message-ID: <1170361502.45c24c9eb0a62@webmail> "CMOS integrated biosensor array based on GMR devices and magnetic nanoparticles" Shu-Jen Han Department of Materials Sci. and Eng. Advisor: Professor Shan X. Wang Date: Friday, February 2nd, 2007 Time: 9:45AM (Refreshment served at 9:30AM) Place: CISX auditorium (101) Abstract: Molecular recognition is exploited in assay techniques such as those based on DNA hybridization microarrays. Integrating biosensor arrays and other laboratory functions on a single CMOS chip yields a low-cost system that constitutes a promising tool for future biological diagnostics. Magnetic biosensors are under active development and may soon rival established biological detection methods that use surface-bond fluorescent tags. In a magnetoresistive biosensor detection scheme, single?stranded DNA receptors are immobilized on the surface of giant magnetoresistive (GMR) sensors. Oligonucleotides of unknown sequence are selectively captured by complementary probes. Streptavidin coated magnetic nanoparticles are then introduced and bind to the biotin of the hybridized DNA. Finally, magnetic field disturbances due to the nanoparticles are sensed by GMR devices. In this work, we have designed and fabricated the first GMR sensor integrated CMOS biochip. The chip has been fabricated in a 0.25?m BiCMOS process, and sub-micron sized sensors were successfully integrated with the diced chip. It contains >1000 sensing elements within 1mm^2, together with low noise, high throughput readout channels for high sensitivity DNA detection on the same chip. Compared to complex and expensive optical detection systems, the GMR biochip measures electrical signal directly from the sensor, and makes a highly portable and sensitive device feasible. From mahnaz at stanford.edu Fri Feb 2 14:18:09 2007 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 02 Feb 2007 14:18:09 -0800 Subject: Dump rinse Message-ID: <45C3B8A1.7010303@stanford.edu> Hello all, I like to let you all know that Jim Haydon has borrowed the controller from the webmis ( litho area ) dump rinse to use it in Nitride bench. This is a temporary loan till he gets his controller back. If you need to use the dump rinse in the litho area, we need to arrange for it so please let me know a head of time so I can schedule it. mahnaz From nevran at stanford.edu Sun Feb 4 16:46:09 2007 From: nevran at stanford.edu (Nevran Ozguven) Date: Sun, 04 Feb 2007 16:46:09 -0800 Subject: Ph.D. Dissertation Defense (Feb 8th) - Nevran Ozguven Message-ID: <45C67E51.2040004@stanford.edu> "Interdiffusion Studies in Si-Ge Heterostructures and Selective Oxidation for Ge-on-Insulator" Nevran Ozguven Department of Materials Science and Engineering Advisor : Professor Paul McIntyre Date : Thursday, February 8th, 2007 Time : 2PM (Refreshments served at 1:45 PM) Place : CISX 101 (Auditorium) * *Abstract: Recently, Si/Si_1-x Ge_x _ heterostructures have gained interest for use in MOS devices. These structures offer significant improvements in device performance relative to Si due to their enhanced carrier mobilities. Compared to other lattice mismatched systems, Si/Si_1-x Ge_x heterostructures are especially attractive due to their compatibility with mainstream CMOS processing technology. The Si/Si_1-x Ge_x _ system has been understood well enough to be implemented in commercial products. However, there is still a need for fundamental research, especially regarding methods to prepare Ge-rich Si_1-x Ge_x of controlled strain and composition on Si substrates. During device fabrication, processing temperatures in the range of 600-1000?C are typically used. It is therefore important to understand the temperature-dependent mechanisms of Si-Ge interdiffusion and strain relaxation in detail. In this study, two different conditions of interdiffusion in Si-Ge heterostructures were explored. We first present interdiffusion results of single-crystal Si_1-x Ge_x /Si_1-y Ge_y superlattices, with an epitaxial Si capping layer, grown by low-pressure chemical vapor deposition (LPCVD) on Si (001) substrates. During post-deposition dry oxidations, which inject interstitial defects, the Si cap was partially consumed. The effects of oxidation on Si-Ge interdiffusion were studied over the temperature range of 770-870?C. The interdiffusion kinetics, including Ge concentration effects, were measured via high-resolution x-ray diffraction (XRD). Experiments were performed on superlattice samples annealed in both inert and oxidizing ambients. We have observed enhancement in interdiffusion during oxidation. This indicates that the non-equilibrium point defect concentrations created during Si oxidation can significantly modify Si-Ge interdiffusion rates. These results allow us to place bounds on the interstitial- and vacancy-mediated contributions to Si-Ge interdiffusion. We also investigate the effects of direct oxidation of an LPCVD-grown Si_1-x Ge_x layer prepared on an SOI (100) substrate. In this case, thermal oxidation was carried out at temperatures below the Si_1-x Ge_x melting point. This is a possible means of preparing high-mobility Ge-rich films on insulator for future high-performance transistors. During oxidation, the Ge atoms are rejected from the SiO_2 layers, and their out-diffusion is suppressed by the top and buried oxides. As a result, the thickness of the Si_1-x Ge_x layer decreases, while its Ge concentration increases. The Ge fraction and the strain in the Si_1-x Ge_x layer as a function of oxidizing conditions were determined using XRD. Secondary ion mass spectrometry (SIMS) was used to observe Ge depth profiles, while transmission electron microscopy (TEM) was used to measure film thicknesses. We found that it is possible to retain the initial in-plane lattice spacing of the SOI layer after selective Si oxidation for final Si_1-x Ge_x layers with ~60% Ge composition and thicknesses exceeding critical layer thickness values. -------------- next part -------------- An HTML attachment was scrubbed... URL: From adhikari at stanford.edu Mon Feb 5 09:04:01 2007 From: adhikari at stanford.edu (Hemant Adhikari) Date: Mon, 5 Feb 2007 09:04:01 -0800 Subject: Ph.D. Dissertation Defense, Feb 9th-Hemant Adhikari Message-ID: Growth and Passivation of Germanium Nanowires Hemant Adhikari Thesis Advisors: Prof. Paul C. McIntyre, Prof. Christopher E.D. Chidsey Location: CIS-X 101 Time: Feb, 9th 2007. 1.00 PM. (Refreshments served at 12.45PM) One-dimensional structures such as nanotubes and nanowires are being actively investigated for various applications in nanotechnology, including nanoelectronics. Silicon- or germanium-based nanowire devices are particularly desirable for electronic and other applications because of their compatibility with silicon integrated circuits. In 3-dimensional nanoelectronics, vertically aligned nanowires have been proposed to provide a solution to attain ultra high density nanoscale device arrays. This study demonstrates the growth of vertically aligned single-crystal germanium nanowires (GeNWs) at temperatures of 400?C or less by metal nanoparticle-catalyzed chemical vapor deposition. Because wires grown at higher temperatures are tapered, a two-temperature growth procedure was used to obtain epitaxial GeNWs of constant diameter. Epitaxially oriented GeNWs are also demonstrated on Ge (110), Ge (001) and on a hetero-epitaxial Ge film on Si (001) substrates. The mechanisms governing low temperature epitaxial growth of Ge nanowires (NWs) during gold nanoparticle-catalyzed chemical vapor deposition remain controversial. For the experimental conditions studied, temperatures close to the bulk Au-Ge eutectic are required for efficient nanowire nucleation, but subsequent growth of GeNWs could occur at undercoolings as large as 90?C below the eutectic. The generally accepted vapor-liquid-solid (VLS) mechanism of NW growth requires the presence of a eutectic liquid. We have investigated possible sub-eutectic VLS growth of Ge NWs both experimentally and theoretically. This study presents the equilibrium phase diagrams for the Au-Ge binary in the nanometer-scale regime. We find that equilibrium arguments, including capillary effects, do not explain VLS for the growth conditions studied. Observations from ex-situ heating and cooling behavior of GeNWs (without Ge deposition) inside a transmission electron microscope column suggest that there is a kinetic barrier to solid Au nucleation which can cause a substantial undercooling of the liquid below the bulk eutectic temperature. We have also explored the possibility of the presence of liquid catalyst at large undercoolings because of Ge supersaturation of the Au-Ge catalyst particle during NW growth. Surface passivation of GeNWs before deposition of dielectric and metal layers has been identified as a key step to fabricate high-performance devices. A detailed investigation of the surface chemistry of as-grown and air-exposed GeNWs and exploration of various chemical passivation pathways was undertaken by photoemission using a low energy synchrotron source. We also demonstrate uniform encapsulation of vertically aligned dense array of germanium nanowires by a highly conformal SiO2? layer synthesized by alternating-layer deposition. While most of the conventional techniques either require high deposition temperatures or else fail to fill such high aspect ratio nanostructures without introducing voids in the oxide, this alternating-layer-deposition process results in rapid conformal deposition of several monolayers of silica in each cycle at temperatures as low as 250?C. The growth and surface passivation of GeNWs demonstrated forms a sound basis for application of NWs in ultra-high areal density devices for dimensional scaling of semiconductor memory and logic. From nevran at stanford.edu Thu Feb 8 01:53:14 2007 From: nevran at stanford.edu (Nevran Ozguven) Date: Thu, 08 Feb 2007 01:53:14 -0800 Subject: Ph.D. Dissertation Defense (Today - 2PM) - Nevran Ozguven Message-ID: <45CAF30A.6020202@stanford.edu> "Interdiffusion Studies in Si-Ge Heterostructures and Selective Oxidation for Ge-on-Insulator" Nevran Ozguven Department of Materials Science and Engineering Advisor : Professor Paul McIntyre Date : Thursday, February 8th, 2007 Time : 2PM (Refreshments served at 1:45 PM) Place : CISX 101 (Auditorium) * *Abstract: Recently, Si/Si_1-x Ge_x _ heterostructures have gained interest for use in MOS devices. These structures offer significant improvements in device performance relative to Si due to their enhanced carrier mobilities. Compared to other lattice mismatched systems, Si/Si_1-x Ge_x heterostructures are especially attractive due to their compatibility with mainstream CMOS processing technology. The Si/Si_1-x Ge_x _ system has been understood well enough to be implemented in commercial products. However, there is still a need for fundamental research, especially regarding methods to prepare Ge-rich Si_1-x Ge_x of controlled strain and composition on Si substrates. During device fabrication, processing temperatures in the range of 600-1000?C are typically used. It is therefore important to understand the temperature-dependent mechanisms of Si-Ge interdiffusion and strain relaxation in detail. In this study, two different conditions of interdiffusion in Si-Ge heterostructures were explored. We first present interdiffusion results of single-crystal Si_1-x Ge_x /Si_1-y Ge_y superlattices, with an epitaxial Si capping layer, grown by low-pressure chemical vapor deposition (LPCVD) on Si (001) substrates. During post-deposition dry oxidations, which inject interstitial defects, the Si cap was partially consumed. The effects of oxidation on Si-Ge interdiffusion were studied over the temperature range of 770-870?C. The interdiffusion kinetics, including Ge concentration effects, were measured via high-resolution x-ray diffraction (XRD). Experiments were performed on superlattice samples annealed in both inert and oxidizing ambients. We have observed enhancement in interdiffusion during oxidation. This indicates that the non-equilibrium point defect concentrations created during Si oxidation can significantly modify Si-Ge interdiffusion rates. These results allow us to place bounds on the interstitial- and vacancy-mediated contributions to Si-Ge interdiffusion. We also investigate the effects of direct oxidation of an LPCVD-grown Si_1-x Ge_x layer prepared on an SOI (100) substrate. In this case, thermal oxidation was carried out at temperatures below the Si_1-x Ge_x melting point. This is a possible means of preparing high-mobility Ge-rich films on insulator for future high-performance transistors. During oxidation, the Ge atoms are rejected from the SiO_2 layers, and their out-diffusion is suppressed by the top and buried oxides. As a result, the thickness of the Si_1-x Ge_x layer decreases, while its Ge concentration increases. The Ge fraction and the strain in the Si_1-x Ge_x layer as a function of oxidizing conditions were determined using XRD. Secondary ion mass spectrometry (SIMS) was used to observe Ge depth profiles, while transmission electron microscopy (TEM) was used to measure film thicknesses. We found that it is possible to retain the initial in-plane lattice spacing of the SOI layer after selective Si oxidation for final Si_1-x Ge_x layers with ~60% Ge composition and thicknesses exceeding critical layer thickness values. -------------- next part -------------- An HTML attachment was scrubbed... URL: From jonroth at stanford.edu Thu Feb 8 09:48:01 2007 From: jonroth at stanford.edu (Jonathan Edgar Roth) Date: Thu, 8 Feb 2007 09:48:01 -0800 Subject: Other options for Nitride / Oxide deposition? Message-ID: <1170956881.45cb62511a610@webmail.stanford.edu> This morning STS PECVD's hard drive stopped working. Does anyone know of any other (external?) options for depositing silicon nitride and silicon dioxide on pieces? Thermal oxidation won't work for me. Thanks. Jon From adhikari at stanford.edu Fri Feb 9 11:44:05 2007 From: adhikari at stanford.edu (Hemant Adhikari) Date: Fri, 9 Feb 2007 11:44:05 -0800 Subject: Reminder: Ph.D. Dissertation Defense, Today 1PM Hemant Adhikari Message-ID: On 2/5/07, Hemant Adhikari wrote: > Growth and Passivation of Germanium Nanowires > Hemant Adhikari > Thesis Advisors: Prof. Paul C. McIntyre, Prof. Christopher E.D. Chidsey > Location: CIS-X 101 > Time: Feb, 9th 2007. 1.00 PM. (Refreshments served at 12.45PM) > > One-dimensional structures such as nanotubes and nanowires are being > actively investigated for various applications in nanotechnology, > including nanoelectronics. Silicon- or germanium-based nanowire > devices are particularly desirable for electronic and other > applications because of their compatibility with silicon integrated > circuits. In 3-dimensional nanoelectronics, vertically aligned > nanowires have been proposed to provide a solution to attain ultra > high density nanoscale device arrays. This study demonstrates the > growth of vertically aligned single-crystal germanium nanowires > (GeNWs) at temperatures of 400?C or less by metal > nanoparticle-catalyzed chemical vapor deposition. Because wires grown > at higher temperatures are tapered, a two-temperature growth procedure > was used to obtain epitaxial GeNWs of constant diameter. Epitaxially > oriented GeNWs are also demonstrated on Ge (110), Ge (001) and on a > hetero-epitaxial Ge film on Si (001) substrates. > The mechanisms governing low temperature epitaxial growth of Ge > nanowires (NWs) during gold nanoparticle-catalyzed chemical vapor > deposition remain controversial. For the experimental conditions > studied, temperatures close to the bulk Au-Ge eutectic are required > for efficient nanowire nucleation, but subsequent growth of GeNWs > could occur at undercoolings as large as 90?C below the eutectic. The > generally accepted vapor-liquid-solid (VLS) mechanism of NW growth > requires the presence of a eutectic liquid. We have investigated > possible sub-eutectic VLS growth of Ge NWs both experimentally and > theoretically. This study presents the equilibrium phase diagrams for > the Au-Ge binary in the nanometer-scale regime. We find that > equilibrium arguments, including capillary effects, do not explain VLS > for the growth conditions studied. Observations from ex-situ heating > and cooling behavior of GeNWs (without Ge deposition) inside a > transmission electron microscope column suggest that there is a > kinetic barrier to solid Au nucleation which can cause a substantial > undercooling of the liquid below the bulk eutectic temperature. We > have also explored the possibility of the presence of liquid catalyst > at large undercoolings because of Ge supersaturation of the Au-Ge > catalyst particle during NW growth. > Surface passivation of GeNWs before deposition of dielectric and metal > layers has been identified as a key step to fabricate high-performance > devices. A detailed investigation of the surface chemistry of as-grown > and air-exposed GeNWs and exploration of various chemical passivation > pathways was undertaken by photoemission using a low energy > synchrotron source. We also demonstrate uniform encapsulation of > vertically aligned dense array of germanium nanowires by a highly > conformal SiO2? layer synthesized by alternating-layer deposition. > While most of the conventional techniques either require high > deposition temperatures or else fail to fill such high aspect ratio > nanostructures without introducing voids in the oxide, this > alternating-layer-deposition process results in rapid conformal > deposition of several monolayers of silica in each cycle at > temperatures as low as 250?C. > The growth and surface passivation of GeNWs demonstrated forms a sound > basis for application of NWs in ultra-high areal density devices for > dimensional scaling of semiconductor memory and logic. > From mtang at stanford.edu Fri Feb 9 17:19:22 2007 From: mtang at stanford.edu (Mary Tang) Date: Fri, 09 Feb 2007 17:19:22 -0800 Subject: Suss Spray Coater? Message-ID: <45CD1D9A.80701@stanford.edu> Hi everyone -- Several labmembers have expressed an interest in opening up a discussion about the possibility of obtaining a spray coater, designed to aerosolize resists to ensure conformal coating on substrates with extreme topography. Suss offers a spray coater system that has been recommended by at least one interested party. Spray coating has been demonstrated to be a great way to deposit even thick resists (even silicone elastomer) on topographies which cannot be coated by conventional spin coating. More information is available on the Suss website at: www.suss.com -- and some cool photos can be seen in the attached brochure. If this method sounds like something you could use, drop an email to either me or Mahnaz Mansourpour. It would be helpful to know what your general application would be and exactly how interested (i.e., willing to commit funds or sweat equity) you and your lab might be in obtaining this capability here. Thanks for your time and attention -- Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- A non-text attachment was scrubbed... Name: Spraycoating_enhances_3D_processes[2].pdf Type: application/pdf Size: 229359 bytes Desc: not available URL: From jerabek at snf.stanford.edu Mon Feb 12 13:08:08 2007 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Mon, 12 Feb 2007 13:08:08 -0800 Subject: mask writer Message-ID: <001201c74ee9$e53e2470$916540ab@czech1> To whom it may concern: Micronic mask writer is down due to random failure during exposure. This could be caused by an interferometer problem or a computer problem. I just recently found out that disk drive #2 is full even thou there are very few files on it. Micronic field engineering has been notified of the problem. -Paul -------------- next part -------------- An HTML attachment was scrubbed... URL: From iwjung at stanford.edu Tue Feb 13 10:59:36 2007 From: iwjung at stanford.edu (Il Woong Jung) Date: Tue, 13 Feb 2007 10:59:36 -0800 Subject: Orals abstract Il Woong Jung Message-ID: <20070213185935.333694BF98@smtp2.stanford.edu> "Spatial light modulators for applications in coherent communication, adaptive optics and maskless lithography" Il Woong Jung, Dept. of Electrical Engineering Advisor: Professor Olav Solgaard Date: Friday, February 16th, 2007 Time: 2:00pm (refreshments served at 1:45pm) Place: Packard 101 Abstract Optical MEMS devices have been used in a variety of applications including fiber optic communications, projection TVs and biomedical imaging devices. MEMS-based spatial light modulators (SLM) provide a compact, large scale, and cost-effective solution to these and other applications. In this talk, we introduce the design and fabrication of SLMs for three such applications. Coherent communications between ground based stations and aircraft or satellites, and imaging/targeting of objects at large distances (>1000km) require wavefront control to correct for aberrations due to the atmosphere in addition to very fast scanning ability. We introduce a tip-tilt-piston electrostatic combdrive mirror array with the ability of the individual mirrors to do 2-dimensional angular deflection as well as piston deflection for scanning and wavefront control. Second, in NASA's program to search for earth-like planets, an optical system with the wavefront corrected to lambda/3000 at the detector is required. Image degradation is mainly due to the polishing errors of the primary mirror in a space-based telescope. To correct for the polishing errors we present a SCS (single-crystal-silicon) continuous facesheet deformable mirror. In the IC industry, as masks become prohibitively expensive, there is motivation to use a programmable mask to reduce time and cost in the development and production stage in IC manufacturing. For our third application, we present a piston-type dual-lever actuator mirror array as a programmable mask for maskless lithography. We demonstrate the various capabilities of the SLM in optical pattern generation such as sub-grid patterning, line-width modulation, checkboard generated lines and spaces, and vortex vias. We also present a MEMS scanner with a photonic crystal slab as a high reflectivity broadband mirror. Photonic crystal slabs can achieve higher reflectivity and allow higher processing temperatures than metals and are simpler to fabricate than multi-layer dielectric stacks, which shows potential for wafer-scale encapsulation of optical MEMS devices. Il Woong Jung ----------------------- Research Assistant EL Ginzton Labs 450 Via Palou S31 Stanford CA 94305 phone: 650-723-1992 email: iwjung at stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From dhum at stanford.edu Tue Feb 13 11:28:46 2007 From: dhum at stanford.edu (David Hum) Date: Tue, 13 Feb 2007 11:28:46 -0800 Subject: Ph.D. Oral Examination - David S. Hum - Feb. 15, 2007 Message-ID: Title: Frequency conversion in periodically poled, near-stoichiometric lithium tantalate fabricated by vapor transport equilibration David S. Hum Department of Electrical Engineering Stanford University Adviser : Professor Martin M. Fejer Date : Thursday, February 15, 2007 Time : 11:00am (Refreshments at 10:45am) Location : CIS-X Auditorium Abstract: Frequency conversion using quasi-phasematched (QPM) nonlinear devices is efficient and engineerable. One method of quasi-phasematching can be realized by periodically poling ferroelectrics. Lithium tantalate, like many ferroelectrics, is limited in application by photorefractive damage (PRD) in the commonly available, congruently melting composition. Vapor-transport-equilibrated, near-stoichiometric lithium tantalate (VLT) has been shown to have reduced defect concentrations and increased photoconductivity. Because of the two-order of magnitude increase in photoconductivity, VLT has improved resistance to PRD and has been used to demonstrate efficient and stable frequency conversion at high average powers. QPM devices based on VLT have allowed the demonstration of near room-temperature generation of visible light. Generation of 10 W of CW 532-nm radiation by second harmonic generation from 29 W of 1064-nm radiation has been demonstrated in a 4-cm-long device. Devices periodically poled for generation of 589-nm radiation by both second harmonic and sum frequency generation have also been demonstrated as near room temperature, multi-watt sources. Control of the ferroelectric properties allowed periodic poling down to a period of 5 microns, suitable for generation of 458.3-nm radiation by second harmonic generation. Investigations into the application of periodic poling and vapor transport equilibration on rotated-cut VLT crystals have led to the development of aperture-scalable, quasi-phasematched devices suitable for high peak- and average-power nonlinear optics. From dalyx at stanford.edu Thu Feb 15 13:27:58 2007 From: dalyx at stanford.edu (Dany-Sebastien Ly-Gagnon) Date: Thu, 15 Feb 2007 13:27:58 -0800 Subject: GeOI wafers Message-ID: <7f014b6b0702151327h7f2b0a62te9a3315a8c880115@mail.gmail.com> Hi all, Does anyone know a vendor that can provide Germanium on Insulator wafers? I would also appreciate any information you would have about the pricing / availability of these. Regards, Dany Ly-Gagnon Miller's Group From neureuth at eecs.berkeley.edu Thu Feb 15 15:32:00 2007 From: neureuth at eecs.berkeley.edu (Andrew R Neureuther) Date: Thu, 15 Feb 2007 15:32:00 -0800 Subject: Orals abstract Il Woong Jung In-Reply-To: <20070213185935.333694BF98@smtp2.stanford.edu> References: <20070213185935.333694BF98@smtp2.stanford.edu> Message-ID: <45D4ED70.5090200@eecs.berkeley.edu> All, Confirming that I will arrive by 1:45 Tomorrow. I look forward to the presentation and discussion. Andy Il Woong Jung wrote: > > > "Spatial light modulators for applications in coherent communication, > adaptive optics and maskless lithography" > > > > Il Woong Jung, Dept. of Electrical Engineering > > Advisor: Professor Olav Solgaard > > > > Date: Friday, February 16th, 2007 > > Time: 2:00pm (refreshments served at 1:45pm) > > Place: Packard 101 > > > > Abstract > > Optical MEMS devices have been used in a variety of applications > including fiber optic communications, projection TVs and biomedical > imaging devices. MEMS-based spatial light modulators (SLM) provide a > compact, large scale, and cost-effective solution to these and other > applications. In this talk, we introduce the design and fabrication of > SLMs for three such applications. Coherent communications between ground > based stations and aircraft or satellites, and imaging/targeting of > objects at large distances (>1000km) require wavefront control to > correct for aberrations due to the atmosphere in addition to very fast > scanning ability. We introduce a tip-tilt-piston electrostatic combdrive > mirror array with the ability of the individual mirrors to do > 2-dimensional angular deflection as well as piston deflection for > scanning and wavefront control. Second, in NASA's program to search for > earth-like planets, an optical system with the wavefront corrected to > lambda/3000 at the detector is required. Image degradation is mainly due > to the polishing errors of the primary mirror in a space-based > telescope. To correct for the polishing errors we present a SCS > (single-crystal-silicon) continuous facesheet deformable mirror. In the > IC industry, as masks become prohibitively expensive, there is > motivation to use a programmable mask to reduce time and cost in the > development and production stage in IC manufacturing. For our third > application, we present a piston-type dual-lever actuator mirror array > as a programmable mask for maskless lithography. We demonstrate the > various capabilities of the SLM in optical pattern generation such as > sub-grid patterning, line-width modulation, checkboard generated lines > and spaces, and vortex vias. We also present a MEMS scanner with a > photonic crystal slab as a high reflectivity broadband mirror. Photonic > crystal slabs can achieve higher reflectivity and allow higher > processing temperatures than metals and are simpler to fabricate than > multi-layer dielectric stacks, which shows potential for wafer-scale > encapsulation of optical MEMS devices. > > > > > > Il Woong Jung > > ----------------------- > > Research Assistant > > EL Ginzton Labs > > 450 Via Palou S31 > > Stanford CA 94305 > > phone: 650-723-1992 > > email: iwjung at stanford.edu > > > > > > > > > > > > > From fengj at stanford.edu Thu Feb 15 18:36:39 2007 From: fengj at stanford.edu (Jia Feng) Date: Thu, 15 Feb 2007 18:36:39 -0800 Subject: Serious Contamination in the Clean-room! In-Reply-To: <7f014b6b0702151327h7f2b0a62te9a3315a8c880115@mail.gmail.com> References: <7f014b6b0702151327h7f2b0a62te9a3315a8c880115@mail.gmail.com> Message-ID: <1171593399.45d518b7c2700@webmail.stanford.edu> Dear lab members: I found a long piece of hair inside one of the teflon boxes of wbmetal just now. This is a very serious contamination. There are oil, Na, K, and many other contaminations you can imagine from such a piece of hair. This is NOT a biology lab! Let's do a simple math. If you have a 40-nm gate oxide (as used in EE 410), you need only an ion density of 5.5E11 /cm^2 to change the threshold voltage by 1 volt if the ions sit on the Si/SiO2 interface. For a 4-inch wafer, this density means only 4E13 ions across the entire wafer. How heavy are those ions if they are sodium? You only need about 1.5E-9 gram of sodium to change the threshold voltage of all the devices on one 4-inch wafer by 1 volt!!! It seems that more and more people do not make electronic devices any more. But the particles from the hair can still destroy the mirrors, lenses, and cantilevers. I have seen people unhappy with the paricles in nitride which harm their optics on silicon. Then how about the particles from the hair or hand? Please keep our clean room really clean. What you can simply do is to change gloves before you touch the teflon cassette, put the teflon cassette on the inner side of the cover rather than on anything else, handle the wafers by tweezers rather than by hand, and clean your wafers if you want to put them into any chambers or furnaces. If you are unclear about something, ask. If you see sources of contamination, let the staff members know. If you happen to contaminate something, let the staff members know and they will not punish you. Regards, Jia From mahnaz at stanford.edu Fri Feb 16 10:02:16 2007 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 16 Feb 2007 10:02:16 -0800 Subject: dump rinser Message-ID: <45D5F1A8.80507@stanford.edu> Hello all, Controller on Nitride wet bench died again so I am letting Jim Haydon borrow the controller from the litho dump rinser ( head way bench). We are hopping to get the matter resolved in one week, if this is causing any issues please let me know. mahnaz From iwjung at stanford.edu Fri Feb 16 13:47:11 2007 From: iwjung at stanford.edu (Il Woong Jung) Date: Fri, 16 Feb 2007 13:47:11 -0800 Subject: Orals abstract Il Woong Jung today at 2pm resfreshments 1:45 In-Reply-To: Message-ID: <20070216214712.D03834BE1F@smtp1.stanford.edu> "Spatial light modulators for applications in coherent communication, adaptive optics and maskless lithography" Il Woong Jung, Dept. of Electrical Engineering Advisor: Professor Olav Solgaard Date: Friday, February 16th, 2007 Time: 2:00pm (refreshments served at 1:45pm) Place: Packard 101 Abstract Optical MEMS devices have been used in a variety of applications including fiber optic communications, projection TVs and biomedical imaging devices. MEMS-based spatial light modulators (SLM) provide a compact, large scale, and cost-effective solution to these and other applications. In this talk, we introduce the design and fabrication of SLMs for three such applications. Coherent communications between ground based stations and aircraft or satellites, and imaging/targeting of objects at large distances (>1000km) require wavefront control to correct for aberrations due to the atmosphere in addition to very fast scanning ability. We introduce a tip-tilt-piston electrostatic combdrive mirror array with the ability of the individual mirrors to do 2-dimensional angular deflection as well as piston deflection for scanning and wavefront control. Second, in NASA's program to search for earth-like planets, an optical system with the wavefront corrected to lambda/3000 at the detector is required. Image degradation is mainly due to the polishing errors of the primary mirror in a space-based telescope. To correct for the polishing errors we present a SCS (single-crystal-silicon) continuous facesheet deformable mirror. In the IC industry, as masks become prohibitively expensive, there is motivation to use a programmable mask to reduce time and cost in the development and production stage in IC manufacturing. For our third application, we present a piston-type dual-lever actuator mirror array as a programmable mask for maskless lithography. We demonstrate the various capabilities of the SLM in optical pattern generation such as sub-grid patterning, line-width modulation, checkboard generated lines and spaces, and vortex vias. We also present a MEMS scanner with a photonic crystal slab as a high reflectivity broadband mirror. Photonic crystal slabs can achieve higher reflectivity and allow higher processing temperatures than metals and are simpler to fabricate than multi-layer dielectric stacks, which shows potential for wafer-scale encapsulation of optical MEMS devices. Il Woong Jung ----------------------- Research Assistant EL Ginzton Labs 450 Via Palou S31 Stanford CA 94305 phone: 650-723-1992 email: iwjung at stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mahnaz at stanford.edu Fri Feb 16 14:24:39 2007 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 16 Feb 2007 14:24:39 -0800 Subject: [Fwd: dump rinser] Message-ID: <45D62F27.4070004@stanford.edu> Things did not work out so the exchange did not happen, the dump rinser in litho is up and running. mahnaz -------- Original Message -------- Subject: dump rinser Date: Fri, 16 Feb 2007 10:02:16 -0800 From: Mahnaz Mansourpour Organization: SNF To: Lab Hello all, Controller on Nitride wet bench died again so I am letting Jim Haydon borrow the controller from the litho dump rinser ( head way bench). We are hopping to get the matter resolved in one week, if this is causing any issues please let me know. mahnaz -------------- next part -------------- An HTML attachment was scrubbed... URL: From rissman at stanford.edu Sun Feb 18 14:50:57 2007 From: rissman at stanford.edu (Paul Rissman) Date: Sun, 18 Feb 2007 14:50:57 -0800 Subject: disruption in lithography - Monday, 2/19/07 Message-ID: <1171839057.45d8d851af736@webmail.stanford.edu> Hi All, You may know that for some months now we have been negotiating with ASML to have them install a model 5500/60 i-line stepper at SNF. The installation will occur tomorrow, Monday 2/19/07. The system will arrive at about 8 AM and we expect that it will go in the cleanroom at about 10 AM. You should expect disruption in lithography and no access to the equiment at the end of the first lithography aisle (ovens, yes oven, mask cleaner, solvent bench). The installation should be complete by 4 PM. We are sorry for the inconvenience. More details on the capability of the stepper will be available from the SNF website next week. Paul Rissman From mtang at stanford.edu Sun Feb 18 23:39:29 2007 From: mtang at stanford.edu (Mary Tang) Date: Sun, 18 Feb 2007 23:39:29 -0800 Subject: wbdiff problems Message-ID: <45D95431.90603@stanford.edu> Labmembers -- Our deepest apologies -- It looks like wbdiff is having a heck of a time this weekend (as well as a number of labmembers). Although it is not shutdown, please do not try to use the HCl pot or the HF dump rinser at wbdiff. Instead, wbsilicide can be used for diffusion cleans -- BUT ONLY IF IT IS FIRST DECONTAMINATED. Instructions for decontamination are listed on the Coral problem note for wbsilicide. If the next person who needs a diffusion clean could do this decontamination (and write it up on Coral, so that no one uses it for non-diff clean processing), he/she would earn the gratitude of many labmembers - and a lunch on me. Again, on behalf of the staff, our apologies -- Mary From jhaydon at stanford.edu Mon Feb 19 10:02:34 2007 From: jhaydon at stanford.edu (Jim Haydon) Date: Mon, 19 Feb 2007 10:02:34 -0800 Subject: wbdif problems Message-ID: <45D9E63A.2000500@stanford.edu> Labmembers The HCL hot pot is working at the moment. I found that one of the connections on the level switch sensor was install incorrectly and was flaky. Probably my mistake. I have reprogramed the dump rinser controller and installed a power line conditioner. My apologies for any inconvenience or frustrations these problems have caused you. Jim Haydon From rissman at stanford.edu Mon Feb 19 12:22:18 2007 From: rissman at stanford.edu (Paul Rissman) Date: Mon, 19 Feb 2007 12:22:18 -0800 Subject: lithography now open Message-ID: <200702192022.l1JKMJ1u017045@smtp-roam.Stanford.EDU> Hi All, The ASML is in place and lithography is now completely open. The YES oven was not shutdown, so it is ready for use. However, it has a venting problem, so if you don't know what you are doing, you shouldn't use it. This will be addressed in the morning. Paul Rissman From mtang at stanford.edu Tue Feb 20 07:31:26 2007 From: mtang at stanford.edu (Mary Tang) Date: Tue, 20 Feb 2007 07:31:26 -0800 Subject: [Fwd: CCNE Nano-Bio Seminar, Tuesday, 2/20/07, 4:30PM, Clark Auditorium, Bio-X] Message-ID: <45DB144E.8000203@stanford.edu> -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An embedded message was scrubbed... From: Billie Robles Subject: CCNE Nano-Bio Seminar, Tuesday, 2/20/07, 4:30PM, Clark Auditorium, Bio-X Date: Tue, 20 Feb 2007 07:28:54 -0800 Size: 91983 URL: From jerabek at snf.stanford.edu Wed Feb 21 14:34:00 2007 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Wed, 21 Feb 2007 14:34:00 -0800 Subject: Hitachi ebeam computer Message-ID: <000a01c75608$61994430$916540ab@czech1> To whom it may concern: this email is mainly directed at labmembers using instruments located in the "ebeam room". In spite of a sign I've placed next to the Hitachi ebeam computer asking users not to use the computer as a convenient side table I am finding almost every day stacks of stuff on top of it. At times a pile(s) of stuff is so heavy as to bend top metal plate of the computer case . This is a very old computer and at this time nearly irreplaceable and I am woried that all this fussing around it might compromise the integrity of the computer case and of computer itself. I specificaly do not like to see people leaning on the computer and bumping into it during Raith classes. Please do exercise little caution when working around that computer. I do realize that Raith computer station is right next to it, bur please be careful. -Paul J. -------------- next part -------------- An HTML attachment was scrubbed... URL: From raldaz at stanford.edu Thu Feb 22 14:12:17 2007 From: raldaz at stanford.edu (Rafael Aldaz) Date: Thu, 22 Feb 2007 14:12:17 -0800 Subject: Ph.D. Oral Examination - Rafael I. Aldaz Message-ID: <1c60b4660702221412p694accaco7be10ca2a5823f8c@mail.gmail.com> Ph.D. Oral Examination *Towards the monolithic integration of mode-locked vertical cavity surface emitting lasers * Rafael I. Aldaz Department of Electrical Engineering Adviser: Professor James S. Harris Date: Friday, March 2nd, 2007 Time: 1:30pm (Refreshments at 1:15pm) Location: CIS-X Auditorium Abstract: The speed and performance of today's high end computing and communications systems have placed difficult but feasible demands on off-chip electrical interconnects. However, future interconnect systems may need aggregate bandwidths well into the terahertz range thereby making electrical bandwidth, density, and power targets very difficult to meet. Optical interconnects, and specifically compact semiconductor mode-locked lasers, could alleviate this problem by providing short pulses in time at 10s of GHz for Optical Time Division Multiplexing (OTDM) and clock distribution applications. Furthermore, the characteristic spectral comb of frequencies of these lasers could also serve as a multi-wavelength source for Wavelength Division Multiplexing (WDM) applications. A fully integrated mode-locked Vertical Cavity Surface Emitting Laser (VCSEL) is proposed as a low-cost high-speed source for these applications. The passive mode-locking mechanism of the laser is provided by a semiconductor saturable absorber integrated together with the gain region. Such an aggressive integration forces the resonant beam in the cavity to have the same area on the gain and absorber, placing high demands on the saturation fluence and absorption coefficient for the saturable absorber. Quantum Wells (QWs), excitons in QWs and Quantum Dots (QDs) have been investigated as possible saturable absorbers for the proposed device. QDs have been found to have the lowest saturation fluence and total absorption, necessary for meeting the mode-locking requirements for this configuration. The need to further understand QDs as saturable absorbers has led to the development of a theoretical model on the dynamics of this quantum system. The model agrees very well with the experimental data obtained and predicts the design of unassisted ultrafast QD saturable absorbers, without the need to incorporate recombination center by either ion-implantation or low temperature growth. -------------- next part -------------- An HTML attachment was scrubbed... URL: From pethe at stanford.edu Thu Feb 22 16:10:17 2007 From: pethe at stanford.edu (Abhijit Jayant Pethe) Date: Thu, 22 Feb 2007 16:10:17 -0800 Subject: Ph.D. Orals Announcement- Abhijit Pethe Message-ID: <1172189417.45de30e9dff6d@webmail.stanford.edu> GE-BASED TRANSISTORS FOR HIGH-PERFORMANCE LOGIC APPLICATIONS Abhijit Pethe Department of Electrical Engineering Advisor: Prof. Krishna Saraswat Date: February 28, 2007 Time: 10:00am (Refreshments at 9:45am) Place: CISX Auditorium Abstract Ultra-fast and reliable switching transistors have been the backbone of explosive growth in the semiconductor industry over the last few decades. This has been achieved mainly by continued scaling of transistor dimensions to achieve higher drive currents and higher switching speeds. However, with gate lengths presently scaling into the sub-50nm regime, switching these devices off may pose a considerable challenge to their reliable operation. One way to continue enhancing device performance involves the introduction of novel materials in the channel to boost drive currents without compromising off-state characteristics. In the first part of the talk, we will discuss the performance limits of MOSFETs using various materials such as Ge and III-Vs. Though many of these materials have low electron effective mass providing for higher injection velocities, they also have high dielectric constants and smaller bandgaps, making them susceptible to higher leakage and worse short channel effects. Ballistic transport simulations considering conduction in all valleys, quantum effects in thin film structures, band-to band tunneling and short-channel effects, were performed for transistors with suitable architectures in the sub-20nm regime. Studied materials were benchmarked for their efficacy as nMOS channels. Our results show that under normal operation, a majority of the ON current in the III-V materials occurs through the heavier L-valleys, and hence these materials perform similarly to Ge. In the second part of the talk, we will discuss experimental results of bulk Ge transistors. We have obtained higher electron and hole inversion mobilities in bulk-Ge transistors compared to Si. A gate stack of thermally grown GeOxNy capped with CVD SiO2 was used. We have investigated the Dit at the gate interface using low-temperature quasi-static and conductance measurements and report a low interface trap density of 3-4E11 #/cm-2. We also discuss the effect of surface orientation on the mobility and interface states at the gate interface. Replacement of MOSFET Source/Drain regions with metals of suitable barrier heights has been investigated as a method to increase performance by reducing parasitic resistance. We have characterized the barrier heights of various metals on the Ge interface. We report a low barrier height of ~100mV at the NiGe/Ge interface and have successfully fabricated NiGe-based Schottky Source/Drain Ge transistors. We have also fabricated Si/Ge/Si heterostructure MOSFETs with Schottky S/D to increase inversion layer mobility without adversely impacting off-state leakage. This transistor provides an attractive avenue for pMOSFET scaling into the sub-25nm regime by exploiting the excellent transport properties of inversion holes in Ge and the use of metal in the Source/Drain regions to reduce parasitic resistance. From mtang at stanford.edu Thu Feb 22 22:04:10 2007 From: mtang at stanford.edu (Mary Tang) Date: Thu, 22 Feb 2007 22:04:10 -0800 Subject: MicroResist Presentation: Nanoimprint Resists and Ormocers, 2/23/07 Message-ID: <45DE83DA.8060101@stanford.edu> Greetings labmembers: Apologies for the late notice... Marko Vogler, from MicroResist, will be presenting information about new polymers for nanoimprinting (UV and thermal) and functional hybrid polymers for micro-optics (Ormocers.) The presentation will be Friday, 2/23/07, at 10 am in CIS 201. Dr. Vogler will be available afterwards for questions and discussion. Mary From pethe at stanford.edu Mon Feb 26 19:16:44 2007 From: pethe at stanford.edu (Abhijit Jayant Pethe) Date: Mon, 26 Feb 2007 19:16:44 -0800 Subject: Reminder: Ph.D. Oral Examination - Abhijit Pethe Wed 10:00AM Message-ID: <1172546204.45e3a29cd549b@webmail.stanford.edu> GE-BASED TRANSISTORS FOR HIGH-PERFORMANCE LOGIC APPLICATIONS Abhijit Pethe Department of Electrical Engineering Advisor: Prof. Krishna Saraswat February 28, 2007 10:00am (Refreshments at 9:45am) CISX Auditorium Abstract Ultra-fast and reliable switching transistors have been the backbone of explosive growth in the semiconductor industry over the last few decades. This has been achieved mainly by continued scaling of transistor dimensions to achieve higher drive currents and higher switching speeds. However, with gate lengths presently scaling into the sub-50nm regime, switching these devices off may pose a considerable challenge to their reliable operation. One way to continue enhancing device performance involves the introduction of novel materials in the channel to boost drive currents without compromising off-state characteristics. In the first part of the talk, we will discuss the performance limits of MOSFETs using various materials such as Ge and III-Vs. Though many of these materials have low electron effective mass providing for higher injection velocities, they also have high dielectric constants and smaller bandgaps, making them susceptible to higher leakage and worse short channel effects. Ballistic transport simulations considering conduction in all valleys, quantum effects in thin film structures, band-to band tunneling and short-channel effects, were performed for transistors with suitable architectures in the sub-20nm regime. Studied materials were benchmarked for their efficacy as nMOS channels. Our results show that under normal operation, a majority of the ON current in the III-V materials occurs through the heavier L-valleys, and hence these materials perform similarly to Ge. In the second part of the talk, we will discuss experimental results of bulk Ge transistors. We have obtained higher electron and hole inversion mobilities in bulk-Ge transistors compared to Si. A gate stack of thermally grown GeOxNy capped with CVD SiO2 was used. We have investigated the Dit at the gate interface using low-temperature quasi-static and conductance measurements and report a low interface trap density of 3-4X1011 #/cm-2. We also discuss the effect of surface orientation on the mobility and interface states at the gate interface. Replacement of MOSFET Source/Drain regions with metals of suitable barrier heights has been investigated as a method to increase performance by reducing parasitic resistance. We have characterized the barrier heights of various metals on the Ge interface. We report a low barrier height of ~100mV at the NiGe/Ge interface and have successfully fabricated NiGe-based Schottky Source/Drain Ge transistors. We have also fabricated Si/Ge/Si heterostructure MOSFETs with Schottky S/D to increase inversion layer mobility without adversely impacting off-state leakage. This transistor provides an attractive avenue for pMOSFET scaling into the sub-25nm regime by exploiting the excellent transport properties of inversion holes in Ge and the use of metal in the Source/Drain regions to reduce parasitic resistance. From vigneshg at stanford.edu Tue Feb 27 12:47:04 2007 From: vigneshg at stanford.edu (Vignesh Gowrishankar) Date: Tue, 27 Feb 2007 12:47:04 -0800 Subject: Defects in silica and passivating them Message-ID: <6.2.1.2.2.20070227121658.06212230@vigneshg.pobox.stanford.edu> Hi All, After seeing unexpected results in an experiment, we seem to think that the (mesoporous) silica we used had a lot of defects, perhaps mid-gap. Do any of you have any experience / knowledge of such defects, and how to possibly passivate them? I have found that silica does have photoluminescence at 2.3 eV, 3.1 eV and 4.2 eV or so, which somewhat confirms our belief. Does anybody have more information? Thanks, Vignesh. From ccreese at stanford.edu Tue Feb 27 13:01:24 2007 From: ccreese at stanford.edu (Colin Reese) Date: Tue, 27 Feb 2007 13:01:24 -0800 Subject: ARC for Resist In-Reply-To: <6.2.1.2.2.20070227121658.06212230@vigneshg.pobox.stanford.edu> References: <6.2.1.2.2.20070227121658.06212230@vigneshg.pobox.stanford.edu> Message-ID: <45E49C24.5080205@stanford.edu> Hello all, I'm spin-coating PR on top of 2-6um PDMS and performing lithography atop of it. I've been using 3617M to prevent transmission and reflection. Resolution is fine, however adhesion is not so great, resulting in feature-related cracks across the wafer. I'm looking for either an intermediate layer to improve adhesion, or an Anti-Reflective Coating that can perform this function and allow me to use a different resist. Any suggestions welcomed. Regards, Colin From aokyay at stanford.edu Tue Feb 27 14:05:32 2007 From: aokyay at stanford.edu (Ali Kemal Okyay) Date: Tue, 27 Feb 2007 14:05:32 -0800 Subject: Ph. D. Oral Examination - Ali Kemal Okyay Fri 8:45AM Message-ID: <001b01c75abb$6a9607f0$c76418ac@kapadokya> Ph. D. Oral Examination SI-GE PHOTODETECTION TECHNOLOGIES FOR INTEGRATED OPTOELECTRONICS Ali K. Okyay Department of Electrical Engineering Adviser: Professor Krishna C. Saraswat Date: Friday, March 2nd, 2007 Time: 8:45am (Refreshments at 8:30am) Location: CIS-X Auditorium Abstract: The communications bottleneck is identified as one of the grand challenges in the progress of silicon computation. While individual logic elements have become significantly faster, computational speed is limited by the communication between different parts of a processor. Traditional copper wires are efficient at short distances, but they suffer excessive power dissipation and delay in global lines, and cannot cope with the ever growing bandwidth demand. Moreover, with the chip architectures evolving towards a modular design, the requirements for increased bandwidth density further strain the electrical interconnects. Optical interconnects (OIs) can provide a solution to the communication bottleneck by alleviating significant power dissipation and delay problems faced by copper wires. Monolithically integrated photodetectors with very low capacitance are sought after for the receiver end of high performance OIs. In the first part of the talk, we will discuss Ge based metal-semiconductor-metal (MSM) optical detectors integrated on Silicon. The Ge layer is grown by a novel multi-step Ge-on-Si direct epitaxial growth technique. An important byproduct of this growth technique is tensile strain within the Ge film, resulting in enhanced absorption around 1550 nm. We will present experimental results of electrical and optical characterization of Ge detectors. We have report very high responsivity of 0.84 A/W at 1550 nm. We have investigated the origin of strain in the Ge layers, and report a significant red shift in the absorption edge of Ge in these films. In the second part of the talk, we will discuss a novel CMOS compatible optoelectronic switch. The proposed device is a Si MOSFET with Ge gate. We have investigated the basic operation of the proposed device. The gate photocurrent is amplified by the MOSFET current gain at the drain terminal. We will present experimental proof-of-principle demonstration of device operation. We will discuss complementary function in the proposed device by simulations. -------------- next part -------------- An HTML attachment was scrubbed... URL: