Reminder: Ph.D. Oral Examination - Abhijit Pethe Wed 10:00AM

Abhijit Jayant Pethe pethe at stanford.edu
Mon Feb 26 19:16:44 PST 2007


GE-BASED TRANSISTORS FOR HIGH-PERFORMANCE LOGIC APPLICATIONS

Abhijit Pethe
Department of Electrical Engineering
Advisor: Prof. Krishna Saraswat

February 28, 2007
10:00am (Refreshments at 9:45am)
CISX Auditorium

Abstract

Ultra-fast and reliable switching transistors have been the backbone of
explosive growth in the semiconductor industry over the last few decades.
This has been achieved mainly by continued scaling of transistor dimensions
to achieve higher drive currents and higher switching speeds. However, with
gate lengths presently scaling into the sub-50nm regime, switching these
devices off may pose a considerable challenge to their reliable operation.
One way to continue enhancing device performance involves the introduction
of novel materials in the channel to boost drive currents without
compromising off-state characteristics.

In the first part of the talk, we will discuss the performance limits of
MOSFETs using various materials such as Ge and III-Vs. Though many of these
materials have low electron effective mass providing for higher injection
velocities, they also have high dielectric constants and smaller bandgaps,
making them susceptible to higher leakage and worse short channel effects. 
Ballistic transport simulations considering conduction in all valleys,
quantum effects in thin film structures, band-to band tunneling and
short-channel effects, were performed for transistors with suitable
architectures in the sub-20nm regime.  Studied materials were benchmarked
for their efficacy as nMOS channels. Our results show that under normal
operation, a majority of the ON current in the III-V materials occurs
through the heavier L-valleys, and hence these materials perform similarly
to Ge.

In the second part of the talk, we will discuss experimental results of bulk
Ge transistors. We have obtained higher electron and hole inversion
mobilities in bulk-Ge transistors compared to Si. A gate stack of thermally
grown GeOxNy capped with CVD SiO2 was used. We have investigated the Dit at
the gate interface using low-temperature quasi-static and conductance
measurements and report a low interface trap density of 3-4X1011 #/cm-2. We
also discuss the effect of surface orientation on the mobility and interface
states at the gate interface. Replacement of MOSFET Source/Drain regions
with metals of suitable barrier heights has been investigated as a method
to increase performance by reducing parasitic resistance. We have
characterized the barrier heights of various metals on the Ge interface. We
report a low barrier height of ~100mV at the NiGe/Ge interface and have
successfully fabricated NiGe-based Schottky Source/Drain Ge transistors. We
have also fabricated Si/Ge/Si heterostructure MOSFETs with Schottky S/D to
increase inversion layer mobility without adversely impacting off-state
leakage. This transistor provides an attractive avenue for pMOSFET scaling
into the sub-25nm regime by exploiting the excellent transport properties
of inversion holes in Ge and the use of metal in the Source/Drain regions
to reduce parasitic resistance.



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