Reminder: Hoon Cho(chozone)'s oral defense tomorrow July 5th, 10am(Thursday), @CIS-X Audi
chozone at stanford.edu
Wed Jul 4 20:32:41 PDT 2007
Ph. D. Oral Examination
Low Power, Highly Scalable, Vertical Flash Memory Cell and MOSFET
Department of Electrical Engineering
Adviser: Professor Krishna C. Saraswat
Date: Thursday, July 5th, 2007
Time: 10:00am (Refreshments at 9:45am)
Location: CIS-X Auditorium
Conventional floating gate NOR flash memory faces serious scaling challenges. One of the impediments stems from the relative non-scalability of gate length due to large short channel effects (SCE) and an inability to scale the gate stack (leakage control requirements). On the transistors side, to mitigate the impending power crisis in modern ICs, multi-gate devices and having dynamic Vt adjustment are considered promising options. A vertical, 3D MOSFET paradigm, with current flow perpendicular to the wafer plane, provides a versatile option as both a low power, scalable transistor, as well as a scalable flash cell. The scalability in the case of flash cell is achieved by removing the gate length (non-lithographically defined) from the critical path by placing it in the direction perpendicular to the wafer plane, and through architecture level density enhancement. Whereas, a vertical double gate transistor (not a FINFET) is attractive because of the process complexity problems with the planar double gate (DG) FETs and width discretization issues with the FINFET structure.
We experimentally demonstrate and characterize a sub-30nm body thickness, vertical channel, symmetric double gate MOSFETs which is highly versatile. We show it to function as a 1) scalable multi-bit NOR flash memory cell, 2) DGFET with the two gates tied together showing excellent short channel effect immunity, 3) a back-gated transistor with a dynamic Vt adjustment knob for low power, and as a 4) capacitorless, single transistor, DRAM. These devices are demonstrated on a bulk-silicon substrate as apposed to an SOI substrate, thus provide a low cost option. The devices are fueled by several key, unit process innovations, which in themselves exhibit the versatility of being independently implemented in other applications. The process innovations include: 1) a new spacer process capable of building hard masks of thicknesses down to 5nm; 2) a novel self-aligned process exploiting curvature dependent differential poly-silicon oxidation rates to make either thick field oxide at the vertical device corners, a drain contact to thin vertical bodies, and to achieve electrical isolation between the two gates on either side of a vertical device; 3) a novel drain contact process including etch stop and implant. Extensive MEDICITM and TSUPREM4TM simulations are used for device/process design. The process, in principle, is scalable down to sub-5nm body thicknesses, does not require CMP, and is capable of being integrated with a planar CMOS flow with minimal additional mask steps.
Excellent electrical properties in the form of Id-Vd, Id-Vg and Ig-Vg are measured for both the vertical DGFET and for the multi-bit flash memory. For vertical DGFET, we also electrically measure a large Vt shift with an independent back bias on the second gate, a close to ideal subthreshold slope (64mV/decade) in the symmetric double gate operational mode, and retention times in excess of 25ms in the capacitorless DRAM operational mode. For the NOR flash memory, we also present fully functional devices exhibiting excellent program, erase, and retention. In addition, we extensively study the important effect of charge interference from the cell sharing the thin body in terms of device scalability, mitigating solutions, and even possibly exploiting it to increase the number of bits per cell.
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