MIT Club Event: 3D Chip Technologies - Thur 6/14, 6:30-8:30pm, Palo Alto

Alissa M. Fitzgerald amf at
Wed Jun 6 22:59:26 PDT 2007

"Good Things Come in Small Packages: 3D Chip Technologies"


Date:	 06/14/2007 Thursday
Time:	 6:30pm	 (networking), 7pm (discussion start)
Venue:	 Cooley Godward Kronish LLP 	
Location: 3175 Hanover Street, Palo Alto, CA 	
Cost: $20 pre-registered on-line before 9pm on 6/13; $30 after (includes
Contact: alissa.fitzgerald at	

Online Registration Link:

The desire for smaller and thinner handsets and other portable devices is
just one of the many forces driving chip integration and packaging
innovations. New technologies, such as 3D device structures, chip stacking,
and through-silicon vias, are opening up the third dimension to facilitate
increasingly compact chip and package designs. Advance packaging also
promises seamless heterogeneous integration of analog components,
compound-semiconductors, opto-electronics, MEMS, and even bio-sensors, for
exciting new system applications.

Join us for a panel discussion on the near- and long-term prospects for
engineering chips in the third dimension, featuring representatives from
companies involved in 3D package technologies and 3D system integration.

Topics for discussion:
-          For what current applications is 3D integration essential?
-          Are today's 3D integration and packaging techniques cost
-          How are new devices being enabled by 3D technologies?
-          How are packaging technologies affecting chip design and EDA?
-          Where are there opportunities for entrepreneurs?

Moderator: Eelco Bergman, Semiconductor Industry Consultant

*	Charles White, VP of Advanced Technology Initiatives, Tessera
*	Raymond C. Wiley, VP North America Sales and Marketing, Icemos
Technology, Ltd.
*	Dr. Marcos Karnezos, former CTO, STATS ChipPAC


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