retrograde doping for NMOS switch

Kevin Huang kevhuang at
Thu Jun 21 14:33:25 PDT 2007

         I would like to make an NMOS switch in the SNF that can sustain 50V
gate voltage and low leaking due to drain induced barrier lowering.  I'd
like the gate length to be 1.5 um and width is 130um.  I did one run
following the EE410 process but the leakage is too big and the break down
voltage is only at about 6V.  I learned that I can get what I want with a
retrograde doping profile.  So I was wondering if anyone has done something
like this and if so, could I know the implant recipe that was used?  I want
to use As as the dopant because of its lower diffusivity.

Thanks for the help.

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