From jerabek at snf.stanford.edu Thu Mar 1 14:47:43 2007 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Thu, 1 Mar 2007 14:47:43 -0800 Subject: system up Message-ID: <000a01c75c53$9fa218f0$916540ab@czech1> To whom it may concern: Micronis laser writer is back up for production. -Paul -------------- next part -------------- An HTML attachment was scrubbed... URL: From sjo at stanford.edu Fri Mar 2 12:24:43 2007 From: sjo at stanford.edu (Sebastian J. Osterfeld) Date: Fri, 02 Mar 2007 12:24:43 -0800 Subject: Who has QC process automation expertise - pls. advise Message-ID: <45E8880B.1000409@stanford.edu> Dear Labmembers, Many of the devices we make at the SNF need thorough quality control and testing, so as to properly qualify them for actual use. This is very tedious work, as many of you probably know from your own work. I am looking to automate the quality control process for our chips, and I would like to know if there are good examples of custom-built, automated quality control stations at Stanford. I am planning on having a setup with several pumps and fluidic valves, and a high number of I/O data channels that are automatically interrogated as our chip iterates through many possible configurations and operating conditions. So if you happen to know a research group or maybe a contractor who has gone through the process of designing and building a customized automated QC setup, then please let me know. I would very much like to have a look and talk to someone with experience in that area. Many thanks! - - Sebastian J. Osterfeld Ph.D. Candidate Shan X. Wang Group, MagArray Project Dept. of Materials Science & Engineering Stanford University From mtang at stanford.edu Fri Mar 2 18:33:51 2007 From: mtang at stanford.edu (Mary Tang) Date: Fri, 02 Mar 2007 18:33:51 -0800 Subject: Ammonium Fluoride Crystals at wet benches Message-ID: <45E8DE8F.9000309@stanford.edu> Labmembers: We have got a serious problem! Large clumps of ammonium fluoride crystals have been observed on several wet benches (wbgen2, wbdiff, wbnonmetal, and wbmetal). These crystals have been found on the benchtops, on top of the dump rinser lids, on the side splash shields, on TOP of the upper splash shield, and down the front of one bench continuing to the floor. This appears to be happening during the night, since these crystals are found in the morning. This was first observed last week (http://snf.stanford.edu/cgi-bin/ezmlm-cgi?1600:mss:125:200702:abibmcjcckmmpcidocfi) and has been observed yesterday morning and this morning. We are presuming that someone or some people are extraordinarily sloppy in their handling of HF-BOE etchants. Just to remind everyone -- ammonium fluoride is as bad for you as HF because as soon as it hits moisture (like on your skin), it turns into HF which is readily absorbed through your skin and evaporates so you can inhale it. For your reference, here's a section from the JT Baker MSDS for BOE etchants and ammonium fluoride. *Skin Contact:* Wipe off any excess material from skin and then immediately flush skin with large amounts of soapy water. Remove contaminated clothing and shoes. Wash clothing before re-use. Apply bandages soaked in magnesium sulfate. CALL A PHYSICIAN IMMEDIATELY. *Label Hazard Warning:* DANGER! MAY BE FATAL IF SWALLOWED OR INHALED. AFFECTS RESPIRATORY SYSTEM, HEART, SKELETON, CIRCULATORY SYSTEM, CENTRAL NERVOUS SYSTEM AND KIDNEYS. CAUSES IRRITATION AND BURNS TO SKIN, EYES AND RESPIRATORY TRACT. IRRITATION AND BURN EFFECTS MAY BE DELAYED. HARMFUL IF ABSORBED THROUGH SKIN. I hope everyone is as mad about this as I am. On behalf of the SNF staff, I'm asking you the following: - Be observant when you are in the lab. Report any problems to staff. But don't be afraid to tell someone when you uncomfortable with their lab procedure -- this is your safety they are risking too! - . Be careful using the wet benches. Treat any liquid as if it were acid (as it very well may be!) Treat crystals as if they were acid (because they will be!) Leave the bench space clean when you leave it. In the meantime, we are continuing to investigate. If you have any observations or suggestions to share, please don't hesitate to drop us a note. Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From rcrane at snf.stanford.edu Mon Mar 5 08:13:09 2007 From: rcrane at snf.stanford.edu (Dick Crane) Date: Mon, 05 Mar 2007 08:13:09 -0800 Subject: Missing power meter Message-ID: <45EC4195.1020305@snf.stanford.edu> Labmembers, We are missing a lamp power meter and need your help in locating it. The Ultratech specific, AIO 350, lamp power meter, which normally lives at its charging station in Finger Wall 13, has disappeared. I assume someone has moved it or borrowed it. We need it to perform normal PM tasks on the Ultratech. If you know the location of the missing meter, please let Mario, Mahnaz or me know as soon as possible. Thanks, Dick From kattsai at stanford.edu Mon Mar 5 09:28:18 2007 From: kattsai at stanford.edu (Katherine Tsai) Date: Mon, 5 Mar 2007 09:28:18 -0800 Subject: anyone have SU8-2050? Message-ID: <1c62e49d0703050928x5ef78ae9waa177174be4efa5f@mail.gmail.com> Dear Labmembers, Does anyone have extra SU8-2050 that he/she would be willing to spare? We need approximately 80-100 mL but Microchem only sells it in 500 mL quantities. If you do, please let us know. Thanks! Best regards, Katherine Tsai & Maryam Ziaei-Moayyed -------------- next part -------------- An HTML attachment was scrubbed... URL: From randalls at stanford.edu Mon Mar 5 17:26:43 2007 From: randalls at stanford.edu (Randy Mark Stoltenberg) Date: Mon, 5 Mar 2007 17:26:43 -0800 Subject: Si 110 wafers needed Message-ID: <1173144403.45ecc353e9e69@webmail.stanford.edu> My group is interested in running some initial experiments using Si wafers with 110 orientation. If anyone has a couple they could spare (preferably with an oxide or nitride layer), we would be grateful. We would also be glad to reimburse in kind if needed. Randy Stoltenberg From rcrane at stanford.edu Tue Mar 6 09:58:44 2007 From: rcrane at stanford.edu (Dick Crane) Date: Tue, 06 Mar 2007 09:58:44 -0800 Subject: Varian VacuumTechnology Seminar 3/20/07 Message-ID: <45EDABD4.2060601@stanford.edu> Lab and CIS/CISX building dwellers, It is time for our annual Varian Vacuum Technology Seminar to be held on Tuesday, March 20, 2007 from 10:00 to 2:00 in CISX101. The seminar includes a vacuum technology manual and free lunch, but you need to pre-register. Please see detail below or in the attachment. See you there, Dick Vacuum Technology Seminar FREE Seminar, Manual and Refreshments The Objective. Assist in the training and education of scientists, engineers and technicians in the art and science of VACUUM. Who is this for? Anyone with an interest in Vacuum Science will benefit from this seminar. Skilled practitioners can expect to gain valuable insights and pointers while those with minimal vacuum experience will receive a comprehensive treatment of high and ultra high vacuum practice. Taught by a trained vacuum expert. . Approximately four hours in length . Informal to allow for questions and answers . Comprehensive manual provided FREE . Limited registration Contents . HV/UHV Introduction . System Pressure . Total Gas Load . Materials Selection . System Pumping Speed . Gauges . System Operation . Troubleshooting . Q & A Session Location, Date & Contact Information Date: Tuesday, March 20, 2007 Time: 10:00 AM to 2:00 PM Location: Paul Allen Center for Integrated System Annex, Room 101 (CISX101) Contact: To register, contact Gary Scarsdale - Call 408.248.8061 or e-mail gary.scarsdale at varianinc.com Sponsored by: Varian, Inc.'s Vacuum Technologies, 1.800.882.7426, a world leader in vacuum pumps and components, dedicated to the advancement of the art and science of vacuum. Hosted by: Stanford Nanofabrication Facility Presentation of this event on the Stanford Campus does not imply or represent endorsement by Stanford University regarding content, programming, materials or associated organizations. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: VacSeminar3-20-07-Flyer.pdf Type: application/pdf Size: 149908 bytes Desc: not available URL: From ybkim at stanford.edu Tue Mar 6 14:47:57 2007 From: ybkim at stanford.edu (Young Beom Kim) Date: Tue, 6 Mar 2007 14:47:57 -0800 Subject: Looking for PbS (Lead Sulfide) or PbSe (Lead Selenide) sputtering targets Message-ID: <20070306224757.B74EE4C045@smtp1.stanford.edu> Hi, if anyone knows someone who has one of those sputtering targets or if you have one of those in your group, lab or somewhere, please let me know the contact info. I would like to use one of those to deposit just few atomic layers(of course I'll pay for that) or I would like to buy if possible. Also, if you have information of vendors which can make those targets as soon as possible (my contact takes 4 weeks) please let me know plea~~se~~! Thank you so much and have a great day~! YoungBeom -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Wed Mar 7 09:22:47 2007 From: mtang at stanford.edu (Mary Tang) Date: Wed, 7 Mar 2007 09:22:47 -0800 Subject: Litho Temp & Humidity control problem Message-ID: <1173288167.45eef4e75d11c@webmail.stanford.edu> Labmembers -- Just to let you know -- The power plant across the street has lost steam, which means that the lithography area in the lab has little control over temperature and humidity. The equipment is still functioning but be aware of this problem, especially if you have critical litho processes. Updates will follow. The SNF staff From closega at stanford.edu Wed Mar 7 13:05:16 2007 From: closega at stanford.edu (Gael Close) Date: Wed, 7 Mar 2007 13:05:16 -0800 Subject: Pre-metal-deposition clean for via Message-ID: <1e089c430703071305r359e5bfcx72f2819cb0fb2176@mail.gmail.com> Dear labmembers, I am trying to deposit Al in via holes. It is critical that I minimize the contact resistance between the underlying Al present at the bottom of the hole, and the Al to be deposited. I think the normal procedure is to run a quick etch right before deposition in the same chamber to clean up the bottom of the hole. Gryphon is capable of this, but my sample is gold-contaminated. Is there any gold-contaminated alternative: like a quick dip in Al etchant, before depositing Al in metallica? Will this give me a decent contact? Thank you? -- Gael Close PhD Candidate Center for Integrated Systems, CISX-300 Stanford University, California +1-650-450-3567 From mwiemer at stanford.edu Wed Mar 7 13:44:11 2007 From: mwiemer at stanford.edu (Michael Wiemer) Date: Wed, 7 Mar 2007 13:44:11 -0800 Subject: Ph.D. Orals Examination - Mike Wiemer Message-ID: Ph.D. Oral Examination *Monolithically Integrated Long Vertical Cavity Surface Emitting Lasers* Michael W. Wiemer Department of Electrical Engineering Advisor: Professor David A. B. Miller Date: Tuesday, March 13th, 2007 Time: 10:00am (Refreshments at 9:45am ) Location: Packard 101 Abstract: Electrical interconnect technology in computing and communication systems is under extreme pressure to improve performance and meet future demands. Future systems will need aggregate interconnect bandwidths well into the terahertz range, thereby making electrical spatial bandwidth density and power targets very difficult to meet. However, link performance is not the only consideration. In a typical interconnect system, the number of links rapidly increases as link distance decreases, making low cost per link also critical. Thus, if computing system performance is to scale into the future as it has in the past, a low-cost yet high-performance short distance interconnect technology must be found. Under certain conditions, optical interconnect solutions can decrease link power consumption over their electrical counterparts. In addition, Optical Wavelength Division Multiplexing (WDM) may increase the spatial bandwidth density of an interconnect. Due to the bosonic nature of light, optical waves do not interact with each other. Thus, in contrast to the electrical paradigm where a different metallic wire is required for every electrical interconnect signal, a single optical waveguide can simultaneously carry many data channels, each on a different optical wavelength. WDM systems therefore require multiple laser sources, each at a different, well-controlled wavelength. These two issues (large number of lasers & their strict wavelength control) increase the cost and complexity of WDM systems significantly. However, a single mode-locked laser naturally produces a spectral comb of many optical wavelengths. Such a laser could potentially replace a multitude of discrete wavelength lasers in future short distance WDM interconnect systems. A Fully Integrated Long Vertical Cavity Surface Emitting Laser (LVCSEL) platform, capable of being mode-locked, is proposed as a low-cost optical source solution for future WDM interconnects. Motivated by the concept of mode-locking, we will review our work developing this laser platform. In particular, we will address the need for high intracavity optical power/cm 2, which is required for passive mode-locking at high repetition rates. -------------- next part -------------- An HTML attachment was scrubbed... URL: From rcrane at stanford.edu Wed Mar 7 14:25:23 2007 From: rcrane at stanford.edu (Dick Crane) Date: Wed, 07 Mar 2007 14:25:23 -0800 Subject: Litho Temp and Humidity normal Message-ID: <45EF3BD3.4060705@stanford.edu> Litho users, The steam plant is back on-line so temperature and humidity in litho should soon be approaching normal values. Thanks, Dick From beinnmuir at stanford.edu Thu Mar 8 12:05:02 2007 From: beinnmuir at stanford.edu (Beinn Muir) Date: Thu, 8 Mar 2007 12:05:02 -0800 Subject: Al annealing Message-ID: <1173384302.45f06c6e5e0f5@webmail.stanford.edu> Dear Labmembers, I am interested in increasing the grain size and reducing the roughness of thermally evaporated films of Al (200-1000nm thick) deposited on Si with native oxide. Do any of you have experience with annealing Al films, or can reccommend any useful literature discussing the conditions and resulting morphology changes? Another possible route I could take would be to etch / polish the Al film to reduce roughness, but I have had limited success with this. I would be grateful for any information. Best regards, Beinn... From dparent at email.sjsu.edu Thu Mar 8 13:01:58 2007 From: dparent at email.sjsu.edu (David W. Parent) Date: Thu, 08 Mar 2007 13:01:58 -0800 Subject: Al annealing In-Reply-To: <1173384302.45f06c6e5e0f5@webmail.stanford.edu> References: <1173384302.45f06c6e5e0f5@webmail.stanford.edu> Message-ID: <7.0.1.0.0.20070308125822.01b9d8a0@email.sjsu.edu> Dear Beinn, I have had a hard time fining data on this issue. I have found though brute force experimentation that the longer the pull time on any Al film on SIO2, the greater the surface roughness, and the higher the resistivity! To reduce surface roughness and decrease RS I pull the wafers out of our furnace (AT SJSU not SNF) as quickly as possible. (I mean I yank them out.) -DAve At 12:05 PM 3/8/2007, Beinn Muir wrote: >Dear Labmembers, > >I am interested in increasing the grain size and reducing the roughness of >thermally evaporated films of Al (200-1000nm thick) deposited on Si with >native oxide. Do any of you have experience with annealing Al films, or can >reccommend any useful literature discussing the conditions and resulting >morphology changes? Another possible route I could take would be to etch / >polish the Al film to reduce roughness, but I have had limited success with >this. > >I would be grateful for any information. > >Best regards, >Beinn... From baylortriplett at earthlink.net Fri Mar 9 10:13:33 2007 From: baylortriplett at earthlink.net (Baylor B Triplett) Date: Fri, 09 Mar 2007 10:13:33 -0800 Subject: Al annealing In-Reply-To: <7.0.1.0.0.20070308125822.01b9d8a0@email.sjsu.edu> References: <1173384302.45f06c6e5e0f5@webmail.stanford.edu> <7.0.1.0.0.20070308125822.01b9d8a0@email.sjsu.edu> Message-ID: <45F1A3CD.3050003@earthlink.net> All, Al-1%Cu is a reasonable option to reduce the crystallization described below unless you have extreme needs but you have to be careful to eliminate ions and water to prevent corrosion...shelf life of the devices may be limited without passivation of the Al alloy. Another alternative is Al-2%Si with much less susceptibility to corrosion but larger crystallite sizes. Below is a little of what I remember about this subject. [ "Surface roughness" with Al or Al alloys is usually simply grain growth resulting from crystallization. Although quite dependent on film thickness (the thicker the film, the larger the crystallite sizes), it is also dependent on cooling rate...rapid cooling will minimize the grain size formed. Aluminum is particularly bad since it has a low melting point. For this reason, many in semiconductor technologies use Al-2%Si alloys or Al-0.5%, Al-2%Cu, and even Al-4%Cu to suppress grain growth and improve electromigration. However, the Achilles heel of high Cu is the strong electrochemical cell formed between Al and the Al2Cu mixed phase which suppresses the size of the crystallites. About 10 years ago (before the advent of straight Cu metallization to improve electromigration), industry.] Depending on needs more refractory metals such as Ti can also provide solutions and a dual layer of Ti plus Al alloy often works well at the expense of complexity. Baylor Triplett, Consulting Professor David W. Parent wrote: > Dear Beinn, > > I have had a hard time fining data on this issue. I have found though > brute force experimentation that the longer the pull time on any Al > film on SIO2, the greater the surface roughness, and the higher the > resistivity! To reduce surface roughness and decrease RS I pull the > wafers out of our furnace (AT SJSU not SNF) as quickly as possible. > (I mean I yank them out.) > -DAve > At 12:05 PM 3/8/2007, Beinn Muir wrote: > >> Dear Labmembers, >> >> I am interested in increasing the grain size and reducing the >> roughness of >> thermally evaporated films of Al (200-1000nm thick) deposited on Si with >> native oxide. Do any of you have experience with annealing Al films, >> or can >> reccommend any useful literature discussing the conditions and resulting >> morphology changes? Another possible route I could take would be to >> etch / >> polish the Al film to reduce roughness, but I have had limited >> success with >> this. >> >> I would be grateful for any information. >> >> Best regards, >> Beinn... > > From maurice at stanford.edu Fri Mar 9 11:27:32 2007 From: maurice at stanford.edu (Maurice M Stevens) Date: Fri, 9 Mar 2007 11:27:32 -0800 Subject: WBDiff down for at least 2 hours Message-ID: <1173468452.45f1b5246fd52@webmail.stanford.edu> 4:1 sulfuric bath is getting decontaminated right now, it might take 4 hours. Bath has to cool before it can be decon'ed From baylortriplett at earthlink.net Fri Mar 9 12:25:29 2007 From: baylortriplett at earthlink.net (Baylor B Triplett) Date: Fri, 09 Mar 2007 12:25:29 -0800 Subject: Al annealing In-Reply-To: <1173384302.45f06c6e5e0f5@webmail.stanford.edu> References: <1173384302.45f06c6e5e0f5@webmail.stanford.edu> Message-ID: <45F1C2B9.5050403@earthlink.net> Beinn, Sorry, I responded to a response to your inquiry without reading your note to see the full context. To minimize roughening by crystallization make the film as thin as possible....or use metals that have high glass transition temperatures like refractory metals such as Ti. For instance, metals typically have a glass transition temperature about 1/3 of the melting point in absolute temperature (Kelvin) and will not often crystallize below this point. Thus Ti has a glass transition temperature about 1/3 x T(melting)= 1/3 x1933 K= ~644 K or 371 C. I have often used Ti deposited by e-beam evaporation and found it to form a brown glassy layer at substrate temperatures below 300 C and a silvery metallic crystalline film at 400 C. I have assumed (but not verified) that the brown film is smoother than the crystallized film. I should point out that sputter deposition and stress change this picture by ion or electron energy annealing of the film so that it crystallizes Ti at a lower temperatures (often much lower) and e-beam can produce some spitting which can damage your smoothness if you need it over a large area. As I remember chrome sublimes so it might also be a good candidate for e-beam or thermal evaporation. There must be people in the material science dept who know much more about this than I. You might try Bill Nix. I learned some of this subject from a feloow by the name of H. Windishman...I see on Google that he published a paper entitled "Microstructural Evolution during film growth" J. Appl. Physics (1987) that also incorporates the effects of stress in ion beam sputtering. You might start there. Look also at his diamond films on metallic substrates. If you are stuck with aluminum, it's melting point is 660 C so it's glass transition temperature is about 1/3 x 933 K = 311 K or about 40 C. It crystallizes under almost all deposition conditions. The primary way I can conceive of making this crystallized film smoother is to make it much thinner. Baylor Triplett Beinn Muir wrote: > Dear Labmembers, > > I am interested in increasing the grain size and reducing the roughness of > thermally evaporated films of Al (200-1000nm thick) deposited on Si with > native oxide. Do any of you have experience with annealing Al films, or can > reccommend any useful literature discussing the conditions and resulting > morphology changes? Another possible route I could take would be to etch / > polish the Al film to reduce roughness, but I have had limited success with > this. > > I would be grateful for any information. > > Best regards, > Beinn... > > > > From beinnmuir at stanford.edu Fri Mar 9 12:53:34 2007 From: beinnmuir at stanford.edu (Beinn Muir) Date: Fri, 9 Mar 2007 12:53:34 -0800 Subject: Al annealing -- update Message-ID: <1173473614.45f1c94ee3c25@webmail.stanford.edu> Dear all, Thanks for all the replies regarding my Al deposition question. They have all been very useful. What I have learnt so far is that I need to carefully consider what surface morphology is really important for my application. I should elaborate on the purpose of using Al. I need the Al layer for electrochemical anodisation and the formation of porous surfaces, therefore using metals other than Al (or alloys) is not currently an option. The anodisation process appears to initiate at the pore boundaries, and therefore the pore density is driven by the grain size. If I want larger pores (less dense pores) then I want larger grains. It is perhaps not an important requirement that the surface is very flat, although it is possible that even if the grain size is small that if the surface is flat, or periodically textured, then the pore density will be lower -- something which is done with bulk Al anodisation during an initial electropolishing step. I have tried this electrochemical etching step with the thin films and it does not appear to change the surface morphology. A number of you have pointed out that annealing will most likely cause the roughness to increase. It also seems that the grain size is proportional to the layer thickness, so the next thing I will do is to look at >500nm thick films. In addition slow cooling will promote large grain size. One option which was suggested was to deposit thick films and then etch back. Does anyone have information on suitable etchants for Al, and whether etching is likely to reduce or increase roughness (ie will it maintain the triangular or hillock structures, or remove them)? I am still interested in trying some annealing experiments with the Al films, but I am not sure which parameters will be the most important, and where I should be in experimental space. Is it common to anneal metals below the mp for long times (hours) or above the mp for short times (minutes)? Should the cooling be done over >12 hours, or is 1-2 hours slow enough? Your thoughts would be most welcome. Thanks again for all your help. Best regards, Beinn... From xzhuang at stanford.edu Fri Mar 9 21:35:22 2007 From: xzhuang at stanford.edu (Steve Zhuang) Date: Fri, 9 Mar 2007 21:35:22 -0800 Subject: thermal oxide coverage in deep vias Message-ID: <1173504922.45f2439ab492b@webmail.stanford.edu> Dear lab members, I have a question regarding thermal oxidation coverage in deep vias. I have 20-um diameter, 300-um deep vias on a 400-um thick silicon wafer. Now when I do wet oxidation and grow 1-um thick oxide on the wafer surface, will the oxide coverage be uniform even at the bottom of the vias? I know for through-wafer vias the thermal oxide coverage is good. But now my vias are not all the way through the wafer. Anyone had such experience? Thanks Steve Zhuang Khuri-Yakub Group From xzhuang at stanford.edu Sat Mar 10 09:51:42 2007 From: xzhuang at stanford.edu (Steve Zhuang) Date: Sat, 10 Mar 2007 09:51:42 -0800 Subject: etching high aspect ratio vias using STS etcher References: <1173504922.45f2439ab492b@webmail.stanford.edu> Message-ID: <002101c7633c$c33d71c0$bb5640ab@pky7> Dear labmembers, Does anyone have experience in etching high aspect ratio vias using STS or STS2 etcher? I'd like to etch 20-um diameter, 400-um deep vias on an SOI wafer, and the etching would stop at the burried oxide layer. Is this doable? Which recipe is best suited for this particular process? Any input will be highly appreciated. Thanks a lot!! Steve Zhuang Khuri-Yakub Group From choongho.yu at gmail.com Mon Mar 12 14:54:22 2007 From: choongho.yu at gmail.com (Choongho Yu) Date: Mon, 12 Mar 2007 14:54:22 -0700 Subject: chemical mechanical polishing vendor Message-ID: <002801c764f0$ff147d50$54919888@NL> Hi SNF members, I am trying to find a vendor for a chemical and/or mechanical polishing of tiny samples. The material of my sample is SrTiO3 and its size is 5 mm x 5 mm x 0.5 mm. I want to remove 100 nm top layer, but it is extremely difficult to remove 100 nm layer with smooth surface behind. HF leave a very rough surface and ion milling leaves a damaged surface. I would appreciate if someone can send a name or contact information of the vendors. Thank you. C. Yu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mdeal at stanford.edu Thu Mar 15 12:42:23 2007 From: mdeal at stanford.edu (Michael Deal) Date: Thu, 15 Mar 2007 12:42:23 -0700 Subject: SNF and Community Day Message-ID: <6.2.5.6.2.20070315124125.01d3b4c8@stanford.edu> SNF labmembers, This year, SNF will once again participate in Stanford University's "Community Day." This is where adults and children from the neighboring cities are invited to Stanford on a Spring Sunday to visit the campus, and dozens of university organizations put on displays and demonstrations. Two years ago - Community Day is now held every other year - we had a very successful and fun day in which we taught the community about nanotechnology. We had posters, free handouts (ruler/magnifying glasses), microscope demos (where they could see structures built in our lab), and the very popular "be a junior nanoscientist (where kids put on a cleanroom suit, got the photo taken, and got a nanoscientist certificate with their name and picture on it.) We also gave tours of the cleanroom every few hours. Based on the success of previous years, and the fact that only ~30% of Community Day attendees are repeaters from before, we plan on doing basically the same thing as before. In addition, the Stanford Nanocharacterisation Laboratory (SNL) will join us, participating in the microscope activity and offering a tour of their facility. And this year our exhibit area will be right in front of CIS, not by the Hoover tower like last time. As before, I'd like to invite both staff and SNF labmembers to volunteer. The more people who participate, the more fun it will be for all of us. Community Day will be Sunday, April 15 from 10 am to 4pm. You can work part or all of it (we'll need a few here at 9am to help set up). We have lots of fun, and free lunch as well. We'll have a planning meeting some time before the event, with pizza, but it isn't necessary to attend that in order to help out on the actual day. So if you are interested in helping out and participating in SNF's nano activities at Community Day (April 15), please reply to me as soon as you can, and mark the day on your calendar. Thanks! -Mike Deal, SNF From mtang at stanford.edu Thu Mar 15 16:01:04 2007 From: mtang at stanford.edu (Mary Tang) Date: Thu, 15 Mar 2007 16:01:04 -0700 Subject: Warning: PLEASE CLEANUP after yourselves, or.... Message-ID: <45F9D030.9000805@stanford.edu> Labmembers: Please remember, the SNF is a shared lab and everyone must do his or her part to keep this a clean, safe, and productive place to work. As many old-timers have noted, the lab seems to be getting increasingly messy. This is especially evident in the litho area and wet benches, where chemicals have been left unattended, chucks and hot plates are left coated with resist, empty resist bottles have been left on the floor, used wipes left everywhere, optical resist at the ebeam bench, etc. (And of course, the ammonium fluoride crystals found at several wet benches in the white area earlier this month.) At the very least, these are annoying to others; at worst, they present safety hazards to your fellow lab and staff members. And, I hope that everyone would prefer that staff address training, process, and equipment issues rather than cleaning up after others. Remember, cleanliness (and safety!) is EVERYONE?S responsibility! ?But it was that way when I found it, so I left it? is a lame excuse. When you see something, clean it up if you feel safe doing so; if not, report the situation to staff. And when you see someone else leaving a mess, remind them of their responsibility to you and the rest of the lab. *So, here is the warning:** * Starting Monday, for one week SNF staff will sweep the litho area and wet bench areas twice a day... if there is a mess, we will assign cleanup or ?community service? tasks to the guilty party ? and if we cannot determine who it is (often the case) then tasks will be assigned to EVERYONE who was enabled or working in the area at that time. We apologize for any inconvenience this will cause, but understand that we have little choice if we want to improve matters. Not that I don?t believe anyone does this intentionally, but I do think that we?ve got a lot of people with deadlines and a lot of new people in the lab ? under these conditions, it?s very easy to become careless... And we constantly need to remind ourselves and each other that we all are part of the same lab. So, as they say at Burning Man, ?leave no trace...? (other than Coral and logsheets, of course.) Thanks for your attention ? Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From ratiug at stanford.edu Thu Mar 15 17:42:51 2007 From: ratiug at stanford.edu (Ching-Huang Lu) Date: Thu, 15 Mar 2007 17:42:51 -0700 Subject: Ph.D. Dissertation Defense (March 20th) -- Ching-Huang Lu Message-ID: <001901c76764$06d71d20$153342ab@ratiug> " Bilayer Metal Gate Electrodes with Tunable Work Function: Behavior, Mechanism, and Device Characteristics" Ching-Huang Lu Department of Materials Science and Engineering Advisor: Prof. Yoshio Nishi Date: Tuesday, March 20th, 2007 Time: 10AM (Refreshments served at 09:45 AM) Place: Packard 101 Abstract: To eliminate poly depletion and to reduce gate leakage current, metal gate/high-k dielectric structures are needed for future CMOS technology. However, it is challenging to engineer the work function of metal gate electrodes and to integrate them with high-k dielectrics. A metal bilayer structure has the ability to adjust the gate work function by varying the bottom layer thickness. In this work, I will discuss this unique work function behavior, investigate the possible mechanisms, and apply this structure to MOSFET devices with high-k dielectrics. The work function of bilayer metal gates exhibits a gradual transition of the work function as the bottom layer thickness increases from 0 to 6-10nm. With properly selected metal pairs, bilayer metal gates are capable of tuning the work function across the entire Si band edge. The work function tuning behavior is seen for many metal systems and on both SiO2 and high-k dielectrics. Several possible mechanisms for the work function behavior were investigated, including carrier redistribution, non-uniform thin film deposition, and thermally-activated metal/metal reaction and interdiffusion. Compositional and the electrical analysis of gate stacks were performed to understand the work function behavior before and after annealing. The results point to a diffusion mechanism that saturates after an initial annealing. Besides the ability to tune the work function, the thin bottom layers can act as buffer/etch-stop layers. In contrast to the traditional dual metal gate process, gate dielectrics can be protected from possible damage or contamination by employing selective etching of one top metal layer from the thin bottom metal layer. This integration scheme was demonstrated to achieve dual work function metal gates on high-k dielectrics by utilizing bilayer metal electrodes and a selective metal wet etch process. Furthermore, gate-last MOSFETs with bilayer metal gate were fabricated to investigate device characteristics including the threshold voltage controllability and the mobility behavior. -------------- next part -------------- An HTML attachment was scrubbed... URL: From hsanda at stanford.edu Thu Mar 15 18:03:17 2007 From: hsanda at stanford.edu (Hiroyuki Sanda) Date: Thu, 15 Mar 2007 17:03:17 -0800 Subject: PhD Dissertation Defense (March 21) Hiroyuki Sanda Message-ID: <1174006997.45f9ecd57f342@webmail.stanford.edu> Ph.D. Oral Examination Si nanocrystal devices for electronics and photonics Hiroyuki Sanda Department of Electrical Engineering Adviser: Professor Yoshio Nishi Date: Wednesday, March 21nd, 2007 Time: 10:00am (Refreshments at 9:45am) Location: CIS-X Auditorium Abstract: Scaling traditional interconnects of VLSI chips presents various challenging issues, including fabrication issues and electrical parasitic issues. Especially, long Cu interconnects suffer from excessive power dissipation and large RC delay. On-chip optical interconnects are one of promising solution, because the optical communication through fibers does not generate any resistive joule loss or cause RC delay. The most challenging device to realize optical interconnection is a CMOS compatible light emitter, because bulk silicon is an indirect bandgap semiconductor. In addition, the optical interconnection layer that includes light emitting and receiving devices, waveguides, and controlling circuits should be fabricated on processing layers, because these optical devices consume substantial area. In the first part of the talk, we will discuss nanocrystal silicon (nc-Si) embedded in SiO2 as a light emitter, since silicon is quasi-direct bandgap material when its size is less than 5nm. nc-Si was fabricated by co-sputtering from Si and SiO2 targets, followed by annealing at 1100 ??C to make nanocrystals. Two surface terminating annealings, high pressure water vapor annealing (HWA), and forming gas annealing (FGA) were selected. Optical and material characterizations after HWA and FGA were compared to analyze differences. We will demonstrate the enhancement of the photoluminescence (PL) intensity by a factor of 3 after HWA as well as FGA, suggesting efficient termination of dangling bonds in the nc-Si. We will also demonstrate a blue shift of the peak positions of the PL spectrums after HWA. The possible mechanism of the modification of the PL spectrums will also be discussed. In the second part of the talk, we will talk about a proposed device layer transfer technology with porous silicon, which is applicable to the fabrication of the 3D-optical interconnect layer on the existing device layers. A bulk wafer was anodically etched to make porous silicon, followed by silicon epitaxial growth on the porous silicon. Conventional CMOS devices were fabricated on this epitaxial layer. In the final step, the device layer was transferred to a plastic substrate with grinding as a thinning process. We have found that the CMOS characteristics with porous silicon are comparable with those without porous silicon. We will also demonstrate that no degradation of the CMOS electrical characteristics occurs during transfer, suggesting that the porous silicon transfer technology is suitable for fabricating 3D-ICs, as well as applications such as flexible ICs. From gthareja at stanford.edu Sun Mar 18 19:08:56 2007 From: gthareja at stanford.edu (Gaurav Thareja) Date: Sun, 18 Mar 2007 18:08:56 -0800 Subject: water in PRS1000 and PRX127 Message-ID: <1174270136.45fdf0b8beacd@webmail.stanford.edu> classic case of bench abuse bench abuse by previous user. they used the D/R (w/o enabling the bench) badly, and water was all over the bench and inside PRX127 and PRS1000. I changed PRS 1000 since I had to use it and cleaned the bench. next user please change PRX127 thanks -gaurav PS. Water is a no-no in PRX127 and PRS1000. -- Gaurav Thareja Graduate Student Solid State Electronics Electrical Engineering Stanford University 650-704-1029 (cell) 650-497-3556 (home) From nishiy at stanford.edu Mon Mar 19 10:00:34 2007 From: nishiy at stanford.edu (Yoshio Nishi) Date: Mon, 19 Mar 2007 10:00:34 -0700 Subject: acknowledging SNF Message-ID: <000401c76a48$1c5ee880$961142ab@it.win.stanford.edu> Dear Labmembers: We will need to prepare for the next 5 year renewal of NNIN. One of the important aspects for the renewal is how SNF is contributing to users for their research, which can be measured by the number of papers coming out of SNF users. When you publish a paper, please be sure to acknowledge SNF and the support of the National Science Foundation with the following statement: "Work was performed in part at the Stanford Nanofabrication Facility of NNIN supported by the National Science Foundation under Grant ECS-9731293." When the paper is published, please send a copy of the citation to John Shott, Paul Rissman and Mary Tang. Thank you, Yoshio Nishi From izuleta at stanford.edu Mon Mar 19 11:38:47 2007 From: izuleta at stanford.edu (Ignacio A. Zuleta) Date: Mon, 19 Mar 2007 11:38:47 -0700 Subject: Phosphor coating in the bay area Message-ID: <000c01c76a55$d4e880c0$487c40ab@izuletaoffice> Hi All, I have a question, does anyone know of a facility that does phosphor + ITO or phosphor + Al (1um) on glass coatings here in the bay area? I am looking to revitalize a phosphor screen that has developed a couple of dark spots thanks to a spark, but would like to upgrade to P-47 phosphor from P-20 as well. I would appreciate any tips you can give me. Thanks, -ignacio -------------- next part -------------- An HTML attachment was scrubbed... URL: From rissman at stanford.edu Mon Mar 19 14:32:44 2007 From: rissman at stanford.edu (Paul Rissman) Date: Mon, 19 Mar 2007 14:32:44 -0700 Subject: Spring Adcom slide review Message-ID: <200703192132.l2JLWjA7031117@smtp-roam.Stanford.EDU> Hi All, I will reprise the slides I showed today at the Spring Adcom meeting on Thursday, March 22nd 4 pm CISX 101 Everyone is welcome. Paul Rissman From ratiug at stanford.edu Mon Mar 19 14:30:38 2007 From: ratiug at stanford.edu (Ching-Huang Lu) Date: Mon, 19 Mar 2007 14:30:38 -0700 Subject: Reminder: Ph.D. Dissertation Defense (Tomorrow, 10am, Packard 101) -- Ching-Huang Lu Message-ID: <003201c76a6d$d6db6330$3da20c80@ratiug> " Bilayer Metal Gate Electrodes with Tunable Work Function: Behavior, Mechanism, and Device Characteristics" Ching-Huang Lu Department of Materials Science and Engineering Advisor: Prof. Yoshio Nishi Date: Tuesday, March 20th, 2007 Time: 10AM (Refreshments served at 09:45 AM) Place: Packard 101 Abstract: To eliminate poly depletion and to reduce gate leakage current, metal gate/high-k dielectric structures are needed for future CMOS technology. However, it is challenging to engineer the work function of metal gate electrodes and to integrate them with high-k dielectrics. A metal bilayer structure has the ability to adjust the gate work function by varying the bottom layer thickness. In this work, I will discuss this unique work function behavior, investigate the possible mechanisms, and apply this structure to MOSFET devices with high-k dielectrics. The work function of bilayer metal gates exhibits a gradual transition of the work function as the bottom layer thickness increases from 0 to 6-10nm. With properly selected metal pairs, bilayer metal gates are capable of tuning the work function across the entire Si band edge. The work function tuning behavior is seen for many metal systems and on both SiO2 and high-k dielectrics. Several possible mechanisms for the work function behavior were investigated, including carrier redistribution, non-uniform thin film deposition, and thermally-activated metal/metal reaction and interdiffusion. Compositional and the electrical analysis of gate stacks were performed to understand the work function behavior before and after annealing. The results point to a diffusion mechanism that saturates after an initial annealing. Besides the ability to tune the work function, the thin bottom layers can act as buffer/etch-stop layers. In contrast to the traditional dual metal gate process, gate dielectrics can be protected from possible damage or contamination by employing selective etching of one top metal layer from the thin bottom metal layer. This integration scheme was demonstrated to achieve dual work function metal gates on high-k dielectrics by utilizing bilayer metal electrodes and a selective metal wet etch process. Furthermore, gate-last MOSFETs with bilayer metal gate were fabricated to investigate device characteristics including the threshold voltage controllability and the mobility behavior. -------------- next part -------------- An HTML attachment was scrubbed... URL: From vigneshg at stanford.edu Tue Mar 20 11:25:39 2007 From: vigneshg at stanford.edu (Vignesh Gowrishankar) Date: Tue, 20 Mar 2007 11:25:39 -0700 Subject: Dessis (Sentaurus) help Message-ID: <6.2.5.6.2.20070320111828.0470beb0@stanford.edu> Hi All - Dessis-users and Harris-group people in particular, I am working with Prof. McGehee in the Materials Science Dept. I would like to model a small part of my nanostructured solar cells using a 2D device simulator such as Dessis (Sentaurus). I have the manuals, but I actually don't know how to get the software started and where to run it from etc., let alone further details. Depending on how much time any of you Sentaurus users may have, I would greatly appreciate it if you could: a) show me how to get the software going - this shouldn't take more than a few minutes. b) give me a quick tutorial - will take a little longer... and depends on your availability. Thanks in advance, Vignesh. From hsanda at stanford.edu Tue Mar 20 11:41:33 2007 From: hsanda at stanford.edu (Hiroyuki Sanda) Date: Tue, 20 Mar 2007 11:41:33 -0700 Subject: reminder:PhD Dissertation Defense (tomorrow) Hiroyuki Sanda Message-ID: <1174416093.46002adddd4df@webmail.stanford.edu> Ph.D. Oral Examination Si nanocrystal devices for electronics and photonics Hiroyuki Sanda Department of Electrical Engineering Adviser: Professor Yoshio Nishi Date: Wednesday, March 21nd, 2007 Time: 10:00am (Refreshments at 9:45am) Location: CIS-X Auditorium Abstract: Scaling traditional interconnects of VLSI chips presents various challenging issues, including fabrication issues and electrical parasitic issues. Especially, long Cu interconnects suffer from excessive power dissipation and large RC delay. On-chip optical interconnects are one of promising solution, because the optical communication through fibers does not generate any resistive joule loss or cause RC delay. The most challenging device to realize optical interconnection is a CMOS compatible light emitter, because bulk silicon is an indirect bandgap semiconductor. In addition, the optical interconnection layer that includes light emitting and receiving devices, waveguides, and controlling circuits should be fabricated on processing layers, because these optical devices consume substantial area. In the first part of the talk, we will discuss nanocrystal silicon (nc-Si) embedded in SiO2 as a light emitter, since silicon is quasi-direct bandgap material when its size is less than 5nm. nc-Si was fabricated by co-sputtering from Si and SiO2 targets, followed by annealing at 1100 ??C to make nanocrystals. Two surface terminating annealings, high pressure water vapor annealing (HWA), and forming gas annealing (FGA) were selected. Optical and material characterizations after HWA and FGA were compared to analyze differences. We will demonstrate the enhancement of the photoluminescence (PL) intensity by a factor of 3 after HWA as well as FGA, suggesting efficient termination of dangling bonds in the nc-Si. We will also demonstrate a blue shift of the peak positions of the PL spectrums after HWA. The possible mechanism of the modification of the PL spectrums will also be discussed. In the second part of the talk, we will talk about a proposed device layer transfer technology with porous silicon, which is applicable to the fabrication of the 3D-optical interconnect layer on the existing device layers. A bulk wafer was anodically etched to make porous silicon, followed by silicon epitaxial growth on the porous silicon. Conventional CMOS devices were fabricated on this epitaxial layer. In the final step, the device layer was transferred to a plastic substrate with grinding as a thinning process. We have found that the CMOS characteristics with porous silicon are comparable with those without porous silicon. We will also demonstrate that no degradation of the CMOS electrical characteristics occurs during transfer, suggesting that the porous silicon transfer technology is suitable for fabricating 3D-ICs, as well as applications such as flexible ICs. From bkyen at yahoo.com Tue Mar 20 22:27:38 2007 From: bkyen at yahoo.com (Bing K Yen) Date: Tue, 20 Mar 2007 22:27:38 -0700 (PDT) Subject: recommendation for Ge wafer vendor Message-ID: <234950.98461.qm@web34610.mail.mud.yahoo.com> Dear Labmembers: can anyone recommend a vendor who sells 1", 2", or larger Ge wafers? Thanks, Bing ____________________________________________________________________________________ Expecting? Get great news right away with email Auto-Check. Try the Yahoo! Mail Beta. http://advision.webevents.yahoo.com/mailbeta/newmail_tools.html From James.Q.Liu at jdsu.com Wed Mar 21 09:44:00 2007 From: James.Q.Liu at jdsu.com (James Q. Liu) Date: Wed, 21 Mar 2007 09:44:00 -0700 Subject: recommendation for Ge wafer vendor In-Reply-To: <234950.98461.qm@web34610.mail.mud.yahoo.com> Message-ID: <0FC4C1B93D218E428D20BFCB9424D5D20388D986@SJEXCH02.ds.jdsu.net> You can try Wafer World, Inc in FL. The contact person is Dianna, 561-842-4441. Her email address is dianna at waferworld.com AXT in Fremont is another good source. You can talk to Lisa Tan @ 510-226-4352. Good luck, James > -----Original Message----- > From: Bing K Yen [mailto:bkyen at yahoo.com] > Sent: Tuesday, March 20, 2007 10:28 PM > To: labmembers at snf.stanford.edu > Subject: recommendation for Ge wafer vendor > > Dear Labmembers: can anyone recommend a vendor who > sells 1", 2", or larger Ge wafers? Thanks, Bing > > > > ________________________________________________________________________ __ > __________ > Expecting? Get great news right away with email Auto-Check. > Try the Yahoo! Mail Beta. > http://advision.webevents.yahoo.com/mailbeta/newmail_tools.html From rcrane at stanford.edu Thu Mar 22 08:56:16 2007 From: rcrane at stanford.edu (Dick Crane) Date: Thu, 22 Mar 2007 08:56:16 -0700 Subject: New employee Gary Sosa Message-ID: <4602A720.9010606@stanford.edu> Labmembers, I would like to introduce you to our newest SNF staff member, Gary Sosa. He will be working in the litho area as the Lithography Equipment Engineer. Gary comes to us from a employment history that includes National Semiconductor, Honeywell Electronic Materials, Cree Crop, and GE Industrial, sensors division. He has extensive experience on SVG tracks, Ultratechs, Susses, ASMLs, and other litho tools. His office is in CIS155 and his phone number is 5-1685. When you see Gary in Litho, please stop and take a moment to welcome him on-board. Thanks, Dick From tberg at stanford.edu Thu Mar 22 10:21:53 2007 From: tberg at stanford.edu (Ted Berg) Date: Thu, 22 Mar 2007 10:21:53 -0700 Subject: Image capture on 4160 Message-ID: <200703221721.l2MHLwb5014891@smtp-roam.Stanford.EDU> Hello all, Well the new image capture for the 4160 is installed and should be available for use later today or tomorrow. The install was relatively painless and the images so far look quite good. The computer (thanks Mary) is on the small table near the load chamber. let us know if this is too awkward. The images are calibrated . Hopefully this will prove to be a valuable tool. I have attached photos of the sample grid 25u squares ted -------------- next part -------------- A non-text attachment was scrubbed... Name: PCI-Install-03-21-07d.TIF Type: image/tiff Size: 307686 bytes Desc: not available URL: From vigneshg at stanford.edu Thu Mar 22 12:06:05 2007 From: vigneshg at stanford.edu (Vignesh Gowrishankar) Date: Thu, 22 Mar 2007 12:06:05 -0700 Subject: How to run Mdraw on elaine (etc.)? Message-ID: <6.2.5.6.2.20070322120341.06655100@stanford.edu> Hi All, I need to make a 2D device. I have been told MDraw is the way to go, but have not been able to get in running (remotely) off elaine (and bramble etc.). Apparently, some others are experiencing a similar problem. Can somebody who has recently used MDraw please let me (and others interested) know how to get MDraw to work. Thanks, Vignesh. From vigneshg at stanford.edu Thu Mar 22 13:16:38 2007 From: vigneshg at stanford.edu (Vignesh Gowrishankar) Date: Thu, 22 Mar 2007 13:16:38 -0700 Subject: Clarification and problem starting MDraw... Message-ID: <6.2.5.6.2.20070322131443.0665beb0@stanford.edu> Hi All, I had sent an email earlier, this is just to clarify that message... I am using VNC as an X-terminal. It does not seem as if not being able to display MDraw is the problem. MDraw does not start even when I use VNC. I have included the following line to my .cshrc - "source /afs/ir/class/ee/synopsys/tcad/tcad.cshrc". I am trying (learning to anyway) run Sentaurus, which needed that line in the .cshrc. Those programs are running, but Mdraw is not. When I type mdraw at the command prompt, this is the error message I get: "mdraw execution failed for /afs/ir/class/ee/synopsys/tcad/Y_2006.06/tcad/current/amd64/bin/mdraw". I am not sure if my licence is not set up properly... actually I have no idea what the problem is. Any thoughts? Thanks, Vignesh. From raneeyoo at stanford.edu Thu Mar 22 15:20:56 2007 From: raneeyoo at stanford.edu (Kyeongran Yoo) Date: Thu, 22 Mar 2007 15:20:56 -0700 Subject: SOI wafer vender? Message-ID: <1174602056.4603014883657@webmail.stanford.edu> Hello! I am looking for SOI wafer venders. If you have any recommendations for good vendors for SOI wafers, please let me know. Thank you very much and have a nice day! best, Kyeongran Yoo From rissman at stanford.edu Thu Mar 22 16:01:22 2007 From: rissman at stanford.edu (Paul Rissman) Date: Thu, 22 Mar 2007 16:01:22 -0700 Subject: Spring Adcom slide review Message-ID: <200703222301.l2MN1Wu5020853@smtp-roam.Stanford.EDU> reminder - NOW -------------------------------------------------- Hi All, I will reprise the slides I showed today at the Spring Adcom meeting on Thursday, March 22nd 4 pm CISX 101 Everyone is welcome. Paul Rissman From yves-alain.peter at polymtl.ca Thu Mar 22 17:48:13 2007 From: yves-alain.peter at polymtl.ca (Yves-Alain Peter) Date: Thu, 22 Mar 2007 20:48:13 -0400 Subject: SOI wafer vender? In-Reply-To: <1174602056.4603014883657@webmail.stanford.edu> References: <1174602056.4603014883657@webmail.stanford.edu> Message-ID: <460323CD.7070305@polymtl.ca> Hi all, We have been quite happy with Ultrasil (http://www.ultrasil.com/) recently. Best, Yves-Alain **************************************** Yves-Alain Peter Assistant Professor Micro and Nano Systems Laboratory Engineering Physics Department Ecole Polytechnique de Montr?al P.O. Box 6079, Station Centre-Ville Montr?al, Qu?bec H3C 3A7 CANADA Phone : + 1 514 340 4711 ext. 3100 Fax : + 1 514 340 3218 Cell : + 1 514 465 SMEM yves-alain.peter at polymtl.ca http://www.polymtl.ca/mems/en/ **************************************** Kyeongran Yoo wrote: > Hello! > > I am looking for SOI wafer venders. If you have any recommendations for > good vendors for SOI wafers, please let me know. > Thank you very much and have a nice day! > > best, > Kyeongran Yoo > From knozawa at stanford.edu Thu Mar 22 18:21:37 2007 From: knozawa at stanford.edu (Katsuya NOZAWA) Date: Thu, 22 Mar 2007 18:21:37 -0700 Subject: SOI wafer vender? In-Reply-To: <1174602056.4603014883657@webmail.stanford.edu> References: <1174602056.4603014883657@webmail.stanford.edu> Message-ID: <001e01c76ce9$9aefb910$c11b40ab@panasonic> Hi Kyeongran, There are two types in SOI wafer. One is thin type, the other is thick type. In thin type, device layer thickness is less than 1.5 micro meter, typically less than 200nm. In thick type, device layer thickness is more than 2 micro meter. Fabrication methods are quite different each other, so one wafer vender makes only one type. It depends on device structure which type you should choose. Most of fast SOI transistor & photonic crystal require thin type. Some MEMS requires thick type. If you need thick type, Ultrasil is good supplier. But they don't sell thin type. Soitec is a reliable supplier for thin type SOI wafers. http://www.soitec.com/ Sincerely yours, ----- Katsuya Nozawa Visiting scholar in Yamamoto Group, Ginzton Laboratory, Stanford University, Stanford, CA94305, USA Phone: 650-725-9346, Fax: 650-723-5320 E-mail: knozawa at stanford.edu -----Original Message----- From: Kyeongran Yoo [mailto:raneeyoo at stanford.edu] Sent: Thursday, March 22, 2007 3:21 PM To: Labmembers at snf.stanford.edu Subject: SOI wafer vender? Hello! I am looking for SOI wafer venders. If you have any recommendations for good vendors for SOI wafers, please let me know. Thank you very much and have a nice day! best, Kyeongran Yoo From raneeyoo at stanford.edu Thu Mar 22 21:03:34 2007 From: raneeyoo at stanford.edu (Kyeongran Yoo) Date: Thu, 22 Mar 2007 21:03:34 -0700 Subject: SOI wafer vender? Message-ID: <1174622614.46035196b549c@webmail.stanford.edu> Dear Katsuya, Thank you for your kind email. I am looking for thin SOI wafers like 400nm BOX and 200nm SOI. In my case, Ultrasil might not be a choice. Thank you so much again. best, Kyeongran Quoting Katsuya NOZAWA : > Hi Kyeongran, > There are two types in SOI wafer. One is thin type, the other is thick > type. In thin type, device layer thickness is less than 1.5 micro meter, > typically less than 200nm. In thick type, device layer thickness is more > than 2 micro meter. Fabrication methods are quite different each other, > so > one wafer vender makes only one type. > > It depends on device structure which type you should choose. > Most of fast SOI transistor & photonic crystal require thin type. Some > MEMS > requires thick type. > > If you need thick type, Ultrasil is good supplier. But they don't sell > thin > type. > > Soitec is a reliable supplier for thin type SOI wafers. > http://www.soitec.com/ > > Sincerely yours, > ----- > Katsuya Nozawa > > Visiting scholar in Yamamoto Group, Ginzton Laboratory, > Stanford University, Stanford, CA94305, USA > > Phone: 650-725-9346, Fax: 650-723-5320 > E-mail: knozawa at stanford.edu > -----Original Message----- > From: Kyeongran Yoo [mailto:raneeyoo at stanford.edu] > Sent: Thursday, March 22, 2007 3:21 PM > To: Labmembers at snf.stanford.edu > Subject: SOI wafer vender? > > Hello! > > I am looking for SOI wafer venders. If you have any recommendations for > good vendors for SOI wafers, please let me know. > Thank you very much and have a nice day! > > best, > Kyeongran Yoo > > From mahnaz at stanford.edu Fri Mar 23 14:03:17 2007 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 23 Mar 2007 14:03:17 -0700 Subject: Bond Jig Message-ID: <46044095.4090102@stanford.edu> Hello all, I had designed a jig to do the wafer bonding for sts etcher. I am not able to locate it, if you have borrowed it Please bring it back- one user has a immediate use for it. mahnaz From mdeal at stanford.edu Mon Mar 26 14:51:59 2007 From: mdeal at stanford.edu (Michael Deal) Date: Mon, 26 Mar 2007 14:51:59 -0700 Subject: SNF and Community Day In-Reply-To: <6.2.5.6.2.20070315124125.01d3b4c8@stanford.edu> References: <6.2.5.6.2.20070315124125.01d3b4c8@stanford.edu> Message-ID: <6.2.5.6.2.20070326144916.01d98630@stanford.edu> SNF labmembers, Wc can still use a few more volunteers for SNF's participation in Stanford's Community Day (April 15). The description is below. Please email me if you can help. (Attendance at the planning meeting, with pizza, is not required for you to help on the actual day.) Thanks. -Mike Deal, SNF p.s. thanks to those of you who have already said they can help At 12:42 PM 3/15/2007, Michael Deal wrote: >SNF labmembers, > This year, SNF will once again participate in Stanford > University's "Community Day." This is where adults and children > from the neighboring cities are invited to Stanford on a Spring > Sunday to visit the campus, and dozens of university organizations > put on displays and demonstrations. Two years ago - Community Day > is now held every other year - we had a very successful and fun day > in which we taught the community about nanotechnology. We had > posters, free handouts (ruler/magnifying glasses), microscope demos > (where they could see structures built in our lab), and the very > popular "be a junior nanoscientist (where kids put on a cleanroom > suit, got the photo taken, and got a nanoscientist certificate with > their name and picture on it.) We also gave tours of the cleanroom > every few hours. > Based on the success of previous years, and the fact that only > ~30% of Community Day attendees are repeaters from before, we plan > on doing basically the same thing as before. In addition, the > Stanford Nanocharacterisation Laboratory (SNL) will join us, > participating in the microscope activity and offering a tour of > their facility. And this year our exhibit area will be right in > front of CIS, not by the Hoover tower like last time. >As before, I'd like to invite both staff and SNF labmembers to >volunteer. The more people who participate, the more fun it will be >for all of us. Community Day will be Sunday, April 15 from 10 am >to 4pm. You can work part or all of it (we'll need a few here at >9am to help set up). We have lots of fun, and free lunch as >well. We'll have a planning meeting some time before the event, >with pizza, but it isn't necessary to attend that in order to help >out on the actual day. > So if you are interested in helping out and participating in > SNF's nano activities at Community Day (April 15), please reply to > me as soon as you can, and mark the day on your calendar. Thanks! > -Mike Deal, SNF > From sanjah at stanford.edu Mon Mar 26 15:44:16 2007 From: sanjah at stanford.edu (Sanja Hadzialic) Date: Mon, 26 Mar 2007 15:44:16 -0700 Subject: missing chips Message-ID: <1174949056.46084cc09ca07@webmail.stanford.edu> Dear all, My chips (and tweezers!) went missing from the top of wbsolvent today, sometimes between noon and 3 pm. They were in a petri dish and my name and phone # is on the lid. If you know what happened to them please let me know. These chips are VERY important to me. Sanja :~) From mbaran at stanford.edu Thu Mar 29 09:28:19 2007 From: mbaran at stanford.edu (Maureen Baran) Date: Thu, 29 Mar 2007 08:28:19 -0800 Subject: Camera found Message-ID: <20070329162818.C8C9B4C377@smtp2.stanford.edu> A camera was found in or around the lab. If you have misplaced your camera please come by my cubicle and tell me all the details you know about your camera in order to claim it. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Thu Mar 29 10:17:36 2007 From: mbaran at stanford.edu (Maureen Baran) Date: Thu, 29 Mar 2007 09:17:36 -0800 Subject: Hardback Notebook found in the Lab Message-ID: <20070329171735.DB0024C389@smtp2.stanford.edu> A hardback notebook has been found in the lab. If this is yours please come to my cubicle and retrieve it. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From erik.anderson at stanford.edu Thu Mar 29 19:08:18 2007 From: erik.anderson at stanford.edu (Erik Anderson) Date: Thu, 29 Mar 2007 19:08:18 -0700 Subject: sub-pico amp current source Message-ID: <460C7112.7040308@stanford.edu> Hi all, I am looking to borrow a sub-picoAmp current source to do some measurements. Does anyone have one in their lab? Preferably, the instrument could source currents from 10 femtoAmps to 10 nanoAmps. I don't necessarily need to bring your instrument to my lab since I could easily bring my device to yours. Thanks. Erik