PhD Dissertation Defense (March 21) Hiroyuki Sanda

Hiroyuki Sanda hsanda at stanford.edu
Thu Mar 15 18:03:17 PDT 2007


Ph.D. Oral Examination
Si nanocrystal devices for electronics and photonics
 Hiroyuki Sanda
Department of Electrical Engineering
Adviser: Professor Yoshio Nishi
Date: Wednesday, March 21nd, 2007
Time: 10:00am (Refreshments at 9:45am)
Location: CIS-X Auditorium
Abstract:
     Scaling traditional interconnects of VLSI chips presents various
challenging issues, including fabrication issues and electrical parasitic
issues.  Especially, long Cu interconnects suffer from excessive power
dissipation and large RC delay.  On-chip optical interconnects are one of
promising solution, because the optical communication through fibers does
not generate any resistive joule loss or cause RC delay.  The most
challenging device to realize optical interconnection is a CMOS compatible
light emitter, because bulk silicon is an indirect bandgap semiconductor. 
In addition, the optical interconnection layer that includes light emitting
and receiving devices, waveguides, and controlling circuits should be
fabricated on processing layers, because these optical devices consume
substantial area.
     In the first part of the talk, we will discuss nanocrystal silicon
(nc-Si) embedded in SiO2 as a light emitter, since silicon is quasi-direct
bandgap material when its size is less than 5nm.  nc-Si was fabricated by
co-sputtering from Si and SiO2 targets, followed by annealing at 1100 「ェC
to make nanocrystals.  Two surface terminating annealings, high pressure
water vapor annealing (HWA), and forming gas annealing (FGA) were selected.
 Optical and material characterizations after HWA and FGA were compared to
analyze differences.  We will demonstrate the enhancement of the
photoluminescence (PL) intensity by a factor of 3 after HWA as well as FGA,
suggesting efficient termination of dangling bonds in the nc-Si.  We will
also demonstrate a blue shift of the peak positions of the PL spectrums
after HWA.  The possible mechanism of the modification of the PL spectrums
will also be discussed.
     In the second part of the talk, we will talk about a proposed device
layer transfer technology with porous silicon, which is applicable to the
fabrication of the 3D-optical interconnect layer on the existing device
layers.  A bulk wafer was anodically etched to make porous silicon,
followed by silicon epitaxial growth on the porous silicon.  Conventional
CMOS devices were fabricated on this epitaxial layer.  In the final step,
the device layer was transferred to a plastic substrate with grinding as a
thinning process.  We have found that the CMOS characteristics with porous
silicon are comparable with those without porous silicon.  We will also
demonstrate that no degradation of the CMOS electrical characteristics
occurs during transfer, suggesting that the porous silicon transfer
technology is suitable for fabricating 3D-ICs, as well as applications such
as flexible ICs.




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