From tariq_haniff at yahoo.com Fri Aug 1 09:56:18 2008 From: tariq_haniff at yahoo.com (Tariq Haniff) Date: Fri, 1 Aug 2008 09:56:18 -0700 (PDT) Subject: Ni Electroplating vendor Message-ID: <589187.54192.qm@web54107.mail.re2.yahoo.com> Members, I am looking for a vendor (preferably local) that can plate ~5um of Ni (composition is flexible). Does anyone have such a source? Thanks in advance -Tariq From mtang at stanford.edu Fri Aug 1 12:38:25 2008 From: mtang at stanford.edu (Mary Tang) Date: Fri, 01 Aug 2008 12:38:25 -0700 Subject: A few general announcements... Message-ID: <48936631.6050905@stanford.edu> Greetings labmembers -- Just a few general announcements -- - Those interested should check out the new job postings on the SNF website -- http://snf.stanford.edu/Affiliates/Jobs.html - Facilities will be working on Transfer Fan #4 Monday morning (8/4). There will be no laminar flow over the following equipment: alphastep/ellipsometer/p2, wbgaas/wbgen2/fga2/tylans1-4, epi2/AG4100/AG4108. - Reminder that the Labmembers' meeting has been postponed to Friday, Aug. 8, at 1 pm in the CISX Auditorium. - The Litho and Etch Quality Circles will meet Wednesday afternoon from 1-2 and 2-3 pm in CIS 201. Labmembers are welcome. Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Fri Aug 1 14:24:15 2008 From: mtang at stanford.edu (Mary Tang) Date: Fri, 01 Aug 2008 14:24:15 -0700 Subject: Learn to save someone's life: Take a CPR/AED class! Message-ID: <48937EFF.2070407@stanford.edu> Greetings labmembers: On Thursday, August 21, we?ve arranged for a First Aid/CPR/AED class to be offered here. This 8-hour course will cover basic first aid and emergency procedures that you could use to save someone?s life. This course will also cover Cardio-Pulmonary Resuscitation (CPR) and use of the Automated External Defibrillator (AED) ? which are awfully handy skills to know, when someone?s heart stops. If you had First Aid a long time ago, it?s well worth doing again because the recommended practices have changed a LOT. Also, we are fortunate to have TWO AED systems in CIS/CISX, so it?s handy to know how to use them. One statistic is that use of CPR alone results in a survival rate of a few percent. Using an AED within 3 minutes of heart failure has a survival rate of 75% or greater. The class will be held on August 21, from 8 am - 4 pm. Completion of this course gives you a certification that is valid for two years. The class is open to building occupants and active labmembers. If you are interested in registering, please get in touch with me. Thanks for your attention! Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From baylor.triplett at gmail.com Fri Aug 1 14:32:40 2008 From: baylor.triplett at gmail.com (Baylor Triplett) Date: Fri, 01 Aug 2008 14:32:40 -0700 Subject: FW: Die saw at Stanford or elsewhere In-Reply-To: <113F6EB3099A9945ACB6B6AD8F7A390901F84E51@EXCHANGE0.exponent.com> References: <113F6EB3099A9945ACB6B6AD8F7A390901F84E51@EXCHANGE0.exponent.com> Message-ID: <489380F8.5080205@gmail.com> Jason, While I cannot be certain without trying it, my understanding is the wafer saw that CIS has should be able to cut such materials. Certainly, my colleagues (years ago) used an almost identical wafer saw to cut GGG (or Gadolium Gallium Garnet which is quite hard...probably comparable to titania. Only thing is you should use high blade speed, special blade that works best, and probably shallow multiple cuts to reduce the troublesome blade heating. Kulicke and Sofa could probably give you advice...and you may/may not need a special blade to minimize heating....more likely needed if you have a gummy material on top of the titania such as polyimide or polymerized organics. Do not try to cut all the way through...you want to cut 60% to maybe 80% through and then cleave the remainder. And these numbers are only guesses. The important thing is the cutting is more a function of parameters and blade selection than saw. Of course, allbets are off if CIS won't let you use it for contamination reasons. Talk to Mary Tang. Regards, Baylor Triplett Consulting Professor Jason Fu wrote: > Hi, everyone, > > Is there a die saw in the lab or such service elsewhere in the area > that could be used to cut hard glasses and oxides such as zirconia > and titania? > > Thanks, > > Jason > From ytanster at gmail.com Sat Aug 2 22:52:17 2008 From: ytanster at gmail.com (Mike Tan) Date: Sun, 3 Aug 2008 00:52:17 -0500 Subject: etching oxide Message-ID: <249e3dc70808022252h220dcda6qcefb845fc922a896@mail.gmail.com> Dear Lab members, Does anyone have any experience in using amtetcher to pattern substrate with 200um- 300um micron holes? 1) Using the amtetcher, would the plasma go into the holes and then etch the oxide inside the holes (laterally)? My oxide thickness is about 600nm which takes about 15minutes to etch. The holes that I have are 300um deep with 30um and 100um diameters. I am trying to create a tapered surface with several high aspect ratio (1:30) holes. 2) Does anyone have any wet-etch simulation software that I can try out for free? Thank you very much for your consideration. Sincerely, Mike Tan -------------- next part -------------- An HTML attachment was scrubbed... URL: From cmjha at stanford.edu Mon Aug 4 14:50:38 2008 From: cmjha at stanford.edu (Chandra Mohan Jha) Date: Mon, 4 Aug 2008 14:50:38 -0700 Subject: Chandra Mohan Jha Thesis Defense - 8:08 am Friday, 08/08/08 In-Reply-To: <484ED07F.3060509@stanford.edu> References: <484ED07F.3060509@stanford.edu> Message-ID: <017901c8f67c$226919f0$673b4dd0$@edu> Ph.D. Thesis Oral Examination "Design of Thermally and Mechanically Isolated Ovenized Microresonators" Advisor: Prof. Thomas W. Kenny Date: Friday, Aug 8th Time: 8:08 am (Refreshments beforehand) Venue: CISX-101 (Auditorium) http://campus-map.stanford.edu/index.cfm?ID=04-055 Abstract: Micromechanical resonators are becoming an interesting and viable technology as a replacement for quartz crystals for timing and frequency reference applications. For high precision applications in industry and military, oven controlled resonators are used to compensate for the temperature dependence of resonator frequency. An oven controlled resonator requires a good temperature sensor and an efficient heater (oven). However, an external temperature sensor leads to thermal lag and the ovenization leads to power consumption. This work presents a microresonator based digital temperature sensing technique as well as an efficient local-thermal-isolation method. The microresonator based thermometry results into a lag-free temperature sensor for self temperature compensation suitable for high precision oven control of the resonator. The thermal isolation technique includes the design of an integrated heater with the microresonator such that the mechanical suspension, electrical heating and thermal isolation are provided in a single compact structure. This results in reducing the power consumption by more than 20x and the thermal time constant by more than 50x. Further reduction in power consumption requires analysis of the resonator structure to maintain its mechanical integrity. An improved thermally isolated design using topology optimization will be described. The final design provides both the thermal isolation as well as the mechanical isolation with the overall reduction in power consumption of 40x. Furthermore, these methods are simple enough to implement it into any existing MEMS fabrication process. From mtang at stanford.edu Mon Aug 4 17:52:41 2008 From: mtang at stanford.edu (Mary Tang) Date: Mon, 04 Aug 2008 17:52:41 -0700 Subject: Venture Clinic, Thur. Aug. 14, 2 pm, CIS 101 Message-ID: <4897A459.1090509@stanford.edu> Are you thinking about the possibility of building a startup? Shahin Farshchi, an Associate from Lux Capital, will be moderating a Venture Clinic, which aims to provide an informal forum for researchers interested in brainstorming with a venture capitalist on avenues for commercializing technology, what to expect when starting a new venture. Technical discussions should be limited to what has been already disclosed or published. This will take place on Thursday, August 14, at 2 pm in CIS 101. For more information, contact: Shahin Farshchi, Ph.D. Phone: 925.323.2784 Email: shahin.farshchi at luxcapital.com -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From ytanster at gmail.com Tue Aug 5 11:40:53 2008 From: ytanster at gmail.com (Mike Tan) Date: Tue, 5 Aug 2008 11:40:53 -0700 Subject: spray coater In-Reply-To: <249e3dc70808051138p4a8397dfoee47ee98c4d0e0bb@mail.gmail.com> References: <249e3dc70808051138p4a8397dfoee47ee98c4d0e0bb@mail.gmail.com> Message-ID: <249e3dc70808051140u1cbbe4a4m8d7ee13d55280ff0@mail.gmail.com> Hi Does anyone know any commercial spray coating services for silicon wafers in California? I have some TMAH etched V-groves about 300um deep that I would like to coat them with Shipley 3612 resist. Thank you for your help. Mike -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Tue Aug 5 17:18:00 2008 From: mtang at stanford.edu (Mary Tang) Date: Tue, 05 Aug 2008 17:18:00 -0700 Subject: New Manual Resist Handling Procedures Message-ID: <4898EDB8.3090402@stanford.edu> Hello Photolithographers -- Please be aware of the new handling procedures for manual dispensing of standard resists. Small, easy-to-handle bottles of standard resists are provided for your convenience in the small flammables cabinet next to the wbmiscres/headway2 station (special thanks to Mario, Jim, and Mahnaz!) Please use these bottles for manual dispensing at the headway2 and laurell stations only. Bottles may be hand-carried and used ONLY AT HEADWAY OR LAURELL STATIONS. They must be returned to the cabinet when finished. The standard resists stocked are: SPR 3612, SPR 3617M, SPR 220-7, SPR 220-3, and LOL 2000. Do not place other resists in this cabinet. (Any non-standard resist bottles found here will be removed and discarded.) Be courteous to the next user -- make sure to use care to avoid drips -- and carefully wipe away any that might occur. We trust that these smaller bottles are safer than handling the large one-gallon jugs -- and may save people a trip to the back with the solvent cart. Your Litho Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mbaran at stanford.edu Wed Aug 6 14:21:52 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Wed, 6 Aug 2008 14:21:52 -0700 Subject: Watch was found outside the CIS Building Message-ID: <20080806212152.1046365AA5B@smtp2.stanford.edu> Dear Labmembers and CIS Dwellers, A watch was found outside the CIS building today. If you have misplaced your watch and you think it is yours, please come by my cubicle and be prepared to describe it. Thank you, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mailvv at stanford.edu Wed Aug 6 22:01:47 2008 From: mailvv at stanford.edu (Wei Wang) Date: Wed, 6 Aug 2008 22:01:47 -0700 Subject: Reminder: Wei Wang Ph.D Oral Defense 08/07/2008 (Tomorrow) Message-ID: <222535CB510C40809AA49C7D74E02703@stanford.edu> Ph.D Oral Defense Wei Wang ----- Original Message ----- From: Diane Shankle To: ee-students at lists.stanford.edu Sent: Friday, August 01, 2008 11:59 AM Subject: Ph.D Oral Defense Wei Wang Title: Titanium Oxide Nonvolatile Memory Device and its Application Name: Wei Wang Advisor: Prof. Simon Wong Time: 2pm, Thursday, August 7th, 2008 (refreshments at 1:45pm) Place: CISX Auditorium ---------------------------------------------------------------------------------------------------------- With the memory cost per bit reducing at very aggressive rates, nonvolatile memories (NVM) have seen explosive growth in the last few years in electronic applications such as memory cards, cell phones, and other consumer electronic devices. On the other hand, FLASH as the current mainstream nonvolatile memory, is facing major scaling difficulties due to non-scalability of dielectric and cell to cell interference. While FLASH is predicted to reach its definite limit beyond 22nm, non-charge-storage nonvolatile memories are being researched as alternatives. Resistive switching in transition metal oxide (TMO) thin films, such as TiOx and NiO, has raised great interests for possible applications in nonvolatile memories due to their excellent CMOS process compatibility, promising scalability and low manufacturing cost. One extremely undesirable characteristic of TiOx NVM devices is that all fresh devices have to go through a "forming process" before they can be further switched on and off. The forming process is a high-voltage stress (~2Vdd), which is a major obstacle for widespread adoption in products. We pioneered a fabrication process which allows in-situ deposition of the bottom electrode, metal oxide and top electrode The process has been demonstrated to eliminate high voltage forming in TiOx resistive switching devices. TiOx NVM device can switch in both unipolar and bipolar modes. A novel cross-point structure is built to understand the physics of resistive switching in both modes. Our experiments reveal that unipolar and bipolar switching have different working mechanisms: unipolar switching can be explained by thermal dissolution model, and bipolar switching by local redox reaction model. Conductive filament is destroyed during unipolar switching, but can be reused during bipolar switching, which suggests that bipolar switching may have better endurance. One possible application of TiOx NVM device is nonvolatile SRAM (NVSRAM), a technology seeking to solve the problem of rapidly increasing SRAM leakage power in embedded systems. To reduce SRAM leakage power, we propose a nonvolatile SRAM cell with two back-up nonvolatile memory devices. This novel cell offers non-volatile storage, thus allowing selected blocks of SRAM to be powered down during operation, which completely eliminates their leakage power. There is no area penalty in this approach and only a slight performance penalty of less than 15% is anticipated. It is also shown that power savings resulting from the NVSRAM approach increase with technology scaling, for both high speed and general purpose processors. -------------------------------------------------------------------------------- -- EE students mailing list ee-students at lists.stanford.edu https://mailman.stanford.edu/mailman/listinfo/ee-students -------------- next part -------------- An HTML attachment was scrubbed... URL: From shinbh93 at stanford.edu Thu Aug 7 11:40:19 2008 From: shinbh93 at stanford.edu (Byungha Shin) Date: Thu, 7 Aug 2008 11:40:19 -0700 Subject: etching Al2O3 Message-ID: Dear Labmembers, One of my collaborators try to etch off Al2O3 at the corners of samples (consisting of Al2O3 / InGaAs / InP substrate) for Hall measurements. He found that photo-resist used to define the corners on Al2O3 surface was peeled off during etching by BHF. Has anyone sucessfully done photolithography on Al2O3? If so, what kind of adhesion promotor was used? Also, does anyone know the etch rate of Al2O3 by BHF? Thanks, Byungha -------------- next part -------------- An HTML attachment was scrubbed... URL: From shide_cheng at hotmail.com Thu Aug 7 12:29:24 2008 From: shide_cheng at hotmail.com (shide cheng) Date: Thu, 7 Aug 2008 12:29:24 -0700 Subject: etching Al2O3 In-Reply-To: References: Message-ID: Hi, Byungha, My experience is developer will erode the Al, and Al2O3 during development stage. You may need anther layer to protect them during photo process. Shide From: shinbh93 at stanford.eduTo: labmembers at snf.stanford.eduSubject: etching Al2O3Date: Thu, 7 Aug 2008 11:40:19 -0700 Dear Labmembers, One of my collaborators try to etch off Al2O3 at the corners of samples (consisting of Al2O3 / InGaAs / InP substrate) for Hall measurements. He found that photo-resist used to define the corners on Al2O3 surface was peeled off during etching by BHF. Has anyone sucessfully done photolithography on Al2O3? If so, what kind of adhesion promotor was used? Also, does anyone know the etch rate of Al2O3 by BHF? Thanks, Byungha _________________________________________________________________ Get Windows Live and get whatever you need, wherever you are. Start here. http://www.windowslive.com/default.html?ocid=TXT_TAGLM_WL_Home_082008 -------------- next part -------------- An HTML attachment was scrubbed... URL: From agibby at stanford.edu Thu Aug 7 16:56:58 2008 From: agibby at stanford.edu (Aaron Matthew Gibby) Date: Thu, 7 Aug 2008 16:56:58 -0700 (PDT) Subject: Fwd: Aaron Gibby Orals Abstract In-Reply-To: <1048183316.430721218153411985.JavaMail.root@zm03.stanford.edu> Message-ID: <1544603368.430741218153417972.JavaMail.root@zm03.stanford.edu> ----- Original Message ----- From: "Diane Shankle" To: Sent: Thursday, August 07, 2008 4:20 PM Subject: Aaron Gibby Orals Abstract > > > Title: A Layered Chalcogenide Phase-Change Memory Device > > Name: Aaron Gibby > > Advisor: Prof. S. Simon Wong > > Time: 10:00 am, Monday, August 25th, 2008 (refreshments served at > 9:45 am) > > Place: CIS-X Auditorium, 420 Via Palou > > --------------------------------------------------------------------------------- > > Non-volatile memory (NVM) is the fastest growing sector of the > semiconductor market. With sales growing from $26 billion in 2006 to > more than $64 billion in 2011, there is a large economic incentive to > improve on NVM performance. This has lead to aggressive scaling of > Flash memory, the dominant NVM technology. There are, however, > limitations to the degree that Flash can be scaled, with failure of > the technology predicted around the 22 nm node. > > As a result, research has accelerated in alternative NVM > technologies. Among these, phase-change memory (PCM) shows > particular promise given its small cell size, non-destructive read, > direct overwrite ability, large sensing margin, and fast speed. > Despite these advantages, the requirement for a large (mA - range) > programming current remains the major obstacle to mainstream > implementation for PCM. > > To address this issue, we propose a novel layered structure where the > phase-change material (Ge2Sb2Te5, or GST) is sandwiched between two > other layers (called GST-x layers). With the correct choice of > material, the GST-x layers improve the thermal isolation of the GST, > while reducing the volume of material programmed. This, in turn, > lowers the energy and current required to operate the device. > > After a thorough analysis of GST-x candidates using X-ray > Diffraction, X-ray Photoemission Spectroscopy, Thermal Reflectance > Thermometry, and electrical measurements, GeTe (GT) was chosen to > function as the GST-x film. Single layer GST and multi-layer > GT/GST/GT devices were then fabricated and compared. Analysis was > conducted using a combination of electrical measurements, > transmission electron microscopy and scanning Auger spectroscopy. > > As a result of this analysis, GT/GST/GT devices showed a modest (~2x) > improvement in programming current on the first cycle and a > significant (~40x) improvement on subsequent cycling. Reasons for > this and reliability concerns are discussed. > > -- > EE students mailing list > ee-students at lists.stanford.edu > https://mailman.stanford.edu/mailman/listinfo/ee-students > From mtang at stanford.edu Thu Aug 7 17:23:55 2008 From: mtang at stanford.edu (Mary Tang) Date: Thu, 07 Aug 2008 17:23:55 -0700 Subject: Labmembers' Meeting, Friday, Aug. 8, 1-2 pm, CISX Auditorium Message-ID: <489B921B.9030201@stanford.edu> Greetings Labmembers! Just a reminder that there's a Labmembers' meeting tomorrow (Friday) at 1 pm in the CISX Auditorium. Everyone in the labmember community is welcome. We will cover: general announcements (such as the December shutdown schedule -- start planning that holiday now!); the Quality Circle Roundup; the Project List update (including the tylanbpsg upgrade and EE410); and a solicitation for interested participants to revise and update the SNF contamination policy. Be there and be aware! Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From enwang at MIT.EDU Thu Aug 7 20:20:02 2008 From: enwang at MIT.EDU (Evelyn Wang) Date: Thu, 7 Aug 2008 23:20:02 -0400 Subject: Postdoctoral Opening in MechE Message-ID: <00c301c8f905$a59160e0$f0b422a0$@edu> Postdoctoral Associate Opening Department of Mechanical Engineering, MIT We are seeking a Postdoctoral Associate to assist in the development of an integrated air-cooled pumped heat exchanger. Expertise and experience in the following areas are highly desired: - Design and integration of heat transfer and fluidic systems, i.e., heat pipes, microchannel coolers - Micromachining and nanofabrication - Experimental heat transfer, fluid mechanics, interfacial phenomena, phase-change and two-phase flows - Microfluidics and phase-change in microscale systems The project is highly interdisciplinary and the postdoctoral associate will join a team of faculty, and students in the Departments of Mechanical, Electrical, and Aeronautics and Astronautics Engineering at MIT for the project. Please contact Evelyn Wang (enwang at mit.edu) with a detailed CV and 3-4 references. ------------------------------------------ Evelyn Wang Esther and Harold E. Edgerton Assistant Professor Department of Mechanical Engineering M.I.T. 77 Massachusetts Ave. 3-461B Cambridge, MA 02139 617-324-3311 enwang at mit.edu http://drl.mit.edu -------------- next part -------------- A non-text attachment was scrubbed... Name: MIT-ME-Postdoc Announcement.pdf Type: application/pdf Size: 42538 bytes Desc: not available URL: From baylor.triplett at gmail.com Thu Aug 7 23:35:56 2008 From: baylor.triplett at gmail.com (Baylor Triplett) Date: Thu, 07 Aug 2008 23:35:56 -0700 Subject: etching Al2O3 In-Reply-To: References: Message-ID: <489BE94C.3080000@gmail.com> All, While I do not have experience with attempting this particular process, it is common for Hf or BHF to penetrate photoresist and result in lift off depending on how long the etch solution is applied, and how concentrated the etch solution is in HF or fluoride. One first attempt is to hard bake the resist which substantially improves the adhesion to the substrate. Then the resist is stripped by an aggressive stripper or plasma ashed off. Adhesion promoters also can help. The ultimate solution can be a second layer or bilayer (sometimes called a "hard mask" that can be etched more easily). However, I suggest searching first for published papers in this area to see if there isn't an easy solution. Baylor shide cheng wrote: > Hi, Byungha, > > My experience is developer will erode the Al, and Al2O3 during > development stage. You may need anther layer to protect them during > photo process. > > Shide > > ------------------------------------------------------------------------ > > From: shinbh93 at stanford.edu > To: labmembers at snf.stanford.edu > Subject: etching Al2O3 > Date: Thu, 7 Aug 2008 11:40:19 -0700 > > > Dear Labmembers, > > One of my collaborators try to etch off Al2O3 at the corners of > samples (consisting of Al2O3 / InGaAs / InP substrate) for Hall > measurements. He found that photo-resist used to define the corners on > Al2O3 surface was peeled off during etching by BHF. Has anyone > sucessfully done photolithography on Al2O3? If so, what kind of > adhesion promotor was used? Also, does anyone know the etch rate of > Al2O3 by BHF? > > Thanks, > Byungha > > ------------------------------------------------------------------------ > Get Windows Live and get whatever you need, wherever you are. Start > here. > From sjkramer at micron.com Fri Aug 8 06:59:23 2008 From: sjkramer at micron.com (sjkramer at micron.com) Date: Fri, 8 Aug 2008 07:59:23 -0600 Subject: etching Al2O3 In-Reply-To: <489BE94C.3080000@gmail.com> References: <489BE94C.3080000@gmail.com> Message-ID: If your resist will hold up to dilute ammonia or TMAH, those should etch alumina nicely. Steve -----Original Message----- From: Baylor Triplett [mailto:baylor.triplett at gmail.com] Sent: Friday, August 08, 2008 12:36 AM To: shide cheng Cc: Byungha Shin; labmembers at snf.stanford.edu Subject: Re: etching Al2O3 All, While I do not have experience with attempting this particular process, it is common for Hf or BHF to penetrate photoresist and result in lift off depending on how long the etch solution is applied, and how concentrated the etch solution is in HF or fluoride. One first attempt is to hard bake the resist which substantially improves the adhesion to the substrate. Then the resist is stripped by an aggressive stripper or plasma ashed off. Adhesion promoters also can help. The ultimate solution can be a second layer or bilayer (sometimes called a "hard mask" that can be etched more easily). However, I suggest searching first for published papers in this area to see if there isn't an easy solution. Baylor shide cheng wrote: > Hi, Byungha, > > My experience is developer will erode the Al, and Al2O3 during > development stage. You may need anther layer to protect them during > photo process. > > Shide > > ---------------------------------------------------------------------- > -- > > From: shinbh93 at stanford.edu > To: labmembers at snf.stanford.edu > Subject: etching Al2O3 > Date: Thu, 7 Aug 2008 11:40:19 -0700 > > > Dear Labmembers, > > One of my collaborators try to etch off Al2O3 at the corners of > samples (consisting of Al2O3 / InGaAs / InP substrate) for Hall > measurements. He found that photo-resist used to define the corners on > Al2O3 surface was peeled off during etching by BHF. Has anyone > sucessfully done photolithography on Al2O3? If so, what kind of > adhesion promotor was used? Also, does anyone know the etch rate of > Al2O3 by BHF? > > Thanks, > Byungha > > ---------------------------------------------------------------------- > -- Get Windows Live and get whatever you need, wherever you are. Start > here. > > From waqasm at stanford.edu Fri Aug 8 16:34:46 2008 From: waqasm at stanford.edu (Waqas Mustafeez) Date: Fri, 8 Aug 2008 16:34:46 -0700 Subject: single undoped si wafer? References: <249e3dc70808051138p4a8397dfoee47ee98c4d0e0bb@mail.gmail.com> <249e3dc70808051140u1cbbe4a4m8d7ee13d55280ff0@mail.gmail.com> Message-ID: Looking for single undoped si wafer. Can pray market price. size and orientation don't matter but looking for high resistivities. Please reply back to saphadke at stanford.edu Thanks! Waqas --------------------------------------------------------------- http://www.stanford.edu/group/salleo/ Ph.D. Program, Salleo Research Group, Electrical Engineering/ Material Science, Stanford University -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Mon Aug 11 09:54:42 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Mon, 11 Aug 2008 09:54:42 -0700 Subject: REMINDER!!! CIS BUILDING BAKE SALE >>> DATE TUESDAY, AUGUST 12TH Message-ID: <20080811165443.0901C610A31@smtp3.stanford.edu> I know what you are all thinking - just one more day until the Bake Sale. Please make every effort to fit the bake sale into your schedule tomorrow by either: * Buying a Bake Good * Bringing a Bake Good * Skipping the Bake Goods and making a Cash Donation I'm hoping to have a very successful bake sale for our favorite "Hall Monitor" Maureen Rochford. Thank you for any support you can lend the bake sale. Jumping Clock Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 _____ From: Maureen Baran [mailto:mbaran at stanford.edu] Sent: Monday, August 04, 2008 4:45 PM To: 'cis-building at cis.stanford.edu'; 'Labmembers at snf.stanford.edu' Subject: CIS BUILDING BAKE SALE >>> DATE TUESDAY, AUGUST 12TH Join us for the CIS Bake Sale to benefit 2008 Breast Cancer 3 Day Walk in September in memory of Maureen Rochford. There are 3 ways you can participate: 1. Buy Bake Goods that are for sale. 2. Bring a Bake Good for sale. 3. Skip the Bake Goods and make a cash donation. The event is Tuesday, August 12th, all day or until we sell out - whatever comes first. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 32255 bytes Desc: not available URL: From masaharu at stanford.edu Mon Aug 11 19:55:07 2008 From: masaharu at stanford.edu (Masaharu Kobayashi) Date: Mon, 11 Aug 2008 19:55:07 -0700 Subject: CIS159(wafer saw room) water leaking Message-ID: <20080811195507.qzq752d7kkw0cw0g@webmail.stanford.edu> Hello all, I am working on wafer saw now. We saw water leaking in the CMP system! I think something is wrong. Does anyone help? Thank you Masaharu From mbaran at stanford.edu Tue Aug 12 08:50:25 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 12 Aug 2008 08:50:25 -0700 Subject: The BAKE SALE is going on right in Office 146 - next to the copy room Message-ID: <20080812155025.C99F22D6AD5@smtp1.stanford.edu> Good morning, the bake sale is going on right now in office 146 (Uli and Jeannie's office), next to the copy room on the first floor. We have great treats to go with your morning coffee or afternoon break or both. Please come by. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Tue Aug 12 11:42:57 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 12 Aug 2008 11:42:57 -0700 Subject: Great time for Dessert with Lunch - Office 146 Message-ID: <20080812184258.029CB65B64C@smtp2.stanford.edu> Please stop by office 146 and participate in our bake sale. This would be a great time to pick up something sweet for dessert or for later in the afternoon to have with your coffee. This bake sale is a great alternative to the vending machine and as we all know, this opportunity doesn't happen very often for the CIS dwellers. Thank you in advance for your support for a great cause. Maureen Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Wed Aug 13 14:13:42 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Wed, 13 Aug 2008 14:13:42 -0700 Subject: Successful BAKE SALE due to YOU Message-ID: <20080813211342.7B66A65BD17@smtp2.stanford.edu> Dear Lab Members and CIS Building Dwellers, Thank you so much for supporting our bake sale and your generosity over all - we SOLD out and made $600.00!!!! That was the easy part now, Jane Edwards is going to do the hard part and walk for 3 days!! (Thank you, Jane!) Again thank you, for all your support and generosity. Sincerely, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From zeost at stanford.edu Thu Aug 14 16:02:54 2008 From: zeost at stanford.edu (Jaeho Lee) Date: Thu, 14 Aug 2008 16:02:54 -0700 Subject: Help needed for maskmaking Message-ID: <000001c8fe61$e2cb3470$a8619d50$@edu> Dear lab members, My name is Jaeho Lee and I'm working for Dr. Goodson in ME department. I need to fabricate some simple aluminum structure on silicon wafers, which would be used for temperature measurement in ME131A labs. I recently joined SNF so I'm not familiar with this type of work and I currently have no senior members from our lab to help me on maskmaking. I have the design in my mind. A mask should be designed in a fashion that four pad measurements could be performed with a micron thick interconnect. I just don't know where to get started such as using a software for drawing and ordering it the vendor. I'd greatly appreciate anyone's help or comments. Thanks Jaeho Lee MS Candidate Mechaniical Engineering Stanford University 650) 213-6263 -------------- next part -------------- An HTML attachment was scrubbed... URL: From ckenney at stanford.edu Sun Aug 17 15:40:22 2008 From: ckenney at stanford.edu (Crystal Rose Kenney) Date: Sun, 17 Aug 2008 15:40:22 -0700 (PDT) Subject: Question about etching InAlAs/InGaAs - Alternative masking layers In-Reply-To: <221680263.2412941219012379795.JavaMail.root@zm06.stanford.edu> Message-ID: <1701300554.2413201219012822118.JavaMail.root@zm06.stanford.edu> In my experiments I have an MBE stack of InAlAs and InGaAs materials. I need to etch down about 150nm and place contacts in those holes. I was initially planning on using photoresist as my mask layer, first by opening the areas to etch and then evaporating metal into the holes and doing liftoff. However, because of the high bias needed to etch InAlAs that doesn't look like a viable option. I do not wish to use two lithography steps of the same mask layer (karlsuss mask) because I am concerned about misalignment issues since I need good contact of metal on the sides of the contact holes. Are there other masking layers that could be used in this case? I need something that could stand a high bias (possibly using pquest) for etching and then use the same mask layer to evaporate metal and then have some way of removing said mask layer. I'm also open to suggestions for alternative processing steps. Thank you in advance for your help. ~Crystal Kenney From mcvittie at cis.Stanford.EDU Mon Aug 18 11:26:06 2008 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Mon, 18 Aug 2008 11:26:06 -0700 (PDT) Subject: Question about etching InAlAs/InGaAs - Alternative masking layers In-Reply-To: <1701300554.2413201219012822118.JavaMail.root@zm06.stanford.edu> Message-ID: Hi Crystal, The In material etch process on the PQ is run hot. The chuck temp is set to around 170C with the sample running near 200C. This is too hot for a resist mask. You to use either an oxide or a nitride mask. The selectivity to oxide is around 10:1. Jim On Sun, 17 Aug 2008, Crystal Rose Kenney wrote: > In my experiments I have an MBE stack of InAlAs and InGaAs materials. I need to etch down about 150nm and place contacts in those holes. I was initially planning on using photoresist as my mask layer, first by opening the areas to etch and then evaporating metal into the holes and doing liftoff. > > However, because of the high bias needed to etch InAlAs that doesn't look like a viable option. I do not wish to use two lithography steps of the same mask layer (karlsuss mask) because I am concerned about misalignment issues since I need good contact of metal on the sides of the contact holes. Are there other masking layers that could be used in this case? I need something that could stand a high bias (possibly using pquest) for etching and then use the same mask layer to evaporate metal and then have some way of removing said mask layer. > > I'm also open to suggestions for alternative processing steps. Thank you in advance for your help. > > ~Crystal Kenney > -- -------------------------------------------------------------- Jim McVittie, Ph.D. Senior Research Scientist Allen Center for Integrated Systems Electrical Engineering Stanford University jmcvittie at stanford.edu Rm. 336, 330 Serra Mall Fax: (650) 723-4659 Stanford, CA 94305-4075 Tel: (650) 725-3640 From mtang at stanford.edu Mon Aug 18 16:58:17 2008 From: mtang at stanford.edu (Mary Tang) Date: Mon, 18 Aug 2008 16:58:17 -0700 Subject: Lab now open again Message-ID: <48AA0C99.9050708@stanford.edu> Hi all -- The lab is now open again for business. Please make sure to check the status on Coral and be extra careful on your regular system checkout before starting -- not all tools are functional and with a hundred tools in the lab, it is possible something was missed. Also, be aware that steam generation has not yet come back on-line, so the lab may feel unusually cold. As you may have heard, a major power outage took out the lab (and much of Stanford and Menlo Park) for several hours. Special thanks to the efforts of Jose and Leonard of the FacOps crew, who got all the facilities running in short order, and our maintenance & process crew (Gary, Mario, Elmer, Jim, Ted, Ray, Maurice, James) who brought most of the equipment up. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From gsosa at stanford.edu Mon Aug 18 18:23:37 2008 From: gsosa at stanford.edu (Gary J Sosa) Date: Mon, 18 Aug 2008 18:23:37 -0700 Subject: Litho Area Conditions Message-ID: <20080818182337.v22vc36qok0c008c@webmail.stanford.edu> Hi All.... Mary mentioned in her email that there is no steam generation at this time and that the lab feels cold. As of 6:00 PM the temperature near the SVG coaters was 63 degrees and the humidity was 61 %. You may want to reconsider doing Litho tonight, until the temperature and humidity are at optimal conditions. The temp and humidity will have an affect on the photoresist and you may not get the results that you expect. Please be very cautious and take this into consideration so that you will not have to rework you wafers. There is a digital meter on the rack next to the SVG coaters. Typically the temperature is 70 degrees and the humidity is around 42%. If steam generation does not come back online, conditions may get worse as the outside conditions change and the lab has no way to compensate. .. Gary From robinhmb at yahoo.com Mon Aug 18 20:31:46 2008 From: robinhmb at yahoo.com (Robin King) Date: Mon, 18 Aug 2008 20:31:46 -0700 (PDT) Subject: Conditions update at 8:30pm Monday In-Reply-To: <20080818182337.v22vc36qok0c008c@webmail.stanford.edu> Message-ID: <842878.44302.qm@web58709.mail.re1.yahoo.com> Main lab 56F and 63% humidity Litho 59F and 60% humidity --- On Mon, 8/18/08, Gary J Sosa wrote: > From: Gary J Sosa > Subject: Litho Area Conditions > To: "labmembers at snf.stanford.edu" > Date: Monday, August 18, 2008, 6:23 PM > Hi All.... > > Mary mentioned in her email that there is no steam > generation at > this time and that the lab feels cold. As of 6:00 PM the > temperature > near the SVG coaters was 63 degrees and the humidity was 61 > %. You may > want to reconsider doing Litho tonight, until the > temperature and > humidity are at optimal conditions. The temp and humidity > will have an > affect on the photoresist and you may not get the results > that you > expect. Please be very cautious and take this into > consideration so > that you will not have to rework you wafers. There is a > digital meter > on the rack next to the SVG coaters. Typically the > temperature is 70 > degrees and the humidity is around 42%. If steam generation > does not > come back online, conditions may get worse as the outside > conditions > change and the lab has no way to compensate. > > .. Gary From edmyers at stanford.edu Tue Aug 19 03:17:44 2008 From: edmyers at stanford.edu (Ed Myers) Date: Tue, 19 Aug 2008 03:17:44 -0700 Subject: Toxic Gas Alarm 8/19/08 Message-ID: <6.2.5.6.2.20080819031205.02637500@stanford.edu> Lab Members, This mornings Toxic Gas alarm was from a Chlorine signal coming from the exhaust line of the P5000. While there was, and is a signal from this sensor I could not find any indication on the other chlorine sensors in the fab or on our portable system. It is safe to re-enter the fab, I have left the Chlorine and HBr gas boxes which provide these gases to the etch tools turned off. The Chlorine for epi and epi2 should still be available. When the full staff returns in the morning, we will do another evaluation of the sensor and try and get the etch gases turned back on. Regards, Ed From shott at stanford.edu Tue Aug 19 08:11:01 2008 From: shott at stanford.edu (John Shott) Date: Tue, 19 Aug 2008 08:11:01 -0700 Subject: Temperature/humidity control update .... Message-ID: <48AAE285.9070909@stanford.edu> SNF Lab Members: As of about 7 a.m. this morning, steam has been restored to the lab. As a result, we now have the ability to control temperature and humidity in the cleanroom and temperature and humidity are close to their normal range. However, because the lab and tools in it were quite cold overnight (16C/61F), anything with significant thermal mass will not be back to operating temperatures for some time. In particular, I expect that this will include the ASML and ebeam tools. Additionally, any room temperature baths such as 50:1 HF and BOE baths will likely take a couple of hours to get back to their normal daytime temperatures. Please check each tool carefully before use and be extra vigilant in looking for anamolous behavior. We apologize for this extended outage but are doing our best to recover as quickly as possible. Thanks, John From mtang at stanford.edu Tue Aug 19 10:17:51 2008 From: mtang at stanford.edu (Mary Tang) Date: Tue, 19 Aug 2008 10:17:51 -0700 Subject: Maskmaking Clinic, Wed. 8/20, 3 pm Message-ID: <48AB003F.2000101@stanford.edu> Hi all -- Bill Martin will be here on Wednesday, Aug. 20, at 3 pm in CIS 101 with tips and tricks on how to layout and specify a mask -- and how to fill out a maskmaking form. He will also be on hand to answer your specific questions about your mask files. (Bring your USB sticks with your GDSII files!) For those who are interested, there will also be a brief overview on LEdit. Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mbaran at stanford.edu Wed Aug 20 10:22:02 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Wed, 20 Aug 2008 10:22:02 -0700 Subject: 2008-09 SNF Sponsorship Application and 2008-09 Parking Permit Application are Available Message-ID: <20080820172203.32CBB65B80A@smtp2.stanford.edu> IMPORTANT: THE SPONSOR FORM MUST BE RENEWED ANNUALLY ON or BEFORE SEPTEMBER 1st. Note: A parking ticket on Campus will cost you $35.00. Dear Lab Members, The 2008-09 SNF Department Sponsorship Application and Parking Permit Application are available. I have both these applications in a file hanging on the outside of my cubicle. The 2008-09 Sponsorship Application must be filled out before I can have John Shott, Paul Rissman or Mary Tang sign off on it. Then you will need to bring it down to Parking and Transportation at 340 Bonair Siding and hand it in along with your completed 2008-09 Parking Permit Application (if this applies to you). If you need any help in this matter please let me know. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From ytanster at gmail.com Wed Aug 20 14:35:21 2008 From: ytanster at gmail.com (Mike Tan) Date: Wed, 20 Aug 2008 14:35:21 -0700 Subject: sts oxide etch Message-ID: <249e3dc70808201435w22e9a83dleb0dca56e25fbf73@mail.gmail.com> Dear Labmembers, I have been experiencing a significant oxide loss when running the stsetch (I & 2). My 600 A thick oxide is generally etched away within 40 minutes using either the "smooth-shallow" recipe or the "deep" recipe. My process requires an etch time of at least 90minutes with an etch rate of 4um silicon/min. Does anyone have any alternative recipes or recommendations on what oxide thickness I should use? Thank you very much for your help. Mike Tan -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Fri Aug 22 11:26:59 2008 From: mtang at stanford.edu (Mary Tang) Date: Fri, 22 Aug 2008 11:26:59 -0700 Subject: Special Seminar, 2 pm TODAY, CIS 101: Keith Best (ASML) Message-ID: <48AF04F3.4090707@stanford.edu> Greetings labmembers: Are you interested in back-to-front submicron patterning? Are you interested in wafer-level stitching? Does your wafer process sequence lead to difficulty in precision alignment? Then come to Keith Best's presentation this afternoon. Keith is the Director of Special Applications from ASML and he will describe the 3D align system which is installed and recently qualified on the ASML in our lab. He promises interesting examples (and ASML goodies) for attendees. Anyone in the Stanford/SNF community is welcome. This seminar will be held today (Friday), at 2 pm in CIS 101. Hope to see you there! Your ASML & SNF Litho staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Fri Aug 22 13:16:38 2008 From: mtang at stanford.edu (Mary Tang) Date: Fri, 22 Aug 2008 13:16:38 -0700 Subject: PhD Oral Defense, Monday, Aug 25, 2 pm: Ignacio Zuleta Message-ID: <48AF1EA6.8000203@stanford.edu> When: Monday 25, 2pm Where: Clark S361 What: PhD Oral Defense Title: A HIGH SPEED MASS SPECTROMETER BASED ON MICROMACHINED ION OPTICS AND POSITION SENSITVE DETECTION FOR THE MONITORING OF NON-STATIONARY PROCESSES Abstract: As new chemical systems become of relevance, the question of how to monitor their dynamics quickly comes to the fore. In the last few years, chemical systems consisting of complex mixtures of biological molecules have become the subject of intense research, requiring new tools to measure their state. Two main families of techniques have been applied extensively to these problems, spectroscopy and mass spectrometry. With the advent of soft ionization techniques like ESI and MALDI, proteins, DNA and metabolite mixtures can be analyzed using mass spectrometry. Even given these successes, the problem of continuously monitoring a condensed phase chemical system using mass spectrometry still proves very challenging, from the sample introduction aspect to the ability of the analyzer to monitor efficiently the stream of ions created. We have developed a number of advances in this regard, consisting of methods to carry over continuous mass spectrometry based on the continuous modulation of an ion beam. These advances consist of ion optical devices and fabrication methods for the modulation of ion beams, novel ion detection schemes and data processing. We show that when all these elements are combined, real-time mass spectrometric monitoring of chemical systems at very high spectral acquisition rates can be achieved. In particular we demonstrate its application to the monitoring of a number of non-stationary processes: liquid plugs of a given substance, chemical imaging of a surface and protein folding kinetics. -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From hra at stanford.edu Mon Aug 25 09:45:25 2008 From: hra at stanford.edu (Hyejun Ra) Date: Mon, 25 Aug 2008 09:45:25 -0700 Subject: PhD Dissertation Defense for Hyejun Ra Message-ID: <20080825164529.C46C16596FD@smtp2.stanford.edu> University PhD Dissertation Defense In vivo cellular imaging with MEMS scanners Hyejun Ra Department of Electrical Engineering Stanford University Research Advisor: Professor O. Solgaard Date: Wednesday, August 27, 2008 Time: 1:15 PM (Refreshments served at 1 PM) Location: CIS-X Auditorium, Center for Integrated Systems Abstract: The ability to image through tissue with high resolution in vivo enables non-invasive early cancer detection in humans and therapeutic research in live pre-clinical animal models. The dual-axes confocal (DAC) microscope architecture is proposed to miniaturize a tabletop microscope into a handheld or endoscope-compatible size. I will present the 2-D (two-dimensional) MEMS scanner that enables in vivo real-time imaging in the DAC configuration. It consists of a 2-D gimbal structure in double silicon-on-insulator (SOI) layers and is actuated by electrostatic vertical combdrives. In the second part, I will present a handheld DAC microscope system where the MEMS scanner is aligned and integrated with miniature optics. Deep tissue imaging with 3-D reconstruction is demonstrated. Finally, the application of the miniaturized DAC microscope in in vivo intravital imaging will be shown in therapeutic research of siRNA silencing in the skin. -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Mon Aug 25 11:38:36 2008 From: mtang at stanford.edu (Mary Tang) Date: Mon, 25 Aug 2008 11:38:36 -0700 Subject: Process Clinic today (Monday), 2-4 pm Message-ID: <48B2FC2C.8030900@stanford.edu> Greetings Labmembers -- Just a reminder -- there's a Process Clinic today, from 2-4 pm, just in the office/cubicle area near Maureen's office. Keith Best from ASML will be here to answer any 3D align questions (and questions on just about anything else -- he's a wealth of information!) SNF staff will also be on hand, with a SpecMat quorum (so bring your special materials and new processes requests.) New labmembers are strongly encouraged to use this as an opportunity to get help in laying out process flows or device designs. Hope to see you there! Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mbaran at stanford.edu Mon Aug 25 13:26:02 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Mon, 25 Aug 2008 13:26:02 -0700 Subject: One Found Earring outside the Lab Message-ID: <20080825202601.E36AC60EABE@smtp3.stanford.edu> If you misplaced an earring this morning, while you were putting on your booties to enter the lab please stop by my cubicle and be prepared to describe it. Thanks, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From kcrabb at stanford.edu Mon Aug 25 16:25:56 2008 From: kcrabb at stanford.edu (Kevin Crabb) Date: Mon, 25 Aug 2008 16:25:56 -0700 Subject: 6" wafers? Message-ID: <002f01c90709$ed3dcc00$ee2642ab@delllaptop> Hello All, I have need for a total of three 6" wafers, and was wondering if anybody had any 'extras' they're willing to share. They are merely serving as a carrier for my samples which will be getting irradiated with cesium ions from an outside vendor. I therefore do not care what the doping, resistivity, or thickness is, or even if there are oxide or nitride or other layers on top. I only need full (non-broken) 6" wafers. (Heck, they don't even have to be silicon, I don't think.) If anybody has any, I'd be much obliged. Thanks, Kevin kcrabb at stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Tue Aug 26 09:45:39 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 26 Aug 2008 09:45:39 -0700 Subject: FW: 2008-09 SNF Sponsorship Application and 2008-09 Parking Permit Application are Available Message-ID: <20080826164538.803232D6A14@smtp1.stanford.edu> Dear Labmembers, REMINDER: You need to have a new 2008-09 SNF Sponsorship form completed and filed with Parking and Transportation on or before Tuesday, September 2nd, 2008 (next Tuesday because Monday is a campus wide holiday)! Clarification on who needs to fill out a 2008-09 Sponsorship form - ALL current Industrial Users and ALL current other Academic Users of SNF only. The ones that are exempt from having to fill out this form are current Stanford students because they are already sponsored by the University to be on campus. Again, the 2008-09 SNF Sponsorship form and Parking Permit Application are hanging outside my cubicle for you to take. Thanks, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 _____ From: Maureen Baran [mailto:mbaran at stanford.edu] Sent: Wednesday, August 20, 2008 10:22 AM To: 'Labmembers at snf.stanford.edu' Subject: 2008-09 SNF Sponsorship Application and 2008-09 Parking Permit Application are Available Importance: High IMPORTANT: THE SPONSOR FORM MUST BE RENEWED ANNUALLY ON or BEFORE SEPTEMBER 1st. Note: A parking ticket on Campus will cost you $35.00. Dear Lab Members, The 2008-09 SNF Department Sponsorship Application and Parking Permit Application are available. I have both these applications in a file hanging on the outside of my cubicle. The 2008-09 Sponsorship Application must be filled out before I can have John Shott, Paul Rissman or Mary Tang sign off on it. Then you will need to bring it down to Parking and Transportation at 340 Bonair Siding and hand it in along with your completed 2008-09 Parking Permit Application (if this applies to you). If you need any help in this matter please let me know. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From xzhuang at stanford.edu Thu Aug 28 15:57:22 2008 From: xzhuang at stanford.edu (Steve Zhuang) Date: Thu, 28 Aug 2008 15:57:22 -0700 (PDT) Subject: LTO coverage in deep trenches In-Reply-To: <002f01c90709$ed3dcc00$ee2642ab@delllaptop> Message-ID: <2092384857.544621219964242291.JavaMail.root@zm02.stanford.edu> Hello All, I am trying to find out if LTO has good conformal coverage in deep trenches. I have straight trenches are 30 um wide, and about 275 um deep, in a silicon wafer. I plan to deposit 0.5um LTO as an insulation layer over the side walls. Will this work? Your input will be highly appreciated. Thanks. Steve ----- Original Message ----- From: "Kevin Crabb" To: labmembers at snf.stanford.edu Sent: Monday, August 25, 2008 4:25:56 PM GMT -08:00 US/Canada Pacific Subject: 6" wafers? Hello All, I have need for a total of three 6? wafers, and was wondering if anybody had any ?extras? they?re willing to share. ?They are merely serving as a carrier for my samples which will be getting irradiated with cesium ions from an outside vendor. ?I therefore do not care what the doping, resistivity, or thickness is, or even if there are oxide or nitride or other layers on top. ?I only need full (non-broken) 6? wafers. (Heck, they don?t even have to be silicon, I don?t think.) ?If anybody has any, I?d be much obliged.? Thanks, Kevin kcrabb at stanford.edu From mcvittie at cis.Stanford.EDU Thu Aug 28 17:36:04 2008 From: mcvittie at cis.Stanford.EDU (Jim McVittie) Date: Thu, 28 Aug 2008 17:36:04 -0700 (PDT) Subject: LTO coverage in deep trenches In-Reply-To: <2092384857.544621219964242291.JavaMail.root@zm02.stanford.edu> Message-ID: Steve, Some years ago, I did a bit of modeling and measurements of LTO deposition profiles. LTO can be modeled pretty well with a constant sticking coefficient (SC) of about 0.3. This means that you have about 3 brouces off the side walls of your trench before it sticks. This does not lead to good side wall coverage as you go deeper into the trench. TEOS, which is doposited in the 700C range, give much better step coverage. As I recall, TEOS can be modeled as a mixture of a conformal ( very low SC ) component and a high SC ( range of 0.2) component. I am not in my office right now, but I believe these two components were in the range of being so you will get strong conformal deposition deep into your trench with TEOS. If you want, I can send you some papers or some PhD dissertations on this work. Jim On Thu, 28 Aug 2008, Steve Zhuang wrote: > Hello All, > > I am trying to find out if LTO has good conformal coverage in deep > trenches. I have straight trenches are 30 um wide, and about 275 um > deep, in a silicon wafer. I plan to deposit 0.5um LTO as an insulation > layer over the side walls. Will this work? Your input will be highly > appreciated. > > Thanks. > > Steve > > ----- Original Message ----- > From: "Kevin Crabb" > To: labmembers at snf.stanford.edu > Sent: Monday, August 25, 2008 4:25:56 PM GMT -08:00 US/Canada Pacific > Subject: 6" wafers? > > > > > Hello All, > > I have need for a total of three 6??? wafers, and was wondering if anybody had any ???extras??? they???re willing to share. ??They are merely serving as a carrier for my samples which will be getting irradiated with cesium ions from an outside vendor. ??I therefore do not care what the doping, resistivity, or thickness is, or even if there are oxide or nitride or other layers on top. ??I only need full (non-broken) 6??? wafers. (Heck, they don???t even have to be silicon, I don???t think.) ??If anybody has any, I???d be much obliged.?? Thanks, > > Kevin > > kcrabb at stanford.edu > -- -------------------------------------------------------------- Jim McVittie, Ph.D. Senior Research Scientist Allen Center for Integrated Systems Electrical Engineering Stanford University jmcvittie at stanford.edu Rm. 336, 330 Serra Mall Fax: (650) 723-4659 Stanford, CA 94305-4075 Tel: (650) 725-3640