LTO coverage in deep trenches

Jim McVittie mcvittie at cis.Stanford.EDU
Thu Aug 28 17:36:04 PDT 2008


Some years ago, I did a bit of modeling and measurements of LTO deposition
profiles. LTO can be modeled pretty well with a constant sticking
coefficient (SC) of about 0.3. This means that you have about 3 brouces
off the side walls of your trench before it sticks. This does not lead to
good side wall coverage as you go deeper into the trench. TEOS, which is
doposited in the 700C range, give much better step coverage. As I recall,
TEOS can be modeled as a mixture of a conformal ( very low SC ) component
and a high SC ( range of 0.2)  component. I am not in my office right now,
but I believe these two components were in the range of being so you will
get strong conformal deposition deep into your trench with TEOS. If you 
want, I can send you some papers or some PhD dissertations on this work.


On Thu, 28 Aug 2008, Steve Zhuang wrote:

> Hello All,
> I am trying to find out if LTO has good conformal coverage in deep
> trenches. I have straight trenches are 30 um wide, and about 275 um
> deep, in a silicon wafer. I plan to deposit 0.5um LTO as an insulation
> layer over the side walls. Will this work? Your input will be highly
> appreciated.
> Thanks.
> Steve 
> ----- Original Message -----
> From: "Kevin Crabb" <kcrabb at>
> To: labmembers at
> Sent: Monday, August 25, 2008 4:25:56 PM GMT -08:00 US/Canada Pacific
> Subject: 6" wafers?
> Hello All, 
> I have need for a total of three 6” wafers, and was wondering if anybody had any ‘extras’ they’re willing to share.  They are merely serving as a carrier for my samples which will be getting irradiated with cesium ions from an outside vendor.  I therefore do not care what the doping, resistivity, or thickness is, or even if there are oxide or nitride or other layers on top.  I only need full (non-broken) 6” wafers. (Heck, they don’t even have to be silicon, I don’t think.)  If anybody has any, I’d be much obliged.  Thanks, 
> Kevin 
> kcrabb at

Jim McVittie, Ph.D.    			Senior Research Scientist 
Allen Center for Integrated Systems     Electrical Engineering
Stanford University             	jmcvittie at
Rm. 336, 330 Serra Mall			Fax: (650) 723-4659
Stanford, CA 94305-4075			Tel: (650) 725-3640

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