From jptchen at stanford.edu Fri Feb 1 11:31:19 2008 From: jptchen at stanford.edu (Joseph Po-Ta Chen) Date: Fri, 1 Feb 2008 11:31:19 -0800 Subject: Reminder: University Ph.D. Oral Examination- Joseph Po-Ta Chen-Feb. 4th, Monday 9:45 AM In-Reply-To: <51942C4D1C1D4906BE0A0EB3E866E3DC@JosephVaioSZ> References: <51942C4D1C1D4906BE0A0EB3E866E3DC@JosephVaioSZ> Message-ID: "Characterizations of Defects and Bonding Structures in High-K/Si & High-K/GaAs Interfaces" Joseph Po-Ta Chen Department of Materials Science and Engineering Advisor: Yoshio Nishi February 4th, 2008 9:45AM (Refreshments served at 9:30AM) CIS-X Auditorium Abstract: High dielectric constant (K) materials are needed to replace SiO2 and SiON as the gate dielectric for CMOS devices. The leading candidates are hafnium based dielectrics including HfSiON, HfxSi1-xO2, and HfO2. Although recent studies indicate promising device integration of high-K into Si process, the dielectric/Si interface defects and oxide charge trapping centers still remain as critical challenges to process optimizations for MOS gate stacks. Typically, threshold voltage instability and device mobility degrades from scattering with electrical active defects at or near the high-K/Si interface when the interfacial oxide thickness reduced to less than 1 nm. In our study, electron spin resonance (ESR) is utilized to characterize interface defects and trapping centers in Hf0.4Si0.6O2, Hf0.6Si0.4O2, and HfO2deposited on (100)Si. The Pb0 interface defect in Hf0.4Si0.6O2 annealed at 800 oC N2 is found to have ~12% higher g-value anisotropy and higher interfacial strain than those in SiO2/(100)Si. In addition to Pb0 and Pb1 at the underlying SiOx/Si interface, a third defect, believed to be the EX, is observed in undamaged films of 40 nm thick HfxSi1-xO2. For 4 nm HfxSi1-xO2 films annealed in N2 at both 800 and 1000 oC, the Hf0.6Si0.4O2 has a lower total Pb-type interface state density than that of Hf0.4Si0.6O2, and shows less mobility degradation in MOSFET device. Electrically biased paramagnetic defects at 800 oC N2 annealed HfxSi1-xO2/(100)Si and HfO2/(100)Si interfaces in metal oxide silicon (MOS) structures are also reported. These defects are examined by electrical-field controlled ESR and correlated to capacitance-voltage (C-V) analysis. Distributions of ESR active density of interface traps (ESR-Dit), Pb0 and Pb1, exhibit distinct charge humps and peaks in the Si bandgap with maximum peak density of 0.9~1.9?1012 cm-2eV-1 in Hf0.4Si0.6O2/Si interface. Three Pb0 and one Pb1 charged ESR- Dit peaks with density of 1.7~2.8?1012 cm-2eV-1 are observed in Hf0.6Si0.4O2/Si interface. Cross-section transmission electron microscopic (TEM) images show decreasing interfacial layer (IL) thickness with increasing hafnium composition at HfxSi1-xO2/Si interface. The roughest IL observed at the HfO2/Si interface may have contributed to an ESR-Dit of Pb0 greater than 2?1013 cm-2eV-1 and a pinned Fermi-level near mid-gap. It appears that the energy distributions of interface defects in HfxSi1-xO2/Si and HfO2/Si have different signatures compared to those at SiO2/Si interface especially the charged peak near mid-gap. Besides, the ever increasing need for higher speed and lower power computing has already pushed the Si-based transistors close to their performance limit. Alternative materials with high carrier mobility like III-V compound semiconductors are being actively evaluated. GaAs, in particular, embraces the advantages of higher electron mobility and larger bandgap as compared to Si. However, unlike Si, it is difficult to achieve a stable passivation native insulator by the thermal oxidation, and the native oxides were observed to induce high density of interface traps and cause Fermi level pinning. Recent research demonstrates successful MOS devices based on atomic layer deposited (ALD) high-K Al2O3 and HfO2 on GaAs. It suggests that a stable and passivated interface between dielectrics and GaAs is the key component for successful GaAs MOS devices because the GaAs surface is easily degraded during the dielectric deposition. In our study, the interface between ALD grown HfO2 and (100) GaAs which treated with HCl cleaning and (NH4)2S passivation is characterized. ESR detects decreasing paramagnetic defect signals in the sulfide-treated GaAs surface. Meantime, synchrotron radiation photoemission core level spectra indicate successful removal of the native oxides and formation of passivating sulfides on the GaAs surface. Layer-by-layer removal of the HfO2 film reveals a small amount of As2O3 formed at the interface during the ALD process. Traces of arsenic and sulfur out-diffusion into the HfO2 film are observed after a 450oC post-deposition anneal, and may be the origins for the electrically active defects. It appears that HCl+(NH4)2S treatments provide a superior chemical passivation for GaAs and initial surface for atomic layer deposition. -------------- next part -------------- An HTML attachment was scrubbed... URL: From rparsa at stanford.edu Mon Feb 4 08:04:41 2008 From: rparsa at stanford.edu (Roozbeh Parsa) Date: Mon, 04 Feb 2008 08:04:41 -0800 Subject: Seminar: Lessons from Gate Stack Research for Nano Scale Devices and Future Challenges in Silicon based Device Technology Message-ID: <20080204080441.0f968zm5qasw8c8c@webmail.stanford.edu> Title: Lessons from Gate Stack Research for Nano Scale Devices and Future Challenges in Silicon based Device Technology Date: Wednesday, February 6, 2008 Time: 4:00 ? 5:00 pm (refreshments at 3:45) Place: CISX Auditorium Host: Prof. Roger Howe Speaker: Dr. Byoung Hun Lee SEMATECH, Austin, Texas Abstract After the four decades since its implementation in the core of silicon device technology, the polysilicon/SiO2 gate stack has been finally replaced with metal electrode/ high-k dielectric gate stacks for leading edge Si CMOS devices. More than a decade of intense research on the new gate stack materials such as Hf-based gate dielectric and various metal electrodes yielded plenty of new understandings on the device physics and characterization technologies as well as new material systems and provided a new pathway to future nano scale device development. This talk will review the key technical challenges that have been overcome to implement new gate stack materials, including the discussion on the mobility degradation mechanism of high-k dielectric, a unified dipole model used to control the effective workfunction of metal electrode, and new understandings on the reliability physics for high-k dielectrics. Then, the technical challenges associated with alternative materials and novel devices will be discussed for future device and material research. Biography: Byoung Hun Lee received a B.S. (1989) and a M.S. (1992) in Physics from Korea Advanced Institute of Science and Technology and Ph.D (2000) in electrical and computer engineering from the University of Texas at Austin. He worked at Samsung semiconductor (1992-1997) and IBM (2001-2007). He has authored and co-authored more than 300 journal and conference papers in the various semiconductor research areas including memory technology, MOSFET reliability, SOI device and process, strained silicon devices, and high-k and metal gate process and devices. He is currently managing emerging technology program at SEMATECH. He is a senior member of IEEE and acting as a guest editor for Microelectronics Engineering and IEEE Transaction on Devices and Materials Reliability. He is a general chair of IEEE International Symposium on Advanced Gate Stack Technology in 2008 and served a member of technical committee in various technical conferences including International Reliability Physics Symposium, Semiconductor Interface Specialist Conference and VLSI-TSA. From mtang at stanford.edu Mon Feb 4 17:26:14 2008 From: mtang at stanford.edu (Mary Tang) Date: Mon, 04 Feb 2008 17:26:14 -0800 Subject: Reminder re SNF Lab Bins: Purple dots for February Message-ID: <47A7BB36.4010600@stanford.edu> Hi everyone -- Just a reminder: If you have a lab bin in the lab and personal wafer boxes (WIP) that are not stored in a lab bin, please, please please put a PURPLE DOT on them and make sure they are marked with your Coral name by next Monday, Feb. 11. PURPLE DOTS are available in the gowning room. We are asking for your help in keeping on top of lab bins and WIP. Deepest apologies for the inconvenience, but we are short of lab bins -- in no small part because labmembers have left or transferred their bins to lab mates... We need to find a way to keep our records constantly updated which will help ensure that there are lab bins to go around for people who need them. As for the WIP, December's cleanup netted 18 cardboard boxes filled mostly with WIP and about 3 cardboard boxes filled with masks (!?), most of which are still unclaimed. We are hoping the monthly dot marking will help keep the lab tidy. Again, we recognize the inconvenience, but ask that everyone work with us to find a solution that is workable -- the monthly DOTS may not be the answer, but as it's been reasonably successful with the bunnysuits, it seemed reasonable to try using them elsewhere... Suggestions for improvement would be appreciated. Thanks all --- Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From saraswat at cis.stanford.edu Mon Feb 4 22:33:15 2008 From: saraswat at cis.stanford.edu (Krishna Saraswat) Date: Mon, 4 Feb 2008 22:33:15 -0800 Subject: Special seminar by Prof. Luca Larcher on leakage in gate dielectrics Message-ID: <2899B3D8-1E1B-4F66-AA4E-487ECDC56FCC@cis.stanford.edu> SEMINAR By Prof. Luca Larcher University of Modena and Reggio Emilia, Italy on STATISTICAL MODELING OF LEAKAGE CURRENTS THROUGH SIO2/HIGH-K DIELECTRIC STACKS In Packard 204, on Friday, February 8, 2008, at 3 pm ABSTRACT In this talk, a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-k dielectric stacks is presented. It will be shown that simulations accurately reproduce experimental currents measured also at various temperatures on capacitors with various high-k (HfO2, HfSiON, Al2O3) dielectric stacks. Statistical simulations are exploited to investigate the impact of high-k?s traps on leakage current distribution for Flash memory applications, demonstrating that defects strongly reduces the potential improvement due to the introduction of band-gap engineered high-k tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-k tunnel stacks and to improve technology-reliability issues related to Flash memory applications. Prof. Luca Larcher graduated in Electronic Engineering from the University of Padova, Italy, in 1998. He received his Ph.D. degree in 2001 from the University of Modena and Reggio Emilia, working on the compact modeling of non-volatile memories (E2PROM and Flash). He is currently Assistant Professor of Electronics at the University of Modena and Reggio Emilia, Italy. His research interests concern mainly the electrical characterization, the compact modeling and the failure mechanism analysis of standard and innovative Flash memories. He is working on the characterization and design of Radio Frequency integrated circuits in CMOS technology. He authored and coauthored a book (?Floating Gate Devices: Operation and Compact Modeling,? P. Pavan, L. Larcher, and A. Marmiroli, Kluwer Academic Press, Boston, ISBN 1-4020-7731-9, January 2004), and more than 55 technical papers. -------------- next part -------------- An HTML attachment was scrubbed... URL: From jhh323 at stanford.edu Tue Feb 5 11:16:23 2008 From: jhh323 at stanford.edu (Jeong-Hee Ha) Date: Tue, 05 Feb 2008 11:16:23 -0800 Subject: Reminder: Ph.D. Oral Examination- Jeong-Hee Ha - Feb.7th,2PM In-Reply-To: <20080124142120.3dwgcyp5wk0wwwko@webmail.stanford.edu> References: <20080124142120.3dwgcyp5wk0wwwko@webmail.stanford.edu> Message-ID: <20080205111623.ih7rjzsuxogwg8kc@webmail.stanford.edu> "ATOMIC SCALE EXPERIMENTAL AND THEORETICAL STUDIES OF HIGH-K GATE DIELECTRIC INTERFACES" Jeong-Hee Ha Department of Materials Science and Engineering Advisor: Prof. Paul C. McInyre Co-Advisor: Prof. Kyeongjae (KJ) Cho Thursday, February 7th, 2008 2:00 PM (Refreshments served at 1:45 PM) Packard Bldg. Rm 202 ?????? For several decades, silicon semiconductor devices have been dramatically scaled down to sub-100 nm MOSFET channel lengths in order to achieve higher device density and performance. In this regime, high-k dielectrics which can give large gate capacitances with dielectric films that are physically thicker than corresponding silicon oxide or oxynitride gate dielectrics are needed to reduce the substantial gate leakage current resulting from direct quantum mechanical tunneling across the dielectric layer. ???? Recently research and development on materials selection for alternative gate stack has converged on HfO2 based high-k oxides (HfO2, HfSiO4, or HfSiON). In 2007, Intel and IBM also announced their plan to introduce Hf-based high-k for their 45nm production. In general, those high-k oxides are deposited in a process which results in controlled formation of an ultra-thin SiO2-like passivation layer on the Si (100) surface. This SiO2-based interface layer provides the advantages of relatively low defect density afforded by the Si/SiO2 interface. However, defects at the internal dielectric interface between HfO2 and SiO2 may produce fixed charge and threshold voltage instability under bias. In this talk, careful analysis is presented to elucidate intrinsic properties of this HfO2/SiO2 interface and to gain knowledge of possible solutions for problems associated with interface defects. ???? The first part of the presentation contains the results of a phase separation study of initially-intermixed HfO2/SiO2 interfaces by in-situ low angle x-ray scattering technique. Due to the positive heat of mixing (?Hmix>0), the initially-intermixed HfO2/SiO2 interface experiences phase separation upon high temperature annealing up to 750?C, which results in a sharper interface. The extracted activation enthalpy for phase separation was 2.06 ? 0.15 eV. Considering the thermal budget of typical CMOS processes, the HfO2/SiO2 interface will encounter this phenomenon during device fabrication. The second part of the talk summarizes the results of density functional theory (DFT) simulations performed on atomistic models of the HfO2/SiO2 interface. The simulations show that the HfO2/SiO2 interface introduces occupied midgap states within the band gap. This is a result of undercoordinated Hf atoms at the interface, and the mid gap states provide a source of positive fixed charge when non-bonding electrons on the interface Hf atoms are depleted by Fermi level change. Possible remedies of Vfb/Vth shifts by chemical passivation of the HfO2-SiO2 interface are suggested based on these simulations. Finally, a study of oxygen transfer from metal gate into high-k dielectrics is presented. Because alternative metal gates are being developed along with high-k dielectrics, how the HfO2/SiO2 interface will be affected by the presence of the metal gate layer is an important issue. Experimental studies of oxygen transfer from W metal gates to the dielectric stack upon high-temperature annealing is provided using transmission electron microsopy (TEM), Fourier transform infrared spectroscopy (FTIR), synchrotron radiation photoemission spectroscopy (SR-PES), and current-voltage (CV) measurements.??? -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Tue Feb 5 13:48:06 2008 From: mtang at stanford.edu (Mary Tang) Date: Tue, 05 Feb 2008 13:48:06 -0800 Subject: SNF Process Grand Rounds: Friday,2/8, 11:30-1 Message-ID: <47A8D996.9090201@stanford.edu> Hi everyone -- Just a reminder that there's a Process Grand Rounds this Friday, 2/8, at 11:30 am in the CIS 101 conference room. There will be pizza and two topics for discussion: 1. Meredith Lee will be asking for advice on her process flow for her proposed bioanalytical device, a microfluidic channel with integrated photonic structures. 2. There will be an information sharing and brainstorming session for anyone involved or interested in the ASML/Epi wafer loading problem. For those who aren't familiar with the situation, the ASML is having problems loading certain kinds of wafers, which may be related to certain processing through epi/epi2. At least two groups seem to have developed processing solutions. The objective is to pool the experience and knowledge of labmembers and ASML engineers. All labmembers are welcome. Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mbaran at stanford.edu Tue Feb 5 13:58:12 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 5 Feb 2008 13:58:12 -0800 Subject: Phone Found in the Ladies Room Across from The Lab Message-ID: <20080205215812.768BC60ED4C@smtp3.stanford.edu> A cell phone was found in the ladies room across from the lab. If you suddenly can't find your phone please come see me in cubicle # 41 on the first floor next to the doors facing Applied Phyics. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From rohank at stanford.edu Wed Feb 6 12:06:00 2008 From: rohank at stanford.edu (Rohan D. Kekatpure) Date: Wed, 6 Feb 2008 12:06:00 -0800 Subject: AMT for etching <100 nm features on AMTEtcher: Results Message-ID: Hi All, I had asked a few days ago about using AMTEtcher for etching small (50-100 nm) features in Silicon/SOI. Alex Guichard and myself performed three tests and tried to etch features ranging between 200 nm to 50 nm widths (defined on Raith) on AMTetcher. The recipe was the following (suggested by Jim McVittie): Substrate: SOI Pressure: 20 mT NF3: 20 sccm Hexode Temp: 20-22 C Power setting: 1600 W Transmitted Power: 754/722 W Reflected power: 21/0 W Bias setting: -430 V The etch rate was pretty repeatable and typically varied between 30 nm/ min to 33 nm/min. If you are interested further, send me an email and I will send you the SEMs. Sincere thanks to everybody who provided their inputs. -Rohan From rparsa at stanford.edu Wed Feb 6 15:44:32 2008 From: rparsa at stanford.edu (Roozbeh Parsa) Date: Wed, 06 Feb 2008 15:44:32 -0800 Subject: MEMS Seminar NOW in CISX Aud. Message-ID: <20080206154432.1ert4vo68g8g0gw8@webmail.stanford.edu> Title: Lessons from Gate Stack Research for Nano Scale Devices and Future Challenges in Silicon based Device Technology Date: Wednesday, February 6, 2008 Time: 4:00 ? 5:00 pm (refreshments at 3:45) Place: CISX Auditorium Host: Prof. Roger Howe Speaker: Dr. Byoung Hun Lee SEMATECH, Austin, Texas Abstract: After the four decades since its implementation in the core of silicon device technology, the polysilicon/SiO2 gate stack has been finally replaced with metal electrode/ high-k dielectric gate stacks for leading edge Si CMOS devices. More than a decade of intense research on the new gate stack materials such as Hf-based gate dielectric and various metal electrodes yielded plenty of new understandings on the device physics and characterization technologies as well as new material systems and provided a new pathway to future nano scale device development. This talk will review the key technical challenges that have been overcome to implement new gate stack materials, including the discussion on the mobility degradation mechanism of high-k dielectric, a unified dipole model used to control the effective workfunction of metal electrode, and new understandings on the reliability physics for high-k dielectrics. Then, the technical challenges associated with alternative materials and novel devices will be discussed for future device and material research. Biography: Byoung Hun Lee received a B.S. (1989) and a M.S. (1992) in Physics from Korea Advanced Institute of Science and Technology and Ph.D (2000) in electrical and computer engineering from the University of Texas at Austin. He worked at Samsung semiconductor (1992-1997) and IBM (2001-2007). He has authored and co-authored more than 300 journal and conference papers in the various miconductor research areas including memory technology, MOSFET reliability, SOI device and process, strained silicon devices, and high-k and metal gate process and devices. He is currently managing emerging technology program at SEMATECH. He is a senior member of IEEE and acting as a guest editor for Microelectronics Engineering and IEEE Transaction on Devices and Materials Reliability. He is a general chair of IEEE International Symposium on Advanced Gate Stack Technology in 2008 and served a member of technical committee in various technical conferences including International Reliability Physics Symposium, Semiconductor Interface Specialist Conference and VLSI-TSA. From pleu at stanford.edu Wed Feb 6 21:43:43 2008 From: pleu at stanford.edu (Paul Leu) Date: Wed, 6 Feb 2008 23:43:43 -0600 Subject: Reminder: PhD Oral Defense and Abstract - Paul Leu, Friday 2/8 3 PM Message-ID: <000001c8694c$66e14750$34a3d5f0$@edu> Semiconductor Nanowires: Modeling, Experiments, and Their Implications Paul W. Leu Department of Mechanical Engineering Advisors: Prof. Paul C. McIntyre and Prof. Kyeongjae (KJ) Cho Friday, February 8th, 2008 3:00 PM (Refreshments served at 2:45 PM) CIS-X 101 Semiconductor nanowires (NWs) have the potential for a variety of nanoelectromechanical and nanodevice applications. This presentation discusses the electromechanical properties and electrical transport of semiconductor NWs. The first part of the talk covers the systematic study of the mechanical and electrical properties of small diameter (< 3 nm) silicon NWs under axial strain using ab initio density functional theory calculations. The values of Young's Modulus, Poisson ratio, band gap, effective mass, work function (WF) and deformation potentials were calculated for <110> and <111> oriented Si NWs. We performed a detailed study of the effects of axial strain on the band structure and electronic properties and attempt to predict the effect of strain on electronic transport properties. We found a dramatic decrease of the deformation potentials of Si NWs under strain, which may lead to a many fold increase of electron or hole mobilities. The decrease of deformation potentials occurs as NWs undergo a direct-to-indirect band gap transition and is concurrent to the increase of effective mass. We also found that quantum confinement in Si NWs acts as a built-in tensile strain, which splits conduction band valleys and decreases transport effective mass. The second part of the talk covers the fabrication of vertically aligned germanium NW structures and their transport and doping characterization. Dense vertical Ge NWs were grown epitaxially on Ge <111> substrates from Au catalysts. The NWs could be doped by the deposition of a conformal shell of boron-doped Ge around the vertical NWs. The NWs were encapsulated in highly conformal silica using an alternating layer deposition process to isolate and support them. Chemical mechanical polishing was used to planarize the samples and expose the Ge NW tips. The post-CMP cleaning was found to be important in removing slurry particles and contamination from the samples while leaving the Ge NWs intact. We probed the topography and electrical transport properties of these encapsulated vertical Ge NW structures using a probe station and conductive AFM. The NWs were shown to exhibit resistor-like IV characteristics when grown on p-type substrates and p-n junction rectifying behavior when grown on n-type substrates. All processes took place at temperatures below 400o C, a key requirement for monolithic 3-dimensional integration of semiconductor devices on Si integrated circuits. -------------- next part -------------- An HTML attachment was scrubbed... URL: From saraswat at cis.stanford.edu Thu Feb 7 16:37:30 2008 From: saraswat at cis.stanford.edu (Krishna Saraswat) Date: Thu, 7 Feb 2008 16:37:30 -0800 Subject: Special seminar by Prof. Luca Larcher on leakage in gate dielectrics Message-ID: <5E613A58-6925-4D21-B5EE-6A046C56B02F@cis.stanford.edu> SEMINAR By Prof. Luca Larcher University of Modena and Reggio Emilia, Italy on STATISTICAL MODELING OF LEAKAGE CURRENTS THROUGH SIO2/HIGH-K DIELECTRIC STACKS In Packard 204, on Friday, February 8, 2008, at 3 pm ABSTRACT In this talk, a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-k dielectric stacks is presented. It will be shown that simulations accurately reproduce experimental currents measured also at various temperatures on capacitors with various high-k (HfO2, HfSiON, Al2O3) dielectric stacks. Statistical simulations are exploited to investigate the impact of high-k?s traps on leakage current distribution for Flash memory applications, demonstrating that defects strongly reduces the potential improvement due to the introduction of band-gap engineered high-k tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-k tunnel stacks and to improve technology-reliability issues related to Flash memory applications. Prof. Luca Larcher graduated in Electronic Engineering from the University of Padova, Italy, in 1998. He received his Ph.D. degree in 2001 from the University of Modena and Reggio Emilia, working on the compact modeling of non-volatile memories (E2PROM and Flash). He is currently Assistant Professor of Electronics at the University of Modena and Reggio Emilia, Italy. His research interests concern mainly the electrical characterization, the compact modeling and the failure mechanism analysis of standard and innovative Flash memories. He is working on the characterization and design of Radio Frequency integrated circuits in CMOS technology. He authored and coauthored a book (?Floating Gate Devices: Operation and Compact Modeling,? P. Pavan, L. Larcher, and A. Marmiroli, Kluwer Academic Press, Boston, ISBN 1-4020-7731-9, January 2004), and more than 55 technical papers. -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Thu Feb 7 18:03:07 2008 From: mtang at stanford.edu (Mary Tang) Date: Thu, 07 Feb 2008 18:03:07 -0800 Subject: Reminder: Process Grand Rounds 2/8/08 Message-ID: <47ABB85B.2050000@stanford.edu> Hi everyone -- Just a reminder of the Process Grand Rounds Friday, 11:30 am in CIS 101. On the agenda: - Meredith Lee, asking for inputs about her proposed process flow for an integrated biophotonic/microfluidic device. - Brainstorming session on the handling problems the ASML seems to have with Epi/Epi2-processed wafers. Pizza will be provided. -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Thu Feb 7 18:52:39 2008 From: mtang at stanford.edu (Mary Tang) Date: Thu, 07 Feb 2008 18:52:39 -0800 Subject: Ultratech: Down for good.... Message-ID: <47ABC3F7.304@stanford.edu> Dear labmembers: It is with deepest regret and a sigh of relief that we report the remaining ultratech stepper is down for good. With blood, sweat, and tears, Mahnaz, Mario, Gary, and Cesar kept the machine limping along for months (years?) until the last user reported his project complete. For SNF, the Ultratech 1000 stepper was a workhorse system: easy to use and reliable, until age and obsolescence began to take its toll. In its time, it had state-of-the-art autoalignment capability and was the industry standard. It (or rather, a slightly earlier model) is commemorated on the insightful Chip History website: https://www.chiphistory.org/equipment_landmarks/1980/interesting_products/ultratech_model900_stepper_1980_84/ultratech.htm It remains in the lab, though will be removed soon. We will hold a memorial ceremony then and all will be welcome to join. The SNF Litho Team -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From tberg at stanford.edu Fri Feb 8 08:56:15 2008 From: tberg at stanford.edu (Ted Berg) Date: Fri, 08 Feb 2008 08:56:15 -0800 Subject: Power Glitch Message-ID: <47AC89AF.4040201@stanford.edu> Hello all, We ha d a power glitch at about 8:20 several furnace banks , the Epi and possibly other tools most have been restarted but check with tool owners to be sure before running. Thanks,ted From mbaran at stanford.edu Fri Feb 8 14:57:06 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Fri, 8 Feb 2008 14:57:06 -0800 Subject: Another cell phone found... Message-ID: <20080208225706.444CB65B51F@smtp2.stanford.edu> Another cell phone found in the gowning room if it is yours, please come by my cubicle #41 on the first floor of the CIS building and claim it. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From gsosa at stanford.edu Fri Feb 8 16:12:49 2008 From: gsosa at stanford.edu (Gary J Sosa) Date: Fri, 08 Feb 2008 16:12:49 -0800 Subject: YES Oven Update Message-ID: <20080208161249.6zjpsxenqgo0cckk@webmail.stanford.edu> Hello Labmembers.... In an attempt to try and eliminate the intermittant odors from the YES Oven, we added 2 vacuum and nitrogen cycles to the program to ensure that any residual HMDS is evacuated from the chamber. The 2 additional vacuum / nitrogen cycles add about 6 minutes to the total process time. These changes in the program are not reflected on the green program sheet at the tool but the steps are as follows: Steps 1 through 9 are the same Step 10: L= 0004 Loop statememt- Loop 4 times Step 11: M= 2:00 02 2 minutes of vacuum to pump out residuals Step 12: M= 1:09 01 1 minute 9 seconds of Nitrogen to purge chamber Step 13: L> 11 Loop statement- Loop back to step 11 Step 14 Continue with normal program. Please continue to report any unusual odors in coral. Thanks... Gary From ytanster at gmail.com Sat Feb 9 08:40:41 2008 From: ytanster at gmail.com (Mike Tan) Date: Sat, 9 Feb 2008 08:40:41 -0800 Subject: code for the wafer_saw room Message-ID: <249e3dc70802090840v51188000q6726dadfdc944e06@mail.gmail.com> Does anyone know what is the combination for the door locking the room with the wafersaw? Thanks. Mike -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Wed Feb 13 07:52:50 2008 From: mtang at stanford.edu (Mary Tang) Date: Wed, 13 Feb 2008 07:52:50 -0800 Subject: Process Grand Rounds THIS Friday/Demo Video Message-ID: <47B31252.4000105@stanford.edu> Greetings labmembers: Due to popular demand (and rapidly growing list of proposed topics for discussion), it looks like we'll have another Process Grand Rounds THIS Friday, 2/15, at 11:30 in CIS 101. (For minutes of last week's session, check http://snf/Labmembers/ProcessGrandRound020808.html ). All are welcome to attend. The topics for discussion: 1. Wafer handling on the ASML (presented by the ASML Team, subject to availability of presentation materials) and update on action items from last Friday's brainstorming. 2. Brainstorming session on performance issues with STS etch (everyone is encouraged to bring data, recipes, etc.) 3. Quick 10 minute planning session for future Process Grand Rounds. As long as there are topics of interest, we'll keep holding them. If we can set agendas for the next few sessions, people can plan ahead and bring/prepare materials to share. Pizza will be provided. Hope to see you there! Your SNF Staff PS: Mike Deal has produced the coolest video ever of the (de)struction next door. To see it, check out the links on the SNF home page. Enjoy! -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From pleu at stanford.edu Wed Feb 13 21:31:13 2008 From: pleu at stanford.edu (Paul Leu) Date: Wed, 13 Feb 2008 23:31:13 -0600 Subject: Solar Simulator Message-ID: <004b01c86eca$d0a71880$71f54980$@edu> Hi all, I was wondering if anyone has a solar simulator available. Thanks. Paul -------------- next part -------------- An HTML attachment was scrubbed... URL: From xzhuang at stanford.edu Thu Feb 14 09:36:48 2008 From: xzhuang at stanford.edu (Steve Zhuang) Date: Thu, 14 Feb 2008 09:36:48 -0800 Subject: PhD oral defense (Tue, 2/19 2pm), Steve Zhuang Message-ID: <20080214093648.jf18daqgkkwcsogo@webmail.stanford.edu> Stanford University Ph.D. Oral Examination Xuefeng (Steve) Zhuang Department of Electrical Engineering Advisor: Professor Butrus T. Khuri-Yakub Date: Tuesday, February 19, 2008 Time: 2 PM (Refreshments served at 1:45 PM) Location: Packard room 202 Title: Capacitive Micromachined Ultrasonic Transducers (CMUTs) with Through-Wafer Interconnects Abstract: Capacitive micromachined ultrasonic transducer (CMUT) technology is a promising candidate for making 2D ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with front-end IC to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for 2D CMUT arrays, and many other types of MEMS devices. However, efforts to integrate the direct fusion bonding process with through-wafer via interconnects have been unsuccessful. The interconnect fabrication steps degrade the surface conditions of the wafer, making it difficult to bond. In this talk I present a new through-wafer interconnect technique that is compatible with MEMS device fabrication in general, including both the surface-micromachining and the direct fusion bonding processes. The new technique uses through-wafer trenches to separate array elements and utilizes the silicon substrate as the conductive electrode. Two exemplary implementations incorporating CMUT arrays are presented, one with a carrier wafer and the other with a built-in silicon frame structure for mechanical support. Both implementations reduce fabrication complexity compared to the through-wafer via process, and result in low series resistance and small parasitic capacitance. 2D CMUT arrays integrated with trench-isolated interconnects show high output pressure (2.9 MPa), wide bandwidth (95%), small pulse-echo amplitude variation (sigma = 6.6%), and excellent yield (100%). An important added benefit of the trench-isolated interconnect is the capability to realize flexible arrays, which is also discussed in the presentation. I will also demonstrate 3D ultrasound imaging based on a trench-isolated 2D array integrated with an IC. From pleu at stanford.edu Thu Feb 14 11:01:04 2008 From: pleu at stanford.edu (Paul Leu) Date: Thu, 14 Feb 2008 13:01:04 -0600 Subject: Solar cell testing apparatus Message-ID: <00a901c86f3b$f59140f0$e0b3c2d0$@edu> Hi all, Sorry for some of the confusion. I am looking for a light which approximates the solar spectrum to be used for solar cell testing. Preferably, this would be a setup with probe tips, but other setups may be workable. Please let me know if such a setup in your lab. Thanks. Paul -------------- next part -------------- An HTML attachment was scrubbed... URL: From hector at AsylumResearch.com Thu Feb 14 14:50:09 2008 From: hector at AsylumResearch.com (Hector Cavazos) Date: Thu, 14 Feb 2008 14:50:09 -0800 Subject: CoCr film removal Message-ID: <1JPmu9-0005Zc-Qo@exchange.AsylumResearch.com> Does anyone know how to remove CoCr films from silicon wafers? Any help would be appreciated. Thank you, Hector -------------- next part -------------- An HTML attachment was scrubbed... URL: From gsosa at stanford.edu Thu Feb 14 16:18:17 2008 From: gsosa at stanford.edu (Gary J Sosa) Date: Thu, 14 Feb 2008 16:18:17 -0800 Subject: Scheduled downtime for ASMl Stepper Message-ID: <20080214161817.16kxrtklws08k80g@webmail.stanford.edu> Hello Labmembers... This email is to inform you that the ASML Stepper will be down on Monday, February 25 from 8:00AM to 6:00PM to perform a scheduled monthly PM. There may be some additional time on the following day if we do not complete the PM in the scheduled time. Please make plans accordingly and sorry for the inconvenience. Thanks.. Gary From mtang at stanford.edu Thu Feb 14 18:49:34 2008 From: mtang at stanford.edu (Mary Tang) Date: Thu, 14 Feb 2008 18:49:34 -0800 Subject: Reminder: SNF Process Grand Rounds, Friday, 2/15, 11:30 Message-ID: <47B4FDBE.7080407@stanford.edu> Hi all -- Just a reminder of the Process Grand Rounds for Friday, 2/15, 11:30 in CIS 101. All are welcome to attend. On the agenda: 1. Wafer handling on the ASML (presented by the ASML Team) and update on action items from last Friday's brainstorming. 2. Brainstorming session on performance issues with STS etch (everyone is encouraged to bring data, recipes, etc.) 3. Quick 10 minute planning session for future Process Grand Rounds. As long as there are topics of interest, we'll keep holding them. If we can set agendas for the next few sessions, people can plan ahead and bring/prepare materials to share. Pizza will be provided. Hope to see you there! Your SNF Staff From rissman at stanford.edu Fri Feb 15 07:50:16 2008 From: rissman at stanford.edu (Paul Rissman) Date: Fri, 15 Feb 2008 07:50:16 -0800 Subject: Alarm inspections - Friday, 2/15 - 9 AM Message-ID: <200802151550.m1FFoMA1001050@smtp-roam.Stanford.EDU> Santa Clara County will be inspecting improvements which have been made to the toxic gas monitoring system this morning. There is the possibility that alarms may sound momentarily in the building due to the testing. Facilities will shut off any alarms caused by testing quickly. However, if you have any question whether the alarm is real or a test, don't hesitate to evacuate the building and check with staff on the actual status. >X-Sieve: CMU Sieve 2.3 >Delivered-To: rissman at stanford.edu >Delivered-To: rissman at snf.stanford.edu >From: "Leonard Chan" >To: , , > , "Ted Barg" , > "Ed Myers" >Subject: FW: Tomorrows inspection is a go >Date: Fri, 15 Feb 2008 07:14:50 -0800 >X-Mailer: Microsoft Outlook IMO, Build 9.0.6604 (9.0.2911.0) >X-PMX-Version: 5.3.0.289146, Antispam-Engine: 2.5.0.283055, >Antispam-Data: 2008.2.15.65944 >X-PerlMx-Spam: Gauge=IIIIIIII, Probability=8%, Report='HTML_50_70 >0.1, HTML_NO_HTTP 0.1, __C230066_P5 0, __CT 0, __CTYPE_HAS_BOUNDARY >0, __CTYPE_MULTIPART 0, __HAS_MSGID 0, __HAS_MSMAIL_PRI 0, >__HAS_X_MAILER 0, __HAS_X_PRIORITY 0, __HTML_FONT_BLUE 0, >__MIME_HTML 0, __MIME_VERSION 0, __SANE_MSGID 0, __TAG_EXISTS_HTML >0, __USER_AGENT_MS_GENERIC 0' > >To All, > >FYI.... the final County acceptance test for the phase 1 TGO project >will be done today. > >Thanks, > >Leonard >-----Original Message----- >From: David Boyanich [mailto:dboy at facilities-dynamics.us] >Sent: Thursday, February 14, 2008 3:43 PM >To: Leonard Chan >Cc: Aaron McCarthy >Subject: Tomorrows inspection is a go > >Leonard, > >I just confirmed with Rob Campbell of the County Fire Marshalls >office that we will still have an inspection at 9:00 am. Please >have a printed copy of the full test report that was performed in >December, and a printed copy of the current Matrix. I will arrive >around 8:00 to prepare. > >Best regards, > >David Boyanich >Managing Partner >Facilities Dynamics, Inc. >Cell Phone: (408) 690-5357 -------------- next part -------------- An HTML attachment was scrubbed... URL: From jerabek at snf.stanford.edu Fri Feb 15 08:56:02 2008 From: jerabek at snf.stanford.edu (Paul Jerabek) Date: Fri, 15 Feb 2008 08:56:02 -0800 Subject: Mask making Message-ID: <001301c86ff3$aaed17a0$916540ab@czech1> To whom it may concern: as many of you already know I will be retiring at the end of this month and Micronic Laser writer will be shut down. Therefore as of this day I will no longer accept any new mask orders and will finish those already submitted. -Paul J. -------------- next part -------------- An HTML attachment was scrubbed... URL: From pease at cis.stanford.edu Fri Feb 15 10:50:22 2008 From: pease at cis.stanford.edu (Fabian Pease) Date: Fri, 15 Feb 2008 10:50:22 -0800 Subject: Mask making In-Reply-To: <001301c86ff3$aaed17a0$916540ab@czech1> References: <001301c86ff3$aaed17a0$916540ab@czech1> Message-ID: <47B5DEEE.9050000@cis.stanford.edu> Paul Jerabek wrote: > To whom it may concern: > as many of you already know I will be retiring at the end of this > month and Micronic Laser writer will be shut down. > Therefore as of this day I will no longer accept any new mask orders > and will finish those already submitted. > -Paul J. This the end of an era that started in early1982 when MEBES was (finally) brought on line in the McCullough basement and Paul started producing masks for all of us. We owe him a big vote of thanks and a fine send-off. Fabian Pease From rissman at stanford.edu Fri Feb 15 13:39:44 2008 From: rissman at stanford.edu (Paul Rissman) Date: Fri, 15 Feb 2008 13:39:44 -0800 Subject: Alarm inspections complete Message-ID: <200802152139.m1FLdsv5021009@smtp-roam.Stanford.EDU> All alarm inspections are complete. Please assume that any alarm is real and take action to evacuate if appropriate. >X-Sieve: CMU Sieve 2.3 >Delivered-To: rissman at stanford.edu >Delivered-To: rissman at snf.stanford.edu >From: "Leonard Chan" >To: , , > , "Ted Barg" , > "Ed Myers" >Subject: FW: Tomorrows inspection is a go >Date: Fri, 15 Feb 2008 07:14:50 -0800 >X-Mailer: Microsoft Outlook IMO, Build 9.0.6604 (9.0.2911.0) >X-PMX-Version: 5.3.0.289146, Antispam-Engine: 2.5.0.283055, >Antispam-Data: 2008.2.15.65944 >X-PerlMx-Spam: Gauge=IIIIIIII, Probability=8%, Report='HTML_50_70 >0.1, HTML_NO_HTTP 0.1, __C230066_P5 0, __CT 0, __CTYPE_HAS_BOUNDARY >0, __CTYPE_MULTIPART 0, __HAS_MSGID 0, __HAS_MSMAIL_PRI 0, >__HAS_X_MAILER 0, __HAS_X_PRIORITY 0, __HTML_FONT_BLUE 0, >__MIME_HTML 0, __MIME_VERSION 0, __SANE_MSGID 0, __TAG_EXISTS_HTML >0, __USER_AGENT_MS_GENERIC 0' > >To All, > >FYI.... the final County acceptance test for the phase 1 TGO project >will be done today. > >Thanks, > >Leonard >-----Original Message----- >From: David Boyanich [mailto:dboy at facilities-dynamics.us] >Sent: Thursday, February 14, 2008 3:43 PM >To: Leonard Chan >Cc: Aaron McCarthy >Subject: Tomorrows inspection is a go > >Leonard, > >I just confirmed with Rob Campbell of the County Fire Marshalls >office that we will still have an inspection at 9:00 am. Please >have a printed copy of the full test report that was performed in >December, and a printed copy of the current Matrix. I will arrive >around 8:00 to prepare. > >Best regards, > >David Boyanich >Managing Partner >Facilities Dynamics, Inc. >Cell Phone: (408) 690-5357 -------------- next part -------------- An HTML attachment was scrubbed... URL: From shott at stanford.edu Sat Feb 16 11:04:52 2008 From: shott at stanford.edu (John Shott) Date: Sat, 16 Feb 2008 11:04:52 -0800 Subject: Computer outage early Sunday morning 2/17 .... Message-ID: <47B733D4.5090600@stanford.edu> SNF Lab Members: The Sunrays and the SNF Mail Server/Web Site will be down early Sunday morning for a period of several hours starting at about 4:30 a.m. The purpose of this downtime will be to move home directories to a new file system that will: 1. Provide somewhat more disk space so that we are not so close to 100% on the /home/User partition (once again we are hovering between 99% and 100% on that system). 2. Allow us to increase the size of that partition "on the fly" if/when we need to do so in the future. 3. Provide better redundancy in the event of a disk crash. 4. Provide somewhat faster performance. To do this, however, we have to shutdown key systems so that incoming mail messages, browser caches, and file edits do not thwart our attempts to synchronize the old file system with the new file system. So, starting in the very early hours on Sunday morning, the Sunrays in the lab, the SNF mail system, and the SNF web site will be down for what I expect to be a period of several hours while we move/synchronize these file systems. During that time, Remote Coral should be available the entire time. Also, I will be available either in CIS 220 or my office (CIS 129, x5-3715) in case you need to contact me to enable or disable a tool. The Coral servers will be fully functional during that time. We apologize for this inconvenience but hope that this has been schedule so as to provide minimal disruption. Thank you for your continued support, John From serenaf at stanford.edu Sun Feb 17 12:04:38 2008 From: serenaf at stanford.edu (Serena Faruque) Date: Sun, 17 Feb 2008 12:04:38 -0800 Subject: Dyes Message-ID: <602AC16F-CD2B-4F5D-869D-AEC678C2D78A@stanford.edu> On rather short notice, we were wondering where to acquire a dye molecule such as rhodamine 6G or DCM. We will, of course, replace the chemical as soon as possible. Thank you! Serena Serena Faruque Center for Integrated Systems, CISX-213A 330 Serra Mall Stanford, CA 94305-4470 serenaf at stanford.edu Office: (650) 725 - 6924 Cell: (650) 387-9834 -------------- next part -------------- An HTML attachment was scrubbed... URL: From xzhuang at stanford.edu Mon Feb 18 10:33:51 2008 From: xzhuang at stanford.edu (Steve Zhuang) Date: Mon, 18 Feb 2008 10:33:51 -0800 Subject: Reminder: University PhD Dissertation Defense / Xuefeng (Steve) Zhuang (Tue, Feb. 19) Message-ID: <20080218103351.wvvrd7tj444s44o0@webmail.stanford.edu> Stanford University Ph.D. Oral Examination Xuefeng (Steve) Zhuang Department of Electrical Engineering Advisor: Professor Butrus T. Khuri-Yakub Date: Tuesday, February 19, 2008 Time: 2 PM (Refreshments served at 1:45 PM) Location: Packard room 202 Title: Capacitive Micromachined Ultrasonic Transducers (CMUTs) with Through-Wafer Interconnects Abstract: Capacitive micromachined ultrasonic transducer (CMUT) technology is a promising candidate for making 2D ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with front-end IC to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for 2D CMUT arrays, and many other types of MEMS devices. However, efforts to integrate the direct fusion bonding process with through-wafer via interconnects have been unsuccessful. The interconnect fabrication steps degrade the surface conditions of the wafer, making it difficult to bond. In this talk I present a new through-wafer interconnect technique that is compatible with MEMS device fabrication in general, including both the surface-micromachining and the direct fusion bonding processes. The new technique uses through-wafer trenches to separate array elements and utilizes the silicon substrate as the conductive electrode. Two exemplary implementations incorporating CMUT arrays are presented, one with a carrier wafer and the other with a built-in silicon frame structure for mechanical support. Both implementations reduce fabrication complexity compared to the through-wafer via process, and result in low series resistance and small parasitic capacitance. 2D CMUT arrays integrated with trench-isolated interconnects show high output pressure (2.9 MPa), wide bandwidth (95%), small pulse-echo amplitude variation (sigma = 6.6%), and excellent yield (100%). An important added benefit of the trench-isolated interconnect is the capability to realize flexible arrays, which is also discussed in the presentation. I will also demonstrate 3D ultrasound imaging based on a trench-isolated 2D array integrated with an IC. From mbaran at stanford.edu Tue Feb 19 15:59:14 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 19 Feb 2008 15:59:14 -0800 Subject: Yet Another Cell Phone Found in the Ladies Room Across from the Lab Message-ID: <20080219235914.E0C9D60E93C@smtp3.stanford.edu> Another cell phone has been left behind in the ladies room, across from the Lab, on the first floor of the CIS building. If this is your phone, please stop by my cubicle. I will be leaving today at 5:00P today. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Tue Feb 19 15:53:05 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 19 Feb 2008 15:53:05 -0800 Subject: Found Watch - Between the CIS Bldg & Ginzton Lab Message-ID: <20080219235306.035C860E86E@smtp3.stanford.edu> This watch was found a couple of weeks ago and just handed in today. If you misplaced your watch between the CIS building and Ginzton Lab, please come by my cubicle, it's number 41 on the first floor of the CIS building, closest to the doors that face the Applied Physics building. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From jprovine at stanford.edu Tue Feb 19 19:14:43 2008 From: jprovine at stanford.edu (J Provine) Date: Tue, 19 Feb 2008 19:14:43 -0800 Subject: SEMINAR: Prof. Heuer on Silicon Mechanical Fatigue Packard 101 2.21 9am Message-ID: <20080219191443.w9w5cqiihsg884sw@webmail.stanford.edu> Hello everyone, please pardon the mass email, but there is a seminar that I believe would be widely interesting to the SNF community, in particular anyone doing MEMS/NEMS. Prof. Heuer from Case Western Reserve will give a seminar on "Mechanical Fatigue in Polysilicon" at 9am (NOTE the early start time) February 21 (Thursday) in Packard 101. Thanks, ~j -------------- next part -------------- A non-text attachment was scrubbed... Name: AH.Heuer.Feb08.doc Type: application/msword Size: 98304 bytes Desc: not available URL: From mtang at stanford.edu Tue Feb 19 21:40:30 2008 From: mtang at stanford.edu (Mary Tang) Date: Tue, 19 Feb 2008 21:40:30 -0800 Subject: SNF Process Grand Rounds: Special Edition, Friday, 2/22 Message-ID: <47BBBD4E.4060408@stanford.edu> Hi everyone -- Minutes from the last Process Grand Rounds have been posted (linked from the SNF home page.) For those in attendance, please let me know if we've missed something or any other corrections that may be required. The next SNF Process Grand Rounds will be Friday, 2/22, 11:30-1 pm, in CIS 101. The main topic will be a planning meeting for what we're calling "Superuser" and "Quality Circle" programs which grew out of discussions that Prof. Nishi and several other faculty have had over the past few weeks with concerned students about the state of the lab. The objective of this meeting is to define a framework for labmembers to become more involved and have more say in the lab operations -- and better work with the SNF staff to set expectations and lab priorities. All labmembers (and staff members) are welcome. But please be aware that the core group of students who have met with Prof. Nishi have already volunteered and invested much time in discussions with each other, their PI's and staff about their ideas. We would like to make this a productive meeting and so ask that anyone who attends should also be prepared to participate and volunteer (no spectators, please!) And we'd like to encourage everyone to talk with staff and each other -- and bring constructive ideas to the table. Looking forward to seeing you there! Your SNF staff From mtang at stanford.edu Tue Feb 19 21:47:27 2008 From: mtang at stanford.edu (Mary Tang) Date: Tue, 19 Feb 2008 21:47:27 -0800 Subject: [POSSIBLE VIRUS:###] Warning: Watch your Email Message-ID: <47BBBEEF.1040704@stanford.edu> Hi everyone -- If you see a message like this one (CONFIRM YOUR SUNet EMAIL ACCOUNT) - DON'T REPLY! It's a phishing expedition for your personal info. John passed on a warning about this happening at other universities -- looks like they're hitting Stanford now: http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:3036:200801:phkcedhhcfanjhglhamj And always be careful about your personal info.... Your Coral staff -------------- next part -------------- An embedded message was scrubbed... From: SUNet Team Subject: CONFIRM YOUR SUNet EMAIL ACCOUNT Date: Tue, 19 Feb 2008 20:34:13 -0500 Size: 2906 URL: From shott at stanford.edu Wed Feb 20 06:57:30 2008 From: shott at stanford.edu (John Shott) Date: Wed, 20 Feb 2008 06:57:30 -0800 Subject: No acid dumping this morning .... Message-ID: <47BC3FDA.5090808@stanford.edu> SNF Lab Members: I have just received word from FacOps that our supply of sodium hydroxide that is used in the acid neutralization system is virtually exhausted. The truck that will re-supply that tank should be arriving this morning. For the moment, however, we must ask that you not dump any acids this morning until we send out the "all clear". Dumping of unneutralized acid would cause us to be in violation of environmental waste regulations. We apologize for this inconvenience but appreciate your support. Thanks, John From shott at stanford.edu Wed Feb 20 09:28:28 2008 From: shott at stanford.edu (John Shott) Date: Wed, 20 Feb 2008 09:28:28 -0800 Subject: Acid Waste system is functional again ... Message-ID: <47BC633C.3060806@stanford.edu> SNF Lab Members: The bulk sodium hydroxide for the acid neutralization system has been refilled and normal operations may now resume. Thank you for your support, John From gthareja at stanford.edu Wed Feb 20 15:13:01 2008 From: gthareja at stanford.edu (gthareja at stanford.edu) Date: Wed, 20 Feb 2008 15:13:01 -0800 Subject: lost power chord for the projector. Message-ID: <20080220151301.0ceppc7hnkgk8044@webmail.stanford.edu> Dear labmembers. We were having a presentation in CIS-201 (the presentation room next to Prof. Simon Wong's office) on Feb 8 (Friday). I accidentally left the projector power chord in that room. Please let me know if any one of you found the power chord. thanks -gaurav 650-704-1029 Prof. Nishi group From mtang at stanford.edu Wed Feb 20 17:23:58 2008 From: mtang at stanford.edu (Mary Tang) Date: Wed, 20 Feb 2008 17:23:58 -0800 Subject: SNF Enterprise Forum, Wed. 3/5, 4 pm, CIS 101 Message-ID: <47BCD2AE.5050402@stanford.edu> Greetings labmembers -- As part of our enterprise forum series, we are hosting a visit by Shahin Farschi, from Lux Capital. Following a brief presentation, Shahin is most interested in an informal discussion with researchers about the role of VC's in developing new opportunities. This is scheduled for Wednesday, March 5, from 4-5 pm in CIS 101. Shahin invites advance suggestions for specific topics of discussion -- just email him at the address below. Shahin's talk will be on the following: The role of venture capital in the success of today's technology startups Abstract: Ever-increasing market competition and narrow market windows further exacerbate the challenge of commercializing a novel semi/device technology. These circumstances have altered the relationship between investors and entrepreneurs, from one where investors are passive explorers of new opportunities presented by entrepreneurs, to one where entrepreneurs and investors work together to find a timely development path to a market that would best leverage an innovation. This seminar will introduce the audience to several examples of how venture investors can assist innovators at the very early stage, which will be followed by a Q&A session. Background: Shahin Farshchi is an associate at Lux Capital, a venture capital firm that invests in early-stage semiconductor, energy, materials, and biotechnology companies, where he assists in the creation and evaluation of semiconductor and energy-related companies for investment. Shahin earned his B.S. from the University of California at Berkeley, followed by his M.S. and Ph.D. degrees in Electrical Engineering with a focus on MEMS and analog IC design from the University of California at Los Angeles. Shahin Farshchi, Ph.D. Associate Lux Capital Management, LLC T: 925.323.2784 http://www.luxcapital.com shahin.farshchi at luxcapital.com -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From candacec at stanford.edu Thu Feb 21 13:12:36 2008 From: candacec at stanford.edu (Candace Kay Chan) Date: Thu, 21 Feb 2008 13:12:36 -0800 Subject: polyimide on Si? Message-ID: <47BDE944.5040809@stanford.edu> Hi all, Does anyone have experience with liquid polyimide and adhesion to Si (with native oxide)? In particular I am looking for as low a Tg as possible (200C would be nice). I've been trying to call Dupont but have been having trouble reaching an actual person. Thanks in advance, Candace -- Candace K. Chan Ph.D. Student, Department of Chemistry Stanford University McCullough Building Room 209 476 Lomita Mall Stanford, CA 94305 -------------- next part -------------- An HTML attachment was scrubbed... URL: From swlee49 at stanford.edu Fri Feb 22 07:28:51 2008 From: swlee49 at stanford.edu (Seok-Woo Lee) Date: Fri, 22 Feb 2008 07:28:51 -0800 Subject: coarse grained polycrystallne Cadmium? Message-ID: <000001c87567$a0c93000$e25b9000$@edu> Hi all, Does anyone have experience with polycrystalline Cadmium (high purity)? I am looking for coarse grained cadmium (about ~1mm size of grains) because I want to see some mechanical behaviors with different crystallographic orientations. It's not easy for me to find cadmium 'with coarse grain size'. Thanks in advance, Seok-Woo Lee -- Seok-Woo Lee Ph.D. Student, Department of Materials Science and Engineering Stanford University Peterson Building Room 554G Stanford, CA 94305 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Fri Feb 22 10:42:45 2008 From: mtang at stanford.edu (Mary Tang) Date: Fri, 22 Feb 2008 10:42:45 -0800 Subject: DI Water Shutdown this morning Message-ID: <47BF17A5.3010806@stanford.edu> Sorry all -- The building has run out of DI water. According to Facilities Ops, the pump for the DI water system has failed The backup is in the process of getting preventive maintenance and so is not online yet. FacOps is working on this right now and will update us soon. In the meantime, there is no DI water available. At SNF, all equipment requiring DI water for operation has been shutdown. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Fri Feb 22 11:30:25 2008 From: mtang at stanford.edu (Mary Tang) Date: Fri, 22 Feb 2008 11:30:25 -0800 Subject: DI Water update, 11:20 am Message-ID: <47BF22D1.9090501@stanford.edu> Hi all -- Leonard Chan reports that both DI pumps are not functional. He is working on getting a functional one delivered and installed, with the goal of having something in place and working by end of today. Stay tuned for more. SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Fri Feb 22 14:05:43 2008 From: mtang at stanford.edu (Mary Tang) Date: Fri, 22 Feb 2008 14:05:43 -0800 Subject: DI Water!!! Message-ID: <47BF4737.90401@stanford.edu> We have DI water! Apologies for misinformation before -- CISX did not lose DI water, only SNF did. Now (cross fingers) both CISX and SNF have DI water. FacOps is working on getting all the pumps repaired. -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From nayoung at stanford.edu Sun Feb 24 21:04:32 2008 From: nayoung at stanford.edu (Na Young Kim) Date: Sun, 24 Feb 2008 21:04:32 -0800 Subject: short channel Si-MOSFET vendors Message-ID: <20080224210432.39ifmgba8g0w4wg8@webmail.stanford.edu> Dear Labmembers, I am looking for short channel (< 1um) Si (single-crystal) MOSFET devices (n-channel/p-channel enhancement mode). I prefer chip FETs to packaged FETs if possible and would like to know the doping concentration. If you know and share the information of vendors and sources with me, I really appreciate it. Thanks, Na Young From shott at stanford.edu Mon Feb 25 09:54:38 2008 From: shott at stanford.edu (John Shott) Date: Mon, 25 Feb 2008 09:54:38 -0800 Subject: Possible vibration Tuesday morning .... Message-ID: <47C300DE.7070005@stanford.edu> SNF Lab Members: In order to attach two computer racks to the floor, we need to drill a total of 8 holes in the concrete using the RotoHammer. While this should be isolated from the lab by virtue of being on a separate foundation, it could conceivably cause a bit of vibration. In order to minimally inconvenience normal lab activiities .... not to mention the folks that have offices near the first-floor communication closet ... we will plan to do this early tomorrow morning (Tuesday, February 26) starting at about 6 a.m. with the expectation of being completed by 7 a.m. As a second item, Jim Kruger made the suggestion that it would be useful to have some form of identification on the Sun Rays when reporting problems related to keyboards, mice, etc. This is a good suggestion and we have numbered each Sun Ray with a number from 1 to 25 that you can use when reporting problems. For the Sun Ray 1s, this number is on the body of the Sun Ray just above the slot where you insert a smart card. Thank you for your continued support, John From Jfu at exponent.com Mon Feb 25 11:02:20 2008 From: Jfu at exponent.com (Jason Fu) Date: Mon, 25 Feb 2008 11:02:20 -0800 Subject: AFM2 In-Reply-To: <47C300DE.7070005@stanford.edu> Message-ID: <113F6EB3099A9945ACB6B6AD8F7A3909019699D0@EXCHANGE0.exponent.com> Hi, Sorry to send the message to the whole lab instead of only people using AFM2. After spending almost an hour with Ed this morning on the machine to figure out the optical microscope may have problem, just checking with other AFM users in the lab to see if and when other people noticed the same problem. The symptoms are: when engaging the tip, tip scanning started and the tip image was NOT in focus shown on the monitor screen. Since this problem has not been reported on Coral before, please let me know if you are a AFM user and saw this recently. Especially for people using AFM recently, please let me know if your scan looks normal. Users: nppatil, libei, donghun, koba, munehiro, please reply. Appreciated your time and reply! Thanks, Jason From edmyers at stanford.edu Mon Feb 25 12:47:09 2008 From: edmyers at stanford.edu (Ed Myers) Date: Mon, 25 Feb 2008 12:47:09 -0800 Subject: Mask Making Seminar and Q/A session Message-ID: <6.2.5.6.2.20080225124017.0410b2a8@stanford.edu> Lab Members, Bill Martin, who represents Compugraphics will be on campus this week. He is holding a seminar along with a question and answer session on Tuesday, Feb. 26th, beginning at 1pm in CIS101. This will be an ideal time to stop in and learn the new procedure for having mask made at Compugraphics. The objective, is by the end of the day, to have a thorough understanding of the mask submission process, beginning with the design requirements and ending with a mask in you hands. Please join us with all of the mask making questions you might have. Regards, Ed From mtang at stanford.edu Mon Feb 25 13:58:24 2008 From: mtang at stanford.edu (Mary Tang) Date: Mon, 25 Feb 2008 13:58:24 -0800 Subject: Power Glitch this morning Message-ID: <47C33A00.6010505@stanford.edu> Hi all -- Just wanted to let you know -- there was a power glitch this morning around 7:30 am. Most of you probably didn't notice it, since the maintenance crew quickly descended on the lab and reset/checked everything. The cause turns out to have been a downed 16 KV PG&E power line. Please be aware that it is possible there may still be lasting effects (lost recipes, for example) -- if you have any problems, log them onto Coral and notify staff. Thanks, Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From aeonia at stanford.edu Mon Feb 25 17:34:22 2008 From: aeonia at stanford.edu (aeonia at stanford.edu) Date: Mon, 25 Feb 2008 17:34:22 -0800 Subject: University Ph.D. Oral Examination : Hyeun-Su Kim at CISX Aud, Feb. 29th 8:30am Message-ID: <20080225173422.whfa2yf1xc8k4wwg@webmail.stanford.edu> Stanford University Ph.D. Oral Examination Hyeun-Su Kim Department of Mechanical Engineering Adviser: Thomas W. Kenny February 29st, 2008 8:30AM (Refreshments served at 8:15AM) CIS-X Auditorium "A Variable Thermal Resistor (VTR) for Low Power Temperature Regulation of Chip-Scale Atomic Clock (CSAC)" Abstract: It is essential for a chip-scale atomic clock (CSAC) development to make an efficient thermal isolation structure as well as to use low power for temperature controlling due to the low-power requirements (near 30mW total power consumption in the presence of -40~50?C of ambient temperature variation). There have been several efforts on the thermal management of a CSAC to keep the temperature of a vapor cell in a CSAC at 75?C with low power using thermal isolation structures; however, this is the first study that shows the ability of thermal resistance change in multiple stages to control a CSAC temperature in a range of ambient temperature variation. We developed a variable thermal resistor (VTR) for the purpose of changing the thermal resistance of a CSAC package according to the ambient temperature variation. The current VTR is comprised of thermal isolation structures (polyimide posts) and an array of ten electrostatic actuators (suspended gold beams). The top silicon die which has ground electrode for vertical electrostatic actuator is separated by three 30um tall polyimide posts. Ten 1.6um thick gold suspended beams are placed between the top and the bottom dies while they keep the distance to the top die 5?1um at zero bias. When 100V of electrical potential is applied to the gold beams, they bend up and make contact with the top die. As a consequence, the thermal resistance of VTR decreases. The 0.5um SiO2 passivation layer on the top die prevents electrical contact between ground electrode and the gold beams. In addition to the current design of VTR, we also discuss passive actuation type VTR which is actuated by the ambient temperature variation. An improved thermal resistance measurement method we have developed is also introduced and evaluated. The current version of VTR demonstrates thermal resistance variation from 200?C/W to 1200?C/W with 100?20?C/W of resolution. As a room temperature thermal switch that deals with low heat load, VTR may serve as a high thermal resistance package solution for any low- power and high-temperature electric device. From mbaran at stanford.edu Tue Feb 26 15:53:05 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 26 Feb 2008 15:53:05 -0800 Subject: OOPS! Found Black Knit Sweater with Gray Piping on Bench Outside the Lab Message-ID: <20080226235305.CA525270283@smtp1.stanford.edu> Dear Labmembers, I apologize for the last (blank) note. Found Women's Black Knit Sweater with Gray Piping on the bench outside the lab. This sweater has been sitting there for a couple of weeks. If this is your sweater please come to my cubicle # 41 to pick it up. Thanks, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Thu Feb 28 10:58:52 2008 From: mtang at stanford.edu (Mary Tang) Date: Thu, 28 Feb 2008 10:58:52 -0800 Subject: Special SNF Event: 1 pm today, in the lab Message-ID: <47C7046C.90808@stanford.edu> Greeting Labmembers: It's the end of an age for SNF.... where we say "goodbye" to convenient, expert in-house maskmaking, reliable service against all odds, and a solid presence in the lab... Please join us as we say "goodbye" to.... the Micronics Laser Maskwriter. At one pm today, Paul Jerabek will flip the four switches that give life to this system. This is an end of an age. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Thu Feb 28 11:11:55 2008 From: mtang at stanford.edu (Mary Tang) Date: Thu, 28 Feb 2008 11:11:55 -0800 Subject: Process Grand Rounds, Friday, 2/29, 11:30 am Message-ID: <47C7077B.1010601@stanford.edu> Hi again -- The next installment of the Process Grand Rounds will be Friday, 2/29, at 11:30 in CIS 101. On the agenda: 1. Process issues anyone wishes to present (Maryam?) (10 min?) 2. Follow up on action items from previous Grand Rounds. (5 min) 3. Reports from each of the functional area "quality circles" regarding the data each group would like collected and reported. John will not be here, but Bill Murray will try to make it. It would also be valuable for groups to share their proposals to come up with a somewhat unified lab vision of what we'd like data collection and reporting to be. 4. Group discussion to determine the objectives/action items for the next round of Quality Circle activities. All labmembers are welcome. This time, pizza. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From jameson at stanford.edu Thu Feb 28 13:44:47 2008 From: jameson at stanford.edu (John Ross Jameson) Date: Thu, 28 Feb 2008 13:44:47 -0800 (PST) Subject: HP 4145A needs repair Message-ID: <200802282144.m1SLilTX020811@elaine22.Stanford.EDU> Hi Labmembers, I have a broken HP 4145A that I'd like to have repaired. Does anyone know anyone who does this? HP and Agilent no longer support the 4145A in any way. I'm hoping to find a retired HP engineer, maybe even someone who worked on the 4145A itself back in the day. Thanks, John From markphillips at sbamaterials.com Thu Feb 28 14:01:24 2008 From: markphillips at sbamaterials.com (Mark L F Phillips) Date: Thu, 28 Feb 2008 14:01:24 -0800 Subject: HP 4145A needs repair In-Reply-To: <200802282144.m1SLilTX020811@elaine22.Stanford.EDU> References: <200802282144.m1SLilTX020811@elaine22.Stanford.EDU> Message-ID: <5b4c2379f860c783e43561fbd5d5bcfb@sbamaterials.com> Hi John, try OpLink Solutions in GA (www.oplinksolutions.com). They support the HP 4145a. they recently rebuilt a HP LCR meter that I thought was beyond repair, and at reasonable cost. Best, Mark On Feb 28, 2008, at 1:44 PM, John Ross Jameson wrote: > Hi Labmembers, > > I have a broken HP 4145A that I'd like to have repaired. > Does anyone know anyone who does this? HP and Agilent no > longer support the 4145A in any way. I'm hoping to find > a retired HP engineer, maybe even someone who worked on the > 4145A itself back in the day. > > Thanks, > John > From ebasham32 at earthlink.net Thu Feb 28 14:43:25 2008 From: ebasham32 at earthlink.net (Eric) Date: Thu, 28 Feb 2008 14:43:25 -0800 Subject: HP 4145A needs repair In-Reply-To: <200802282144.m1SLilTX020811@elaine22.Stanford.EDU> References: <200802282144.m1SLilTX020811@elaine22.Stanford.EDU> Message-ID: <002301c87a5b$5506c9e0$ff145da0$@net> I have used Calwright for several pieces of older HP equipment. The 4145A shouldn't be a problem for them. What is the "broken" condition? You might find a less damaged system on ebay or used-line that would only need calibration. There is also a shop on the east coast, but shipping can be prohibitive. Eric Calright Instruments David Swanson 2232 Verus Street, Suite D San Diego, CA 92154 USA 866.363.6634 Toll Free 619.374.7012 Fax sales at calright.com www.calright.com -----Original Message----- From: John Ross Jameson [mailto:jameson at stanford.edu] Sent: Thursday, February 28, 2008 1:45 PM To: labmembers at snf.stanford.edu Subject: HP 4145A needs repair Hi Labmembers, I have a broken HP 4145A that I'd like to have repaired. Does anyone know anyone who does this? HP and Agilent no longer support the 4145A in any way. I'm hoping to find a retired HP engineer, maybe even someone who worked on the 4145A itself back in the day. Thanks, John From jameson at stanford.edu Thu Feb 28 16:48:17 2008 From: jameson at stanford.edu (John Ross Jameson) Date: Thu, 28 Feb 2008 16:48:17 -0800 (PST) Subject: Summary: HP 4145A needs repair Message-ID: <200802290048.m1T0mIHb027446@elaine5.Stanford.EDU> Hi, In response to my question about where to get an HP 4145A fixed, several users said they'd also like to know where to fix old HP equipment, so here's a summary of the responses so far: * One SNFer sent a 4195A to Tucker electronics in Texas. * Another SNFer said OpLink Solutions in GA (www.oplinksolutions.com) supports the HP 4145A. * Another SNFer has used Calwright for several pieces of older HP equipment, and thinks the 4145A "shouldn't be a problem for them." * One SNFer said go to www.testlabco.com * Finally, ever the comedian, Josh Ratchford said "I'll fix it for $100k." As a side note, I priced out "new" HP 4145As, and they seem to go for $7.5-10k. John From kattsai at stanford.edu Thu Feb 28 21:12:58 2008 From: kattsai at stanford.edu (Katherine Tsai) Date: Thu, 28 Feb 2008 21:12:58 -0800 Subject: does anyone have a mask with large beams? Message-ID: <1c62e49d0802282112v14408cafmace632518ce959a7@mail.gmail.com> Hi all, Does anyone have a mask with beams or inverted beams (length is not critical, but width needs to be > 50 um; see attached drawing) that I could borrow to test my process in the next couple days? Thanks in advance! Thanks, Katherine Tsai -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: beams.JPG Type: image/jpeg Size: 20930 bytes Desc: not available URL: From kcrabb at stanford.edu Thu Feb 28 17:15:38 2008 From: kcrabb at stanford.edu (Kevin Crabb) Date: Thu, 28 Feb 2008 17:15:38 -0800 Subject: Ferric Chloride (FeCl3) Etch Mask? In-Reply-To: <200802290048.m1T0mIHb027446@elaine5.Stanford.EDU> Message-ID: <002801c87a70$98ae8880$3a2742ab@delllaptop> Hello, I'm hoping to etch patterns into/through copper, nickel, and/or aluminum foils using an aqueous solution of FeCl3. I was wondering if anybody has any experience etching any metals with FeCl3, and which masks work for this process. Any help would be greatly appreciated! Thanks, Kevin kcrabb at stanford.edu From James.Q.Liu at jdsu.com Fri Feb 29 11:33:45 2008 From: James.Q.Liu at jdsu.com (James Q. Liu) Date: Fri, 29 Feb 2008 11:33:45 -0800 Subject: Ferric Chloride (FeCl3) Etch Mask? In-Reply-To: <002801c87a70$98ae8880$3a2742ab@delllaptop> References: <200802290048.m1T0mIHb027446@elaine5.Stanford.EDU> <002801c87a70$98ae8880$3a2742ab@delllaptop> Message-ID: <0FC4C1B93D218E428D20BFCB9424D5D205AA2680@SJEXCH02.ds.jdsu.net> I have used FeCl3 to etch InP anisotropically in the past. The mask was the plated gold pad. The collimated UV light was used to guide the etching. Proper agitation of FeCl3, or the sample rotation in my case, was important. Hope it helps. James -----Original Message----- From: Kevin Crabb [mailto:kcrabb at stanford.edu] Sent: Thursday, February 28, 2008 5:16 PM To: labmembers at snf.stanford.edu Subject: Ferric Chloride (FeCl3) Etch Mask? Hello, I'm hoping to etch patterns into/through copper, nickel, and/or aluminum foils using an aqueous solution of FeCl3. I was wondering if anybody has any experience etching any metals with FeCl3, and which masks work for this process. Any help would be greatly appreciated! Thanks, Kevin kcrabb at stanford.edu From bli003 at student.ucr.edu Fri Feb 29 11:55:59 2008 From: bli003 at student.ucr.edu (bli003 at student.ucr.edu) Date: Fri, 29 Feb 2008 11:55:59 -0800 (PST) Subject: does anyone have heavily-doped Si substrate? Message-ID: <20080229115559.BTJ12083@smh.ucr.edu> I'd like to borrow two heavily-doped n-Si(100) wafer, which is not carried in the stock room. I will appreciate if I can borrow it by tonight. Thank you, Bei ============================== Graduate Student QSL Lab.,EngrII 228 Dept.of Electrical Engineering University of California Riverside, CA 92521 Ph.# (951) 827-6275 Fax# (951) 827-2425 http://qsl.ee.ucr.edu/ ============================== From jwc at snf.stanford.edu Fri Feb 29 11:24:39 2008 From: jwc at snf.stanford.edu (James Conway) Date: Fri, 29 Feb 2008 11:24:39 -0800 Subject: Special Ebeam Lab Presentation: Chemically Amplified Molecular Resists for E-Beam Lithography , Dr. Alex Robinson University of Birmingham, UK. Tuesday March 4 , 20081:30 PM CIS 101 Message-ID: <47C85BF7.6040608@snf.stanford.edu> *Special Ebeam Lab Presentation: Chemically Amplified Molecular Resists for E-Beam Lithography Dr. Alex P.G. Robinson University of Birmingham, UK. Tuesday March 4, 2008 1:30 PM in CIS 101* *It is my pleasure to announce that Dr. Alex P.G. Robinson will be visiting the Stanford Nanofabrication Facility next Tuesday afternoon and will present his work on Chemically Amplified Molecular Resists. He has also promised to give us an introduction and an update on activities at the Nanoscale Physics Research Laboratory at the **University of Birmingham. All interested parties are invited to attend. There will be ample time for discussions after his presentation and we have the room through 3 PM. James W. Conway Ebeam Lab Stanford Nanofabrication Facility 650-725-7075 ------------------------------------------------------- * *Chemically Amplified Molecular Resists for E-Beam Lithography*** J. Manyam^a , F.P. Gibbons^a , S. Diegoli^b , M. Manickam^b , J.A. Preece^b , R.E. Palmer^a , _A.P.G. Robinson_^a / / ^a Nanoscale Physics Research Laboratory, School of Physics and Astronomy, The University of Birmingham, Birmingham, B15 2TT, UK phone: +44 (0)121 414 4641 e-mail: a.p.g.robinson at bham.ac.uk ^b School of Chemistry, The University of Birmingham, Birmingham, B15 2TT, UK Key words: Electron Beam Lithography, Molecular Resist, Fullerene, Chemically Amplified Resist The minimum lithographic feature size for microelectronic fabrication continues to shrink, and resist properties are beginning to dominate the achievable resolution. There is a strong need for a high resolution, high sensitivity resist for the 32 nm node, and beyond, that is not met by conventional polymeric resists at this time. The line width roughness (LWR) requirements at the 32 nm node [1] are already equal to the radius of gyration of a typical resist polymer, [2] whilst the resolution itself will be less than the polymer molecule size at future nodes. Molecular resists, such as oglimers and molecular glasses rely on smaller molecules, giving the potential for lower LWR and improved resolution. Fullerene derivative molecules have a diameter of approximately 1 nm and have been shown to act as negative tone resists with high etch durability and a resolution of 10 nm when exposed via electron beam lithography. However, the sensitivity of such resists is extremely poor and significant improvements would have to be made to make the material commercially viable. A common way to improve resist sensitivity is chemical amplification (CA) by addition of a photosensitizer, and optionally a cross-linker. Here we present a fullerene based three component chemically amplified resist system, which shows high resolution and sensitivity, wide process latitude, and etch durability comparable with commercial novolac resists. Fullerene resist films were prepared on hydrogen terminated silicon by spin coating and were irradiated using a Philips XL30SFEG scanning electron microscope equipped with a Raith lithography system. The fullerene CA resist consisted of the derivative MF03-04, an epoxide cross-linker and a photoacid generator. The sensitivity of this resist was shown to be between 5 and 10 ?C/cm^2 at 20 keV for various combinations of post application bake and post exposure bake conditions. Using 30 keV electron beam exposure, sparse patterns with 12 nm resolution were demonstrated, at a line dose of 300 pC/cm, whilst dense patterns with half-pitch 20 nm were achieved at 200 pC/cm, as shown in figure 1. The LWR for the densely patterned resist (measured at hp 25 nm) is approximately 4 nm. The etch durability of the fullerene resist was comparable to SAL601, a common novolac resist. [1] International Technology Road map for Semiconductors, 2006 Update, http://www.itrs.net . [2] R.L. Brainard, G.G. Barclay, E.H. Anderson, L.E. Ocola, Microelectron. Eng., *2002*, /61-62/, 707. Figure 1: 20 nm half-pitch lines and spaces exposed with a dose of 200 pC/cm at 30 keV, developed in MCB (1:1) IPA for 10 s, with a 10 s IPA rinse. * * * * * * * * * * * * * * -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: clip_image003.gif Type: image/gif Size: 38525 bytes Desc: not available URL: