Reminder: University Ph.D. Oral Examination- Joseph Po-Ta Chen-Feb. 4th, Monday 9:45 AM
Joseph Po-Ta Chen
jptchen at stanford.edu
Fri Feb 1 11:31:19 PST 2008
"Characterizations of Defects and Bonding Structures in High-K/Si & High-K/GaAs Interfaces"
Joseph Po-Ta Chen
Department of Materials Science and Engineering
Advisor: Yoshio Nishi
February 4th, 2008
9:45AM (Refreshments served at 9:30AM)
High dielectric constant (K) materials are needed to replace SiO2 and SiON as the gate dielectric for CMOS devices. The leading candidates are hafnium based dielectrics including HfSiON, HfxSi1-xO2, and HfO2. Although recent studies indicate promising device integration of high-K into Si process, the dielectric/Si interface defects and oxide charge trapping centers still remain as critical challenges to process optimizations for MOS gate stacks. Typically, threshold voltage instability and device mobility degrades from scattering with electrical active defects at or near the high-K/Si interface when the interfacial oxide thickness reduced to less than 1 nm.
In our study, electron spin resonance (ESR) is utilized to characterize interface defects and trapping centers in Hf0.4Si0.6O2, Hf0.6Si0.4O2, and HfO2deposited on (100)Si. The Pb0 interface defect in Hf0.4Si0.6O2 annealed at 800 oC N2 is found to have ~12% higher g-value anisotropy and higher interfacial strain than those in SiO2/(100)Si. In addition to Pb0 and Pb1 at the underlying SiOx/Si interface, a third defect, believed to be the EX, is observed in undamaged films of 40 nm thick HfxSi1-xO2. For 4 nm HfxSi1-xO2 films annealed in N2 at both 800 and 1000 oC, the Hf0.6Si0.4O2 has a lower total Pb-type interface state density than that of Hf0.4Si0.6O2, and shows less mobility degradation in MOSFET device. Electrically biased paramagnetic defects at 800 oC N2 annealed HfxSi1-xO2/(100)Si and HfO2/(100)Si interfaces in metal oxide silicon (MOS) structures are also reported. These defects are examined by electrical-field controlled ESR and correlated to capacitance-voltage (C-V) analysis. Distributions of ESR active density of interface traps (ESR-Dit), Pb0 and Pb1, exhibit distinct charge humps and peaks in the Si bandgap with maximum peak density of 0.9~1.9×1012 cm-2eV-1 in Hf0.4Si0.6O2/Si interface. Three Pb0 and one Pb1 charged ESR- Dit peaks with density of 1.7~2.8×1012 cm-2eV-1 are observed in Hf0.6Si0.4O2/Si interface. Cross-section transmission electron microscopic (TEM) images show decreasing interfacial layer (IL) thickness with increasing hafnium composition at HfxSi1-xO2/Si interface. The roughest IL observed at the HfO2/Si interface may have contributed to an ESR-Dit of Pb0 greater than 2×1013 cm-2eV-1 and a pinned Fermi-level near mid-gap. It appears that the energy distributions of interface defects in HfxSi1-xO2/Si and HfO2/Si have different signatures compared to those at SiO2/Si interface especially the charged peak near mid-gap.
Besides, the ever increasing need for higher speed and lower power computing has already pushed the Si-based transistors close to their performance limit. Alternative materials with high carrier mobility like III-V compound semiconductors are being actively evaluated. GaAs, in particular, embraces the advantages of higher electron mobility and larger bandgap as compared to Si. However, unlike Si, it is difficult to achieve a stable passivation native insulator by the thermal oxidation, and the native oxides were observed to induce high density of interface traps and cause Fermi level pinning. Recent research demonstrates successful MOS devices based on atomic layer deposited (ALD) high-K Al2O3 and HfO2 on GaAs. It suggests that a stable and passivated interface between dielectrics and GaAs is the key component for successful GaAs MOS devices because the GaAs surface is easily degraded during the dielectric deposition.
In our study, the interface between ALD grown HfO2 and (100) GaAs which treated with HCl cleaning and (NH4)2S passivation is characterized. ESR detects decreasing paramagnetic defect signals in the sulfide-treated GaAs surface. Meantime, synchrotron radiation photoemission core level spectra indicate successful removal of the native oxides and formation of passivating sulfides on the GaAs surface. Layer-by-layer removal of the HfO2 film reveals a small amount of As2O3 formed at the interface during the ALD process. Traces of arsenic and sulfur out-diffusion into the HfO2 film are observed after a 450oC post-deposition anneal, and may be the origins for the electrically active defects. It appears that HCl+(NH4)2S treatments provide a superior chemical passivation for GaAs and initial surface for atomic layer deposition.
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