Seminar: Lessons from Gate Stack Research for Nano Scale Devices and Future Challenges in Silicon based Device Technology

Roozbeh Parsa rparsa at stanford.edu
Mon Feb 4 08:04:41 PST 2008


Title: Lessons from Gate Stack Research for Nano Scale Devices and  
Future Challenges in Silicon based Device Technology


Date: Wednesday, February 6, 2008
Time: 4:00 ? 5:00 pm (refreshments at 3:45)
Place: CISX Auditorium
Host: Prof. Roger Howe


Speaker:
Dr. Byoung Hun Lee
SEMATECH, Austin, Texas


Abstract

After the four decades since its implementation in the core of silicon  
device technology, the polysilicon/SiO2 gate stack has been finally  
replaced with metal electrode/ high-k dielectric gate stacks for  
leading edge Si CMOS devices.  More than a decade of intense research  
on the new gate stack materials such as Hf-based gate dielectric and  
various metal electrodes yielded plenty of new understandings on the  
device physics and characterization technologies as well as new  
material systems and provided a new pathway to future nano scale  
device development.
This talk will review the key technical challenges that have been  
overcome to implement new gate stack materials, including the  
discussion on the mobility degradation mechanism of high-k dielectric,  
a unified dipole model used to control the effective workfunction of  
metal electrode, and new understandings on the reliability physics for  
high-k dielectrics. Then, the technical challenges associated with  
alternative materials and novel devices will be discussed for future  
device and material research.



Biography:

Byoung Hun Lee received a B.S. (1989) and a M.S. (1992) in Physics  
from Korea Advanced Institute of Science and Technology and Ph.D  
(2000) in electrical and computer engineering from the University of  
Texas at Austin.  He worked at Samsung semiconductor (1992-1997) and  
IBM (2001-2007). He has authored and co-authored more than 300 journal  
and conference papers in the various semiconductor research areas  
including memory technology, MOSFET reliability, SOI device and  
process, strained silicon devices, and high-k and metal gate process  
and devices.  He is currently managing emerging technology program at  
SEMATECH.  He is a senior member of IEEE and acting as a guest editor  
for Microelectronics Engineering and IEEE Transaction on Devices and  
Materials Reliability.  He is a general chair of IEEE International  
Symposium on Advanced Gate Stack Technology in 2008 and served a  
member of technical committee in various technical conferences  
including International Reliability Physics Symposium, Semiconductor  
Interface Specialist Conference and VLSI-TSA.



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