Special seminar by Prof. Luca Larcher on leakage in gate dielectrics

[Krishna Saraswat]

SEMINAR
By
Prof. Luca Larcher
University of Modena and Reggio Emilia, Italy
on
STATISTICAL MODELING OF LEAKAGE CURRENTS THROUGH SIO2/HIGH-K  
DIELECTRIC STACKS
In Packard 204, on Friday, February 8, 2008, at 3 pm

ABSTRACT
In this talk, a statistical Monte Carlo (MC) simulator modeling  
leakage currents across SiO2/high-k dielectric stacks is presented.  
It will be shown that simulations accurately reproduce experimental  
currents measured also at various temperatures on capacitors with  
various high-k (HfO2, HfSiON, Al2O3) dielectric stacks.
Statistical simulations are exploited to investigate the impact of  
high-k’s traps on leakage current distribution for Flash memory  
applications, demonstrating that defects strongly reduces the  
potential improvement due to the introduction of band-gap engineered  
high-k tunnel dielectric stacks.
In this regard, the simulator is a useful tool to optimize high-k  
tunnel stacks and to improve technology-reliability issues related to  
Flash memory applications.


Prof. Luca Larcher graduated in Electronic Engineering from the  
University of Padova, Italy, in 1998. He received his Ph.D. degree in  
2001 from the University of Modena and Reggio Emilia, working on the  
compact modeling of non-volatile memories (E2PROM and Flash). He is  
currently Assistant Professor of Electronics at the University of  
Modena and Reggio Emilia, Italy. His research interests concern  
mainly the electrical characterization, the compact modeling and the  
failure mechanism analysis of standard and innovative Flash memories.  
He is working on the characterization and design of Radio Frequency  
integrated circuits in CMOS technology. He authored and coauthored a  
book (“Floating Gate Devices: Operation and Compact Modeling,” P.  
Pavan, L. Larcher, and A. Marmiroli, Kluwer Academic Press, Boston,  
ISBN 1-4020-7731-9, January 2004), and more than 55 technical papers.



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