Reminder: PhD Oral Defense and Abstract - Paul Leu, Friday 2/8 3 PM

Paul Leu pleu at stanford.edu
Wed Feb 6 21:43:43 PST 2008


Semiconductor Nanowires: Modeling, Experiments, and Their Implications

 

Paul W. Leu

Department of Mechanical Engineering

 

Advisors: Prof. Paul C. McIntyre and Prof. Kyeongjae (KJ) Cho

 

Friday, February 8th, 2008

3:00 PM (Refreshments served at 2:45 PM)

CIS-X 101

 

Semiconductor nanowires (NWs) have the potential for a variety of
nanoelectromechanical and nanodevice applications. This presentation
discusses the electromechanical properties and electrical transport of
semiconductor NWs. 

 

The first part of the talk covers the systematic study of the mechanical and
electrical properties of small diameter (< 3 nm) silicon NWs under axial
strain using ab initio density functional theory calculations. The values of
Young's Modulus, Poisson ratio, band gap, effective mass, work function (WF)
and deformation potentials were calculated for <110> and <111> oriented Si
NWs. We performed a detailed study of the effects of axial strain on the
band structure and electronic properties and attempt to predict the effect
of strain on electronic transport properties. We found a dramatic decrease
of the deformation potentials of Si NWs under strain, which may lead to a
many fold increase of electron or hole mobilities. The decrease of
deformation potentials occurs as NWs undergo a direct-to-indirect band gap
transition and is concurrent to the increase of effective mass. We also
found that quantum confinement in Si NWs acts as a built-in tensile strain,
which splits conduction band valleys and decreases transport effective mass.

 

The second part of the talk covers the fabrication of vertically aligned
germanium NW structures and their transport and doping characterization.
Dense vertical Ge NWs were grown epitaxially on Ge <111> substrates from Au
catalysts. The NWs could be doped by the deposition of a conformal shell of
boron-doped Ge around the vertical NWs. The NWs were encapsulated in highly
conformal silica using an alternating layer deposition process to isolate
and support them. Chemical mechanical polishing was used to planarize the
samples and expose the Ge NW tips. The post-CMP cleaning was found to be
important in removing slurry particles and contamination from the samples
while leaving the Ge NWs intact. We probed the topography and electrical
transport properties of these encapsulated vertical Ge NW structures using a
probe station and conductive AFM. The NWs were shown to exhibit
resistor-like IV characteristics when grown on p-type substrates and p-n
junction rectifying behavior when grown on n-type substrates. All processes
took place at temperatures below 400o C, a key requirement for monolithic
3-dimensional integration of semiconductor devices on Si integrated
circuits.

 

 

 

 

 

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