From mtang at stanford.edu Thu Jan 3 17:28:11 2008 From: mtang at stanford.edu (Mary Tang) Date: Thu, 03 Jan 2008 17:28:11 -0800 Subject: SNF Lab Update: 1/3/07 Message-ID: <477D8BAB.5000008@stanford.edu> Hello everyone! And welcome back! Just a reminder that the lab opens for business tomorrow, Friday, Jan. 4, at 7 am. If you plan to get an early start for the year, please be aware of the following: *Make sure to review Coral messages before using equipment*. Startup/process quals for some tools may be delayed: make sure to check the tool status before running your wafers. Consult Staff if you have any questions. *svgcoat/svgcoat2* - These tracks were upgraded with a new PC interface. New procedures are being posted. Please consult with Gary, Mahnaz, and Uli, who will be on-hand from 7 am Friday to retrain anyone needing it. Recipes are being requalified one at a time -- check recipe status on Coral. Please be aware that many software and hardware changes are still underway -- if you have any problems, log them on Coral so that they can be addressed as soon as possible (while the vendors are still here!) *Lab Cleanup 2007:* As part of the lab cleanup, all personal items left outside lab bins during shutdown were collected, removed from the lab, and placed in storage. If you are missing wafers or other personal items, please contact a Staff member. .... and while most of us were off enjoying the holidays, the Facilities and SNF Maintenance staff were hard at work, performing annual preventive maintenance (Mike D, Jim H, Cesar & Mario) and other repairs. Some notable activities this shutdown included: a complete functional checkout of the Toxic Gas Alarm system (special thanks to Leonard, Ray and Ted); upgrade of the liquid nitrogen vaporizer and purifier (kudos to Ted and Air Products for the smoothest installation ever); upgrade of the ASML (thanks Gary S, and the ASML team [Binder, Alex, Michael, Linda]); new wbgeneral shelving (Dave, Ed, Uli); new EVG aligner (Gary S, Mahnaz); major SVGcoat recipe manager upgrade (Gary S, Mahnaz); rebuild of the STS dep tool (Jim); new network switches and OS upgrades for SNF servers (John.) Happy processing! Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mahnaz at stanford.edu Fri Jan 4 09:37:57 2008 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 04 Jan 2008 09:37:57 -0800 Subject: SVG cot training Message-ID: <477E6EF5.6070103@stanford.edu> Hello all Due to major changes on the svgcoat, there will be two sessions of training on the system today Friday 4th. first session at 11 am and second session at 2 pm in the lab. Lab members whom planning to use the system over the weekend are encouraged to attend either session. There will be more sessions ( given by Gary, Uli and Mario) next week so no need for the rush and also we do have documentation for the change next to the system. Please help us to make a smooth transition. mahnaz From shott at stanford.edu Mon Jan 7 07:53:24 2008 From: shott at stanford.edu (John Shott) Date: Mon, 07 Jan 2008 07:53:24 -0800 Subject: Computer updates .... Message-ID: <47824AF4.70801@stanford.edu> An HTML attachment was scrubbed... URL: From mahnaz at stanford.edu Mon Jan 7 10:30:56 2008 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Mon, 07 Jan 2008 10:30:56 -0800 Subject: SVG Message-ID: <47826FE0.10601@stanford.edu> Hello I will be in the lab till 12 noon so if you need to learn about the changes on the coater come and LEARN. mahnaz From gsosa at stanford.edu Tue Jan 8 18:48:37 2008 From: gsosa at stanford.edu (Gary J Sosa) Date: Tue, 08 Jan 2008 18:48:37 -0800 Subject: SVG Coat 1 manual dispense program Message-ID: <20080108184837.7jn0znglk40cokgw@webmail.stanford.edu> Hi Serena and Labmembers.... There are a new group of recipes added to SVG coater #1 recipe table, specifically for manual dispensing. There are 4 with vapor prime and 4 without vapor prime and cover bake times of 60, 100, 120 and 200 seconds. The program naming is as follows: With Vapor Prime- 3 M/D w/VP 60s Bake 3 M/D w/VP 100s Bake 3 M/D w/VP 120s Bake 3 M/D w/VP 200s Bake Without Vapor Prime- 3 M/D wo/VP 60s Bake 3 M/D wo/VP 100s Bake 3 M/D wo/VP 120s Bake 3 M/D wo/VP 200s Bake ..... Gary From pruitt at stanford.edu Wed Jan 9 12:10:03 2008 From: pruitt at stanford.edu (Beth Pruitt) Date: Wed, 9 Jan 2008 12:10:03 -0800 Subject: MEMS Seminar on Thursday, Jan. 10, 2008 at 4:15 PM Message-ID: > > >Mechanics & Computation ME395 Seminar In Solid Mechanics > >Winter 2007 >Thursday, 1/10/2008 at 4:15 PM in EDUC128 >Electrostatic Micromotors and Micromachining Methods for Their Fabrication >Edin Sarajlic >CIRMM, Institute of Industrial Science (IIS), The University of Tokyo, Japan > >This seminar focuses on the development of micromotors and >micromachining methods for their fabrication. >Electrostatic stepper motors with built-in mechanical leverage >(shuffle and contraction beams motors), MicroElectroMechanical >Digital-to-Analog Converters (MEMDAC) of displacement and 3-phase >electrostatic stepper motors will be presented. High performance >characteristics of these motors in terms of output force, >displacement range, positioning resolution, speed and durability >make them promising candidates for numerous possible applications >including data storage, microassembly, microscopy, robotics and >optical systems. >In general, electrostatic micromotors require proper electrical >insulation between mechanically interconnected structures. Two >micromachining methods, vertical trench isolation and High Aspect >Ratio Etching and Metallization (HAREM), will be introduced. These >methods allows distinct electrical domains to be formed on both >fixed and movable micromechanical parts opening a wide range of >opportunities for simplified fabrication and performance improvement >of micromotors, and MEMS in general. > > > > >1D Shuffle Motor >2D Shuffle Motor >Vertical Trench Isolation > > >BIOGRAPHY >Edin Sarajlic received in 2001 the M.Sc. degree (Cum Laude) in >mechanical engineering from The University of Twente, The >Netherlands. In 2005 he completed the Ph.D. course in electrical >engineering in Transducers Science and Technology Group conducted by >Prof. Dr. Miko Elwenspoek at MESA+ Research Institute, The >University of Twente. He is currently a Researcher in the MEMS Lab >of Prof. Hiroyuki Fujita at Institute of Industrial Science, The >University of Tokyo, Japan. His research interest focuses on the >development of microactuators and micromachining methods for their >fabrication. > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001 71.jpg Type: image/jpeg Size: 4810 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002 18.jpg Type: image/jpeg Size: 5217 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image003 8.gif Type: image/gif Size: 33697 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image004 3.jpg Type: image/jpeg Size: 4222 bytes Desc: not available URL: From maryamzm at stanford.edu Thu Jan 10 12:33:31 2008 From: maryamzm at stanford.edu (Maryam Ziaei-Moayyed) Date: Thu, 10 Jan 2008 12:33:31 -0800 Subject: Special MEMS Seminar: Firday 1/11/08 at 2PM, CISX Auditorium In-Reply-To: <20070613124758.7lrp44mg774sgs44@webmail.stanford.edu> References: <20070613124758.7lrp44mg774sgs44@webmail.stanford.edu> Message-ID: <20080110123331.xlqnnq25wcsgoc8w@webmail.stanford.edu> MEMS Seminar Announcement: WHEN: Friday 1/11/08 2-3pm Refreshments at 1:45pm WHERE: CISX Auditorium TITLE: Electro Micro Metrology (EMM) SPEAKER: Prof. Jason Clark Dept. of ECE, Purdue University From maryamzm at stanford.edu Thu Jan 10 12:38:42 2008 From: maryamzm at stanford.edu (Maryam Ziaei-Moayyed) Date: Thu, 10 Jan 2008 12:38:42 -0800 Subject: Correction: Special MEMS Seminar: Firday 1/11/08 at 2PM, CISX Auditorium In-Reply-To: <20080110123331.xlqnnq25wcsgoc8w@webmail.stanford.edu> References: <20070613124758.7lrp44mg774sgs44@webmail.stanford.edu> <20080110123331.xlqnnq25wcsgoc8w@webmail.stanford.edu> Message-ID: <20080110123842.4hd1l7uvbgg4w0k8@webmail.stanford.edu> My appologies, the wrong email went out last time-- See below for the correct information. -Maryam --------------------------------------------------------- Special MEMS Seminar Announcement WHEN: Friday 1/11/08 2-3pm Refreshments at 1:45pm WHERE: CISX Auditorium TITLE: Building Blocks for Silicon MEMS Timers and Signal Processors SPEAKER: Dr. Ashwin Seshia Lecturer in MEMS and Fellow, Queens? College Dept. of Engineering, University of Cambridge Abstract: This talk will introduce new building blocks and concepts for silicon-on-insulator based MEMS resonator technology with a focus on developments at the device and circuit levels. A comparison is drawn between different transducer technologies and resonator topologies with a view towards frequency scaling and power handling. Linear and nonlinear circuit topologies are introduced for silicon micromechanical resonator based oscillators with a view towards compensating extremes of capacitive and motional parasitics inherent in the hybrid integration of MEMS with CMOS while simultaneously optimising for low phase noise and power dissipation. Scalable filter topologies based on mechanically and electrically coupled resonant modes in silicon microstructures are presented. Reverse-biased pn junctions embedded in silicon microresonators are introduced as an alternative, CMOS compatible transducer with beneficial scaling for NEMS applications. Short Bio: Ashwin A. Seshia received the B.Tech. in engineering physics from IIT ? Bombay in 1996 and the M.S. and Ph.D. degrees from UC Berkeley in electrical engineering in 1999 and 2002. His Ph.D. thesis demonstrated the theory and operation of an integrated MEMS resonant-frequency-shift output vibratory rate gyroscope. He is presently a member of the faculty of the Cambridge University Engineering Department where he is Lecturer in micro electromechanical systems (MEMS), a Fellow of Queens? College and a member of the Micromechanics and Nanoscience research groups. His research interests include integrated micromechanical resonant structures for sensor and timing applications, micromachined devices for in-vivo monitoring, and biological sensor systems. -------------- next part -------------- A non-text attachment was scrubbed... Name: AASeshia.Seminar.Jan2008.doc Type: application/msword Size: 161280 bytes Desc: not available URL: From nevran at gmail.com Fri Jan 11 12:03:34 2008 From: nevran at gmail.com (Nevran Ozguven) Date: Fri, 11 Jan 2008 12:03:34 -0800 Subject: Silicidation Message-ID: <509d3c110801111203w4b6d1327jdef062929fd7da8b@mail.gmail.com> Dear labmembers, Does anyone know of a company that does silicidation? My preference would be a company in the Bay Area but outside the area would also work. Thanks, Nevran -------------- next part -------------- An HTML attachment was scrubbed... URL: From gsosa at stanford.edu Fri Jan 11 19:58:59 2008 From: gsosa at stanford.edu (Gary J Sosa) Date: Fri, 11 Jan 2008 19:58:59 -0800 Subject: SVG Coater Status Message-ID: <20080111195859.e5j36iphz4wogco0@webmail.stanford.edu> Hi labmembers.... The SVG coaters are back up again!!! There are now 2 computers for the SVG coaters. The right computer controls front track(Track #1) and the left computer controls the back track(Track #2). All of the functions are still the same and the login is the same for both computers(User ID is: litho and password is: svg) The 3612 coatings look good on both tracks now. Verified good thickness for 1.0 and 1.6 microns on both track. Please continue to report any problems or unusual behavior with the new system computers or the track systems. Thanks... Gary From mtang at stanford.edu Mon Jan 14 08:37:00 2008 From: mtang at stanford.edu (Mary Tang) Date: Mon, 14 Jan 2008 08:37:00 -0800 Subject: EE410 begins! Here's the chedule for this week.... Message-ID: <478B8FAC.4050108@stanford.edu> Greetings Labmembers: It's that time of year again,when EE410 descends on the lab.... For those of you who don't know, EE410 is a very challenging class in which the students fabricate, model, and test a CMOS device (for more info, check out the class website at http://www.stanford.edu/class/ee410). The schedule for processing this device is aggressive -- and we ask for your patience over the next 6 weeks as priorities and equipment access may be shifted in order to allow full support for this class. The schedule for the lab sections (which will also be posted on the calendar outside the gowning room) is as follows: Tuesday 1-5: Dawson Wong (Coral name: djwong) Wednesday 8-12: Caner Onal (Coral name: caner) Wednesday 1-5: Dawson Wong(Coral name: djwong) Thursday 1-5: Duygu Kuzum (Coral name: duygu) Unlike before, this year, the EE410 device will be done on the asml. We have reserved the asml and svgcoat/svgdev tracks for the entire four hours of each lab section. We anticipate the tools will be available for general lab use during these times, but please respect that EE410 has priority use during lab sessions. We apologize for any an impact these activities may have on access to key lab equipment -- and will make every effort to give advance warning about our scheduling of high use tools. If you have any questions, comments, or suggestions, please get in touch with the lab TA's or your favorite staff members. Just as a heads up -- For next week, the lab sections will be performing diffusion operations, so will be processing through gasonics, wbnonmetal, wbdiff, and tylans. Thanks for your attention -- Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From shott at stanford.edu Tue Jan 15 17:44:50 2008 From: shott at stanford.edu (John Shott) Date: Tue, 15 Jan 2008 17:44:50 -0800 Subject: Coral failure to update .... Message-ID: <478D6192.3070306@stanford.edu> An HTML attachment was scrubbed... URL: From shott at stanford.edu Wed Jan 16 14:06:33 2008 From: shott at stanford.edu (John Shott) Date: Wed, 16 Jan 2008 14:06:33 -0800 Subject: Shared Probe Station .... Message-ID: <478E7FE9.7080302@stanford.edu> An HTML attachment was scrubbed... URL: From edmyers at stanford.edu Thu Jan 17 09:08:47 2008 From: edmyers at stanford.edu (Ed Myers) Date: Thu, 17 Jan 2008 09:08:47 -0800 Subject: Fwd: J.A. Woollam Co. Short Course Announcement Message-ID: <6.2.5.6.2.20080117085834.03f4ad20@stanford.edu> > >Date: Thu, 17 Jan 2008 10:45:46 -0600 >To: Veronica Inlow >From: Veronica Inlow >Subject: J.A. Woollam Co. Short Course Announcement > > >Dear J.A. Woollam Customers, > >We would like to invite you to our next Standard Short Course to be >held March 24-27, 2008 at the Georgia Institute of Technology in >Atlanta, Georgia, USA. I have attached a course description and >registration form. If you are interested, please fill out the >registration form completely and fax back to me at +1(402)-477-8214 >by March 7, 2008. Once I receive your registration form, I will send >a confirmation email. > >This course will focus on data analysis methods for spectroscopic >ellipsometry with a significant amount of "hands-on" computer time. >For this reason, participants should be familiar with WVASE32 >software. If you have any questions, please feel free to contact me. > >Sincerely, > >Veronica Inlow > > > >Veronica Inlow >Marketing Coordinator >J. A. Woollam Co., Inc. >645 M Street, Suite 102 >Lincoln, NE 68508 >vinlow at jawoollam.com >Phone: (402)477-7501 x101 >Fax: (402)477-8513 -------------- next part -------------- A non-text attachment was scrubbed... Name: ShortCourseRegistration_GATech.pdf Type: application/pdf Size: 29416 bytes Desc: not available URL: From atomada at stanford.edu Thu Jan 17 15:59:19 2008 From: atomada at stanford.edu (Astrid Tomada) Date: Thu, 17 Jan 2008 15:59:19 -0800 Subject: Seminar on Jan. 24: Surface Metrology Using Peelable Polymer Coatings Message-ID: Interested? Come to Varian Building (second floor) Rm #208 on Thursday January 24, 2008 at 4:00 p.m. Professor Hamilton of University of Wisconsin-Platteville will present a seminar on peelable polymer coatings - abstract attached. Diamonds in Washington, Volcanic Dust in Hawaii and Dark Matter: Surface Metrology Using First Contact Polymers Professor James P. Hamilton1,2 1Department of Chemistry and Engineering Physics, University of Wisconsin-Platteville, 1 University Plaza, Platteville, WI 53818 2Photonic Cleaning Technologies, PO Box 435, Platteville, WI 53818 Nanotube doped, ESD free, peelable polymer coatings for surface protection, nanoreplication, cleaning and dust mitigation have been developed and successfully used on diverse surfaces. Some of the exciting metrology we have performed will be discussed using these designer polymers on high power laser optics; the Hope Diamond in Washington; the W.M. Keck telescope on Mauna Kea in Hawaii; mirrors for Hubble; CCD?s for the 520 megapixel Dark Energy Survey Camera being built at Fermilab and CDMS ZIP detector surfaces. Research in our labs has resulted in novel polymeric stripcoatings that are applied as a liquid and subsequently peeled off the substrate as a solid film. These polymer blend solutions safely clean and protect a wide variety of nanostructured surfaces and leave the surface almost atomically clean and ?space ready?(NASA). Contaminant removal was monitored by a variety of techniques including Nomarski, Atomic Force and Scanning Electron Microscopy as well as XPS. In addition, our data demonstrates that the material safely removes particulate contamination and finger oils from microstructures such as the 300nm wide lines on diffraction gratings and similar submicron features on Si wafers. These nanosurfaces are also replicated with high fidelity down to well below 50nm. Recent results also demonstrate YAG laser damage thresholds after cleaning on coated BK7 of 15J/cm2 at 20ns and 20Hz (i.e. good as new). -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: text/enriched Size: 3055 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Stanford CDMS abstract.doc Type: application/msword Size: 27136 bytes Desc: not available URL: -------------- next part -------------- _____-----_____-----_____ Astrid Tomada Department of Physics Stanford University atomada at stanford.edu _____-----_____-----_____ -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: text/enriched Size: 139 bytes Desc: not available URL: From shott at stanford.edu Fri Jan 18 12:04:20 2008 From: shott at stanford.edu (John Shott) Date: Fri, 18 Jan 2008 12:04:20 -0800 Subject: Missing a black, fleece-lined jacket? Message-ID: <47910644.3060809@stanford.edu> SNF Lab Members and CIS Building Occupants: A black, fleece-lined jacket was found in the break room on the first floor of the CIS building and has been put away for safe keeping. If this is your jacket, please contact me at x5-3715 or send email to shott at stanford.edu and I will see that your jacket is returned. Thanks, John From gloria.wong at stanford.edu Fri Jan 18 14:37:14 2008 From: gloria.wong at stanford.edu (Gloria Wong) Date: Fri, 18 Jan 2008 14:37:14 -0800 Subject: University Ph.D. Oral Examination - Gloria Wong Message-ID: <012b01c85a22$ac711860$0100000a@Laptopsally> "An Investigation of the Work Function of Metal Gate Electrodes for Advanced CMOS Applications" Gloria Wong Department of Materials Science and Engineering Advisors: Bruce Clemens and Yoshio Nishi February 1st, 2008 9:30AM (Refreshments served at 9:15AM) CIS-X Auditorium Abstract: Scaling the gate length and oxide thickness of the metal oxide semiconductor field effect transistor (MOSFET) offers great potential to improve device performance and circuit density. While the polycrystalline silicon gate electrode offers process compatibility and a tunable interface work function, its susceptibility to charge carrier depletion and boron penetration into the channel region is driving the need to investigate alternative gate materials. The use of metals for the gate electrode eliminates these problems, and shows better compatibility with high-k gate dielectrics. In order to optimize transistor performance, metals with appropriate work functions for both NMOS and PMOS must be identified and integrated into the conventional CMOS process flow. In this work, both single metal and two-component metal gate systems were investigated to develop a fundamental understanding of the factors that influence the metal gate electrode work function. In the single metal case, tungsten was chosen for study as it is a well-known refractory material in IC processing. The work function was found to be ~0.3eV higher in evaporated electrodes than in sputter-deposited films, which may be related to differences in roughness, density, grain size and as-grown oxygen content observed by physical characterization. In the two-component systems, metal gates were fabricated using a stacked bilayer structure. In previous work, it was found that the work function can be controlled by the thickness of the underlayer metal (the layer closest to the oxide). Depending on the amount of diffusion, the influence of the overlayer on the atomic concentration at the dielectric interface varies. Three two-component systems were investigated: Nb-W, Ti-W and Pt-Ti. By selecting materials systems that exhibit differences in diffusion and phase formation (as predicted by their phase diagrams), the change in work function due to underlayer thickness and composition for all three metal pairs is elucidated. The diffusion behavior in bilayer metal gates was investigated using x-ray reflectivity of multilayer films and was also modeled to quantify the differences between these three metal-metal systems. The effect of composition on the work function was directly probed by fabricating alloy metal gate electrodes by co-sputtering. A non-linear behavior was observed where the work function is dominated by the lower work function constituent. Structural information on the alloy films was obtained using x-ray diffraction. Thermal stability of all three systems was demonstrated during extended anneals and the observed time-dependent diffusion behavior is proposed to be related to diffusion through the grain boundaries. -------------- next part -------------- An HTML attachment was scrubbed... URL: From grace.m.credo at intel.com Mon Jan 21 11:10:36 2008 From: grace.m.credo at intel.com (Credo, Grace M) Date: Mon, 21 Jan 2008 11:10:36 -0800 Subject: Looking for missing item Message-ID: <2D848F959C03D945A84E9EDE7F7BFE4263A530@orsmsx424.amr.corp.intel.com> Hi Labmembers, I need some help locating a missing mask. It should be in one of my small personal storage containers (translucent bottom with light green lid). The mask has small arrays with features sizes from 1000um to 2um. It has text on the bottom part of the mask that indicates it was made for my company - Intel. I think this particular mask is "Intel 00004" or "Intel 00002". I added another mask to my container today, but it is different ("Intel 00003") so I should have two. My SNF name/label is "gcredo" If you have seen something like this let me know when and where. If you know where it is, please let me know and then put it back in my storage container, no questions asked. My storage containers are on the bottom shelf (on top of someone else's boxes) towards the middle of the storage room. Thanks, Grace ________________________________________ Grace Credo Intel Research grace.m.credo at intel.com or gcredo at snf.stanford.edu 1-408-653-8495 -------------- next part -------------- An HTML attachment was scrubbed... URL: From edmyers at stanford.edu Mon Jan 21 12:26:13 2008 From: edmyers at stanford.edu (Ed Myers) Date: Mon, 21 Jan 2008 12:26:13 -0800 Subject: Toxic Gas Alarm, 1/21/08 Message-ID: <6.2.5.6.2.20080121121957.01e387f8@stanford.edu> Lab Members, At approximately 10:10am on Monday, Jan. 21st, we had a toxic gas alarm in the gas bunker. As a result, all of the gases stored in this room were shut off. This included gases such as silane, germane, arsine, phosphine,... The gases were off until approximately 11:45 am, at which time all were returned to service, EXCEPT for phosphine running to Tylan bank 3. If you were processing during this time, you may have seen a gas flow alarm. You need to verify what impact this gas shutdown may have had on your samples. As of 11:45am, all gases EXCEPT phosphine servicing Tylan bank 3 have been returned. Regards, John and Ed From dalyx at stanford.edu Mon Jan 21 16:41:41 2008 From: dalyx at stanford.edu (Dany-Sebastien Ly-Gagnon) Date: Mon, 21 Jan 2008 16:41:41 -0800 Subject: OSA/SPIE Seminar: Prof. Richard De La Rue, Wednesday Jan. 23 2008, 3:15pm In-Reply-To: <7f014b6b0801201552u64574c4er5474931ed6f3f653@mail.gmail.com> References: <7f014b6b0801201552u64574c4er5474931ed6f3f653@mail.gmail.com> Message-ID: <7f014b6b0801211641q2360f832x44a313fb2b1133af@mail.gmail.com> OSA / SPIE Stanford Student Chapter presents *Richard De La Rue* Professor of Optoelectronics Glasgow University Title: *Photonic crystal, Photonic Wire and Metamaterial Nanophotonics * *Wednesday, January 23, 2008 3:15pm, Ginzton building, AP 299 *Refreshments at 3:00pm* * *Abstract* This presentation will describe recent work that pushes the performance envelope of device structures based on photonic crystal and photonic wire principles - both in terms of optical confinement and in terms of propagation and transmission loss reduction. Fabrication technology aspects are crucial for success in this domain. Much of the work has used the silicon-on-insulator platform that is currently 'de rigeur' in integrated photonics, but other material combinations will make an appearance. Silicon will also re-appear as an interesting base, i.e. substrate, for tunable metamaterial structures that test the fabrication capabilities of even the best electron-beam lithographic machines. *About our Speaker * Richard De La Rue has been Professor of Optoelectronics at Glasgow University in Scotland since 1986. His research is now particularly concerned with photonic crystal and photonic wire structures and with waveguide micro-cavities. His research in the area of photonic crystals has now evolved to cover compact lasers, planar micro-cavities, photonic-crystal light extractors for LEDs, photonic integrated circuits (PICs), synthetic opal and inverse opal structures. Other research interests include integrated optics technology more generally, photonic integrated circuits (PICs), DFB and DBR semiconductor lasers, quantum well intermixing, phase masks for silica waveguide photorefractive grating devices and Terahertz electrooptics. His historic interest in lithium niobate integrated optics is currently reviving in the context of photonic crystal structure fabrication. He has published more than 300 articles and papers in journals, as book chapters and as conference presentations. Current involvement in European Community funded collaborations is through the IOLOS and SPLASH projects. He has been involved in European-scale research activity through the SMILED and PICCO projects, as well as being co-leader for working group 2 (WG2) in the COST 268 Action on 'Wavelength Scale Photonics'. He is also deputy leader for the COST P11 Action 'Linear, Nonlinear and Active Photonic Crystals' and participates in the ePIXnet Network of Excellence. He is currently general co-chair for CLEO-Europe/EQEC (Munich 2009) and leading co-chair for the 'Photonic Crystal Materials and Devices' conference at Photonics Europe (Strasbourg 2008). For two years from mid-1999 he served as IEEE-LEOS Distinguished Lecturer. He is a Fellow of the IEEE (FIEEE, 2003) and Fellow of the Royal Academy of Engineering (FREng, 2002), Fellow of the Royal Society of Edinburgh (FRSE, since 1989) and Fellow of the Institution of Electrical Engineers (now Institution of Engineering and Technology, FIET, since 1997). In 2007 he was further honored by election as Fellow of the Optical Society of America (FOSA). -------------- next part -------------- An HTML attachment was scrubbed... URL: From atomada at stanford.edu Wed Jan 23 09:46:01 2008 From: atomada at stanford.edu (Astrid Tomada) Date: Wed, 23 Jan 2008 09:46:01 -0800 Subject: Reminder: Seminar Jan. 24 at 4pm: Surface Metrology Using Peelable Polymer Coatings In-Reply-To: References: Message-ID: <6721dee226411107d9ff1227ff125c89@stanford.edu> > Interested? > Come to Varian Building (second floor) Rm #208 on Thursday January 24, > 2008 at 4:00 p.m. Professor Hamilton of University of > Wisconsin-Platteville will present a seminar on peelable polymer > coatings - abstract attached. > > Diamonds in Washington, Volcanic Dust in Hawaii and Dark Matter: > Surface Metrology Using First Contact Polymers > > Professor James P. Hamilton1,2 > 1Department of Chemistry and Engineering Physics, University of > Wisconsin-Platteville, 1 University Plaza, Platteville, WI 53818 > 2Photonic Cleaning Technologies, PO Box 435, Platteville, WI 53818 > > > > Nanotube doped, ESD free, peelable polymer coatings for surface > protection, nanoreplication, cleaning and dust mitigation have been > developed and successfully used on diverse surfaces. Some of the > exciting metrology we have performed will be discussed using these > designer polymers on high power laser optics; the Hope Diamond in > Washington; the W.M. Keck telescope on Mauna Kea in Hawaii; mirrors > for Hubble; CCD?s for the 520 megapixel Dark Energy Survey Camera > being built at Fermilab and CDMS ZIP detector surfaces. > Research in our labs has resulted in novel polymeric stripcoatings > that are applied as a liquid and subsequently peeled off the substrate > as a solid film. These polymer blend solutions safely clean and > protect a wide variety of nanostructured surfaces and leave the > surface almost atomically clean and ?space ready?(NASA). Contaminant > removal was monitored by a variety of techniques including Nomarski, > Atomic Force and Scanning Electron Microscopy as well as XPS. In > addition, our data demonstrates that the material safely removes > particulate contamination and finger oils from microstructures such as > the 300nm wide lines on diffraction gratings and similar submicron > features on Si wafers. These nanosurfaces are also replicated with > high fidelity down to well below 50nm. Recent results also > demonstrate YAG laser damage thresholds after cleaning on coated BK7 > of 15J/cm2 at 20ns and 20Hz (i.e. good as new). > > > > > > > _____-----_____-----_____ > Astrid Tomada > Department of Physics > Stanford University > atomada at stanford.edu > _____-----_____-----_____ -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: text/enriched Size: 3324 bytes Desc: not available URL: From leewy at stanford.edu Wed Jan 23 14:03:13 2008 From: leewy at stanford.edu (Wonyoung Lee) Date: Wed, 23 Jan 2008 14:03:13 -0800 Subject: Si(111) wafer References: <6.2.5.6.2.20080121121957.01e387f8@stanford.edu> Message-ID: <006401c85e0b$bfcfd8a0$f63140ab@WONCOM> Hi Labmembers, Does anyone know a good vendor for Si(111) prime wafer? P-type doping I prefer. Thanks in advance. Wonyoung Lee From sbasumal at stanford.edu Wed Jan 23 15:12:23 2008 From: sbasumal at stanford.edu (Shrestha Basu Mallick) Date: Wed, 23 Jan 2008 15:12:23 -0800 Subject: Missing wafers Message-ID: <4797C9D7.4020505@stanford.edu> Hi everybody, Mohammed took 2 wafers out from the thermcopoly tube and put them in a wbdiff box for me end of last week. I was not able to go in the day after. But when I went in, I could not find the wafers. If anybody knows where the wafers are and could point me to them, that would be great! Thanks -Shrestha From jhh323 at stanford.edu Thu Jan 24 14:21:20 2008 From: jhh323 at stanford.edu (Jeong-Hee Ha) Date: Thu, 24 Jan 2008 14:21:20 -0800 Subject: University Ph.D. Oral Examination : Jeong-Hee Ha Message-ID: <20080124142120.3dwgcyp5wk0wwwko@webmail.stanford.edu> "ATOMIC SCALE EXPERIMENTAL AND THEORETICAL STUDIES OF HIGH-K GATE DIELECTRIC INTERFACES" Jeong-Hee Ha Department of Materials Science and Engineering Advisor: Prof. Paul C. McInyre Co-Advisor: Prof. Kyeongjae (KJ) Cho Thursday, February 7th, 2008 2:00 PM (Refreshments served at 1:45 PM) Packard Bldg. Rm 202 ?????? For several decades, silicon semiconductor devices have been dramatically scaled down to sub-100 nm MOSFET channel lengths in order to achieve higher device density and performance. In this regime, high-k dielectrics which can give large gate capacitances with dielectric films that are physically thicker than corresponding silicon oxide or oxynitride gate dielectrics are needed to reduce the substantial gate leakage current resulting from direct quantum mechanical tunneling across the dielectric layer. ???? Recently research and development on materials selection for alternative gate stack has converged on HfO2 based high-k oxides (HfO2, HfSiO4, or HfSiON). In 2007, Intel and IBM also announced their plan to introduce Hf-based high-k for their 45nm production. In general, those high-k oxides are deposited in a process which results in controlled formation of an ultra-thin SiO2-like passivation layer on the Si (100) surface. This SiO2-based interface layer provides the advantages of relatively low defect density afforded by the Si/SiO2 interface. However, defects at the internal dielectric interface between HfO2 and SiO2 may produce fixed charge and threshold voltage instability under bias. In this talk, careful analysis is presented to elucidate intrinsic properties of this HfO2/SiO2 interface and to gain knowledge of possible solutions for problems associated with interface defects. ???? The first part of the presentation contains the results of a phase separation study of initially-intermixed HfO2/SiO2 interfaces by in-situ low angle x-ray scattering technique. Due to the positive heat of mixing (?Hmix>0), the initially-intermixed HfO2/SiO2 interface experiences phase separation upon high temperature annealing up to 750?C, which results in a sharper interface. The extracted activation enthalpy for phase separation was 2.06 ? 0.15 eV. Considering the thermal budget of typical CMOS processes, the HfO2/SiO2 interface will encounter this phenomenon during device fabrication. The second part of the talk summarizes the results of density functional theory (DFT) simulations performed on atomistic models of the HfO2/SiO2 interface. The simulations show that the HfO2/SiO2 interface introduces occupied midgap states within the band gap. This is a result of undercoordinated Hf atoms at the interface, and the mid gap states provide a source of positive fixed charge when non-bonding electrons on the interface Hf atoms are depleted by Fermi level change. Possible remedies of Vfb/Vth shifts by chemical passivation of the HfO2-SiO2 interface are suggested based on these simulations. Finally, a study of oxygen transfer from metal gate into high-k dielectrics is presented. Because alternative metal gates are being developed along with high-k dielectrics, how the HfO2/SiO2 interface will be affected by the presence of the metal gate layer is an important issue. Experimental studies of oxygen transfer from W metal gates to the dielectric stack upon high-temperature annealing is provided using transmission electron microsopy (TEM), Fourier transform infrared spectroscopy (FTIR), synchrotron radiation photoemission spectroscopy (SR-PES), and current-voltage (CV) measurements.??? -------------- next part -------------- An HTML attachment was scrubbed... URL: From jptchen at stanford.edu Thu Jan 24 15:18:11 2008 From: jptchen at stanford.edu (Joseph Po-Ta Chen) Date: Thu, 24 Jan 2008 15:18:11 -0800 Subject: University Ph.D Oral Examination- Joseph Po-Ta Chen Message-ID: <51942C4D1C1D4906BE0A0EB3E866E3DC@JosephVaioSZ> "Paramagnetic Defects in High-K Dielectrics/Si & GaAs Interfaces" Joseph Po-Ta Chen Department of Materials Science and Engineering Advisor: Yoshio Nishi February 4th, 2008 9:45AM (Refreshments served at 9:30AM) CIS-X Auditorium Abstract: High dielectric constant (K) materials are needed to replace SiO2 and SiON as the gate dielectric for CMOS devices. The leading candidates are hafnium based dielectrics including HfSiON, HfxSi1-xO2, and HfO2. Although recent studies indicate promising device integration of high-K into Si process, the dielectric/Si interface defects and oxide charge trapping centers still remain as critical challenges to process optimizations for MOS gate stacks. Typically, threshold voltage instability and device mobility degrades from scattering with electrical active defects at or near the high-K/Si interface when the interfacial oxide thickness reduced to less than 1 nm. In our study, electron spin resonance (ESR) is utilized to characterize interface defects and trapping centers in Hf0.4Si0.6O2, Hf0.6Si0.4O2, and HfO2deposited on (100)Si. The Pb0 interface defect in Hf0.4Si0.6O2 annealed at 800 oC N2 is found to have ~12% higher g-value anisotropy and higher interfacial strain than those in SiO2/(100)Si. In addition to Pb0 and Pb1 at the underlying SiOx/Si interface, a third defect, believed to be the EX, is observed in undamaged films of 40 nm thick HfxSi1-xO2. For 4 nm HfxSi1-xO2 films annealed in N2 at both 800 and 1000 oC, the Hf0.6Si0.4O2 has a lower total Pb-type interface state density than that of Hf0.4Si0.6O2, and shows less mobility degradation in MOSFET device. Electrically biased paramagnetic defects at 800 oC N2 annealed HfxSi1-xO2/(100)Si and HfO2/(100)Si interfaces in metal oxide silicon (MOS) structures are also reported. These defects are examined by electrical-field controlled ESR and correlated to capacitance-voltage (C-V) analysis. Distributions of ESR active density of interface traps (ESR-Dit), Pb0 and Pb1, exhibit distinct charge humps and peaks in the Si bandgap with maximum peak density of 0.9~1.9?1012 cm-2eV-1 in Hf0.4Si0.6O2/Si interface. Three Pb0 and one Pb1 charged ESR- Dit peaks with density of 1.7~2.8?1012 cm-2eV-1 are observed in Hf0.6Si0.4O2/Si interface. Cross-section transmission electron microscopic (TEM) images show decreasing interfacial layer (IL) thickness with increasing hafnium composition at HfxSi1-xO2/Si interface. The roughest IL observed at the HfO2/Si interface may have contributed to an ESR-Dit of Pb0 greater than 2?1013 cm-2eV-1 and a pinned Fermi-level near mid-gap. It appears that the energy distributions of interface defects in HfxSi1-xO2/Si and HfO2/Si have different signatures compared to those at SiO2/Si interface especially the charged peak near mid-gap. Besides, the ever increasing need for higher speed and lower power computing has already pushed the Si-based transistors close to their performance limit. Alternative materials with high carrier mobility like III-V compound semiconductors are being actively evaluated. GaAs, in particular, embraces the advantages of higher electron mobility and larger bandgap as compared to Si. However, unlike Si, it is difficult to achieve a stable passivation native insulator by the thermal oxidation, and the native oxides were observed to induce high density of interface traps and cause Fermi level pinning. Recent research demonstrates successful MOS devices based on atomic layer deposited (ALD) high-K Al2O3 and HfO2 on GaAs. It suggests that a stable and passivated interface between dielectrics and GaAs is the key component for successful GaAs MOS devices because the GaAs surface is easily degraded during the dielectric deposition. In our study, the interface between ALD grown HfO2 and (100) GaAs which treated with HCl cleaning and (NH4)2S passivation is characterized. ESR detects decreasing paramagnetic defect signals in the sulfide-treated GaAs surface. Meantime, synchrotron radiation photoemission core level spectra indicate successful removal of the native oxides and formation of passivating sulfides on the GaAs surface. Layer-by-layer removal of the HfO2 film reveals a small amount of As2O3 formed at the interface during the ALD process. Traces of arsenic and sulfur out-diffusion into the HfO2 film are observed after a 450oC post-deposition anneal, and may be the origins for the electrically active defects. It appears that HCl+(NH4)2S treatments provide a superior chemical passivation for GaAs and initial surface for atomic layer deposition. -------------- next part -------------- An HTML attachment was scrubbed... URL: From bongsang at eecs.berkeley.edu Thu Jan 24 15:26:22 2008 From: bongsang at eecs.berkeley.edu (Bongsang Kim) Date: Thu, 24 Jan 2008 15:26:22 -0800 Subject: TO-can packaging vendor? Message-ID: <74f115fb0801241526l135ee5d2gd46abd06cb2d75ee@mail.gmail.com> Hi labmembers, I am looking for a local vendor that if we provide a chip, they can mount it in a metal can (like TO-can) and encapsulate it in vacuum. If you know any such local vendor, please let me know. Best, Bongsang -------------- next part -------------- An HTML attachment was scrubbed... URL: From cearhart at gmail.com Fri Jan 25 17:56:10 2008 From: cearhart at gmail.com (Chris Earhart) Date: Fri, 25 Jan 2008 17:56:10 -0800 Subject: Durimide Resist to borrow? Message-ID: <131c1bff0801251756y38bb82bfqb5ea42cdf20b5863@mail.gmail.com> Dear Labmembers, I was wondering if anyone had some durimide resist, and if I could borrow a bit. The minimum order from FujiFilm is 1 kg, and we'd like to try it out before ordering this amount. Please let me know. Thanks, Chris From gsosa at stanford.edu Fri Jan 25 18:14:08 2008 From: gsosa at stanford.edu (Gary J Sosa) Date: Fri, 25 Jan 2008 18:14:08 -0800 Subject: SVG Coater Update Message-ID: <20080125181408.e4efvlgs0sggwswo@webmail.stanford.edu> Hi Labmembers.. Just a status update on the coaters. 1. The vapor prime module on track #1 is still down due to temperature and vacuum problems 2. I addad a recipe to the back track(SVG coater #2) thad does vapor prime only. The name of the recipe is "Vapor Prime Only" 3. If for some reason you cannot download your recipes or reset the track or there is a message that says "controller 1 fails" or "controller 2 fails, the computer will need to be rebooted. Just exit the applications, if possible. Then reboot the computer as follows: - Go to windows start menu - Select "Turn off computer" - Click on the Restart Icon. The computer will reboot and start windows as normal. - After Windows boots up, double click on the Icon named "Shortcut to_Track_TC... on the Windows desktop. I moved the Icon to the upper/right corner of the screen by itself so it will be easy to find. - After that, start the applications software as per the instruction sheets. - Also, please make a comment in coral with all details so that we can fix this problem. Thanks.. Gary From rohank at stanford.edu Mon Jan 28 16:34:26 2008 From: rohank at stanford.edu (Rohan D. Kekatpure) Date: Mon, 28 Jan 2008 16:34:26 -0800 Subject: AMTEtcher for etching Silicon Message-ID: <5155A940-0C45-4A07-92E9-B9A897B96A74@stanford.edu> Dear all, P5000 and LAMPoly are our standard Si etchers. I was wondering, however, if anyone has ever used AMT for etching Si. There seems to be a recipe for doing it. If you have etched Si in AMT, I would appreciate any information on the etch rate, and, if available, any information on its comparison with P5000. My patterns are thin (30 nm thick) isolated Si lines with widths ranging between 50 nm - 200 nm. Thanks -Rohan From mtang at stanford.edu Mon Jan 28 18:27:31 2008 From: mtang at stanford.edu (Mary Tang) Date: Mon, 28 Jan 2008 18:27:31 -0800 Subject: New Lab Cleanup and Lab Storage Procedures - Effective February Message-ID: <479E8F13.1000409@stanford.edu> Greetings Labmembers: As many of you know, it has been very hard to keep on top of the lab bin situation. Many people have been patiently waiting for weeks/months for bins to get freed up as we try to track down their owners. We also have difficulty with WIP ("Wafers In Progress") that get left in the lab and takes up needed shelf space. In an ideal world, everything in the lab should be in use or in process over the course of a month. Although this is not an ideal world, we can certainly try to keep on top of lab bins -- and personal items (WIP) in the lab -- so... we are going to try a new system. Here it is: Each month, all WIP and personal storage bins need to be marked with an appropriately colored DOT. For the month of February, the dot color is PURPLE. Lab bins should have a PURPLE dot on the front as well as the Coral login of the bin owner. The bin owner should be a current labmember with significant equipment activities over each of the past three months (greater than two hours/month). All WIP boxes stored outside of personal bins (on WIP shelves) must have a PURPLE dot. Anything that is not marked with a PURPLE DOT may be removed or reassigned. This is the same system as is used for personal bunnysuits in the gowning room. The color for February in the gowning room is also PURPLE. Any hangers not marked with a PURPLE tyrap will be removed. The key date is Monday, February 11. If you would like to keep your personal bin, WIP, and bunnysuit hanger for the month of February, please make sure your items are marked with PURPLE by this date. Anything that is not marked by this date may be removed or reassigned. You can find PURPLE dots and tyraps posted on the gowning room door. We recognize and apologize deeply for the inconvenience this will cause, but hope that with everyone's participation, this will lead to less clutter and better use of storage space in the lab for all. Thanks for your attention -- Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From pleu at stanford.edu Mon Jan 28 23:21:28 2008 From: pleu at stanford.edu (Paul Leu) Date: Tue, 29 Jan 2008 01:21:28 -0600 Subject: University Ph.D. Oral Examination : Paul W Leu Message-ID: <000001c86247$90dcd210$b2967630$@edu> Semiconductor Nanowires: Modeling, Experiments, and Their Implications Paul W. Leu Department of Mechanical Engineering Advisors: Prof. Paul C. McInyre and Prof. Kyeongjae (KJ) Cho Friday, February 8th, 2008 3:00 PM (Refreshments served at 2:45 PM) CIS-X 101 Semiconductor nanowires (NWs) have the potential for a variety of nanoelectromechanical and nanodevice applications. This presentation discusses the electromechanical properties and electrical transport of semiconductor NWs. The first part of the talk covers the systematic study of the mechanical and electrical properties of small diameter (< 3 nm) silicon NWs under axial strain using ab initio density functional theory calculations. The values of Young's Modulus, Poisson ratio, band gap, effective mass, work function (WF) and deformation potentials were calculated for <110> and <111> oriented Si NWs. We performed a detailed study of the effects of axial strain on the band structure and electronic properties and attempt to predict the effect of strain on electronic transport properties. We found a dramatic decrease of the deformation potentials of Si NWs under strain, which may lead to a many fold increase of electron or hole mobilities. The decrease of deformation potentials occurs as NWs undergo a direct-to-indirect band gap transition and is concurrent to the increase of effective mass. We also found that quantum confinement in Si NWs acts as a built-in tensile strain, which splits conduction band valleys and decreases transport effective mass. The second part of the talk covers the fabrication of vertically aligned germanium NW structures and their transport and doping characterization. Dense vertical Ge NWs were grown epitaxially on Ge <111> substrates from Au catalysts. The NWs could be doped by the deposition of a conformal shell of boron-doped Ge around the vertical NWs. The NWs were encapsulated in highly conformal silica using an alternating layer deposition process to isolate and support them. Chemical mechanical polishing was used to planarize the samples and expose the Ge NW tips. The post-CMP cleaning was found to be important in removing slurry particles and contamination from the samples while leaving the Ge NWs intact. We probed the topography and electrical transport properties of these encapsulated vertical Ge NW structures using a probe station and conductive AFM. The NWs were shown to exhibit resistor-like IV characteristics when grown on p-type substrates and p-n junction rectifying behavior when grown on n-type substrates. All processes took place at temperatures below 400o C, a key requirement for monolithic 3-dimensional integration of semiconductor devices on Si integrated circuits. -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Wed Jan 30 11:04:06 2008 From: mbaran at stanford.edu (Maureen Baran) Date: Wed, 30 Jan 2008 11:04:06 -0800 Subject: Flash Drive was Found in the Gowning Room Message-ID: <20080130190406.4BDE165B2DA@smtp2.stanford.edu> Dear Labmembers, A flash drive or memory stick was found in the gowning room. The concerned labmember who turned in the memory stick said, the reason he picked it up is because it was very close to the trash can. He was afraid it would eventually fall into the trash. The flash stick is at my desk and I'm in cubicle # 41 on the first floor of the CIS building. Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From gloria.wong at stanford.edu Thu Jan 31 09:47:03 2008 From: gloria.wong at stanford.edu (Gloria Wong) Date: Thu, 31 Jan 2008 09:47:03 -0800 Subject: Reminder- University Ph.D. Oral Examination - Gloria Wong - Feb. 1st, 9:30AM Message-ID: <006a01c86431$5be7eb80$6600a8c0@Laptopsally> "An Investigation of the Work Function of Metal Gate Electrodes for Advanced CMOS Applications" Gloria Wong Department of Materials Science and Engineering Advisors: Bruce Clemens and Yoshio Nishi February 1st, 2008 9:30AM (Refreshments served at 9:15AM) CIS-X Auditorium Abstract: Scaling the gate length and oxide thickness of the metal oxide semiconductor field effect transistor (MOSFET) offers great potential to improve device performance and circuit density. While the polycrystalline silicon gate electrode offers process compatibility and a tunable interface work function, its susceptibility to charge carrier depletion and boron penetration into the channel region is driving the need to investigate alternative gate materials. The use of metals for the gate electrode eliminates these problems, and shows better compatibility with high-k gate dielectrics. In order to optimize transistor performance, metals with appropriate work functions for both NMOS and PMOS must be identified and integrated into the conventional CMOS process flow. In this work, both single metal and two-component metal gate systems were investigated to develop a fundamental understanding of the factors that influence the metal gate electrode work function. In the single metal case, tungsten was chosen for study as it is a well-known refractory material in IC processing. The work function was found to be ~0.3eV higher in evaporated electrodes than in sputter-deposited films, which may be related to differences in roughness, density, grain size and as-grown oxygen content observed by physical characterization. In the two-component systems, metal gates were fabricated using a stacked bilayer structure. In previous work, it was found that the work function can be controlled by the thickness of the underlayer metal (the layer closest to the oxide). Depending on the amount of diffusion, the influence of the overlayer on the atomic concentration at the dielectric interface varies. Three two-component systems were investigated: Nb-W, Ti-W and Pt-Ti. By selecting materials systems that exhibit differences in diffusion and phase formation (as predicted by their phase diagrams), the change in work function due to underlayer thickness and composition for all three metal pairs is elucidated. The diffusion behavior in bilayer metal gates was investigated using x-ray reflectivity of multilayer films and was also modeled to quantify the differences between these three metal-metal systems. The effect of composition on the work function was directly probed by fabricating alloy metal gate electrodes by co-sputtering. A non-linear behavior was observed where the work function is dominated by the lower work function constituent. Structural information on the alloy films was obtained using x-ray diffraction. Thermal stability of all three systems was demonstrated during extended anneals and the observed time-dependent diffusion behavior is proposed to be related to diffusion through the grain boundaries. -------------- next part -------------- An HTML attachment was scrubbed... URL: From shott at stanford.edu Thu Jan 31 13:32:51 2008 From: shott at stanford.edu (John Shott) Date: Thu, 31 Jan 2008 13:32:51 -0800 Subject: [POSSIBLE VIRUS:###] [Fwd: [GECOS] Heads up! --- university spear-fishing attack in progress] Message-ID: <47A23E83.5000203@stanford.edu> SNF Lab Members and CIS Building Occupants: I'm forwarding the following message from John Gerth in Computer Science who spends a lot of time worrying about network abuse, phishing schemes, computer breakins. As you'll see, there is a new generation of phishing scheme that appears to come from the university computer support desk that is asking for sensitive information such as your university ID and password. Please be aware of and skeptical of these attempts. It's no longer only the WaMu things about which you should be suspicious. Thanks, John -------------- next part -------------- An embedded message was scrubbed... From: John Gerth Subject: [GECOS] Heads up! --- university spear-fishing attack in progress Date: Thu, 31 Jan 2008 13:19:54 -0800 Size: 10747 URL: From mtang at stanford.edu Thu Jan 31 14:24:42 2008 From: mtang at stanford.edu (Mary Tang) Date: Thu, 31 Jan 2008 14:24:42 -0800 Subject: Process Grand Rounds, Friday, Feb. 8, 11:30-1 Message-ID: <47A24AAA.6050104@stanford.edu> Greetings labmembers -- You are invited to a (long overdue) Process Grand Rounds, to be held next Friday, Feb. 8, from 11:30-1 in the CIS 101 conference room. Labmembers are invited to present a processing problem to others in the lab community and solicit suggestions. All labmembers are welcome to come, either to present a problem or help brainstorm solutions. If you'd like to present a problem, let us know so we can put you on the schedule. Pizza will be provided. Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu