Donghyun Kim: Ph.D. Oral Defense Abstract

Donghyun Kim dhkim81 at stanford.edu
Fri Jul 18 18:02:34 PDT 2008


PhD Thesis Oral Examination


Candidate : Donghyun Kim
Advisor: Prof. Krishna Saraswat



Time : 9:15 am (Refreshments served at 9:00 am)
Date : Thursday, July 24, 2008
Location : CISX-101 Auditorium
http://campus-map.stanford.edu/index.cfm?ID=04-055




 Title: Theoretical Performance Evaluations of NMOS Double Gate FETs with 
High Mobility Materials : Strained III-V, Ge and Si


Abstract

As Si CMOSFET technology scales down to nanometer scale, it becomes extremely difficult to keep the same drive current due to limitations of channel mobility (μ), gate oxide scaling and parasitics. Currently, strained-Si is the dominant technology for high performance MOSFETs and increasing the strain provides a viable solution to scaling. However, looking into future nanoscale MOSFETs, it becomes important to look at novel channel materials such as strained SixGe(1-x) and strained III-Vs and new device structures.

There are two fundamental problems with these candidates. First, the main advantage of small transport mass to have high injection velocity may be undermined by low density of states which reduces the inversion charge and hence reduces drive current. Second, due to their small effective masses and small band gap combined with high electric fields applied in nanometer-scale devices, large band to band tunneling (BTBT) leakage current is a big concern.

To understand the physics and the performance limitation of nanoscale MOSFETs with high mobility channel materials, we have developed first, a new BTBT model which takes into account complete real and complex band structure, direct/phonon-assisted tunneling, and quantum confinement effect, second, a quantum transport simulator and third, a local pseudo-potential method (LPM) to calculate real and complex band structures of strained semiconductors. While the BTBT models in commercially available TCAD tools largely fail to predict accurate current even in silicon, our model is well matched to experimental results of PIN diodes fabricated on Si, Ge and GaAs, and heterostructure SiGe pMOSFETs.

We have investigated and benchmarked Double-Gate (DG)  n-MOSFETs with different channel materials (GaAs, InAs, InSb, Ge and Si). Our results show that with gate oxide thickness of 0.7 nm, small density of states (DOS) of these materials does not significantly limit the on-current (ION) and high μ materials still show higher ION than Si.  However, the high μ small bandgap materials like InAs, InSb and Ge, suffer from excessive BTBT current and poor SCE, which limits their scalability. InP has significantly higher ION and shorter intrinsic delay at a reduced IOFF,BTBT when compared to Si.

Strained (uniaxial and biaxial) InxGa1-x As may have a very good tradeoff between the excellent transport properties of InAs and the low leakage of GaAs. Full quantum ballistic simulations with new BTBT models based on the bandstructures calculated by LPM shows that at a l00nA/ μ m Ioff specification, 4% biaxial compressive strained In0.75Ga0.25As (111) NMOS DGFET outperforms other InGaAs compositions because of the excellent transport properties and  reduced leakage current with strain engineering.

The power dissipation in nanoscale-MOSFET becomes a huge concern. Reducing VDD is limited by fundamental 60mV/dec turn-off. Band-to Band Tunneling FET (zener mode TFET) is being investigated to overcome 60mV/dec sub-threshold slope, where the transport is dictated by tunneling through a source barrier (instead of diffusion over the barrier). We have experimentally demonstrated a DG, s-Ge, TFET exhibiting record Ion (240uA/um). We have developed a novel quantum transport TFET simulator and our simulations show that the lateral heterostructure is the most scalable approach to solving the ambipolar problem in TFETs.

 
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