From raymondawu at yahoo.com Sun Feb 1 12:18:23 2009 From: raymondawu at yahoo.com (Raymond Wu) Date: Sun, 1 Feb 2009 12:18:23 -0800 (PST) Subject: Native Oxide Removal Message-ID: <289661.73848.qm@web30006.mail.mud.yahoo.com> Hello, ? Does anyone know a good tool and recipe to get rid of native oxide layer? ? Regards, ? Ray -------------- next part -------------- An HTML attachment was scrubbed... URL: From nklejwa at stanford.edu Sun Feb 1 20:42:35 2009 From: nklejwa at stanford.edu (Nathan K) Date: Sun, 1 Feb 2009 20:42:35 -0800 Subject: The SNF Metal Users Survey - Please Take It! Message-ID: <6fb9796f0902012042k38dbfa90p273ed41bc591d399@mail.gmail.com> SNF Labmembers, If you use any of the SNF metal deposition tools - Gryphon, Metallica, Innotec, or SCT - please take a few minutes and fill out the SNF Metal Users Survey at the following location: http://www.surveymonkey.com/s.aspx?sm=phD77AoyrD9AZF7KcYWk6g_3d_3d Your input is essential - we want to know what you think about how the SNF is running, and help everyone get their work done faster. The survey results will be used to help determine new equipment capabilities and policies for the metal deposition tools. Let your voice be heard! Thank you for your help. Nathan Klejwa and the Metal Quality Circle From jprovine at stanford.edu Mon Feb 2 09:57:58 2009 From: jprovine at stanford.edu (J Provine) Date: Mon, 2 Feb 2009 09:57:58 -0800 (PST) Subject: Reminder seminar on Si Nanowire Location and Growth Control TODAY (feb 2) at 3pm in cis 101x Message-ID: <1731880017.5383731233597478755.JavaMail.root@zm08.stanford.edu> Hello: a reminder of the seminar today at 3pm in CIS 101x by Dr. Nathaniel Quitoriano from HP Labs. Title: Silicon Nanowire Location and Growth Direction Control: Enabling both Nanowire MOSFET Sensors and Nanowire/Nanotube Mechanical Resonant Chemical Sensing Abstract: Semiconducting nanowires (NWs) have promising properties suggesting future use in electronic, optical, and sensing applications. In this talk we present results on guiding vapor-liquid-solid (VLS) NW growth by growing NWs against the buried-oxide layer of a silicon-on-insulator (SOI) substrate. Using a (001) SOI substrate, we engineer NW growth in <110> directions against the substrate surface. Growth against the substrate surface enabled straightforward fabrication of top-gated, metal-oxide-semiconductor, field-effect transistors (MOSFETs) exhibiting an Ion/Ioff ratio ~10,000 and a subthreshold slope of ~150 mV/decade. In addition to the device results, we also discuss the structure and mechanism of this type of growth and how these surface NWs could be used as a chemical sensor possible in micro-fluidic channels. We also present exciting results using VLS NWs as differential-mass, resonant sensors. We show the resonant characteristics of these NWs and demonstrate their use as resonant sensors to specifically detect the presence of proteins through functionalization. In addition, we present our latest breakthrough in differential-mass resonant sensing, the use of single-crystal, Si nanotubes (NTs). We discuss the fabrication, materials characteristics and resonant properties of these NTs and their advantages over NWs for differential mass resonant sensing. Biosketch: In 2000, Nate Quitoriano received his Bachelor?s degrees in Electrical Engineering and Computer Science and Materials Science Engineering from the University of California, Berkeley and did research with Professor Tim Sands on an ohmic, transient-liquid-phase bond for semiconductors. Nate received his Ph.D. in Materials Science Engineering at the Massachusetts Institute of Technology under the supervision of Gene Fitzgerald and worked on III-V, lattice-mismatched semiconductors. After that, he worked in Stan William?s group at Hewlett-Packard Labratories under the direction of Ted Kamins where he studied Si and Ge nanowires for use as sensors and electrical devices. From mtang at stanford.edu Mon Feb 2 11:21:51 2009 From: mtang at stanford.edu (Mary Tang) Date: Mon, 02 Feb 2009 11:21:51 -0800 Subject: Laminar Flow Hood Repairs: metalica/sts dep Tuesday am Message-ID: <498747CF.9030006@stanford.edu> Hi all -- The Facilities crew is embarking on a series of repairs to the transfer fans which drive our laminar flow system. On Tuesday, 2/3, from 6:30-9:30 am, Transfer Fan #3 will be shutdown while repairs are made. There will be no laminar flow over the following areas: - The analytical/test room (zygo, woollam, etc) - metalica, sts dep, the little RTA's - ASM epi Although the tools themselves are not affected, there will be no particle control around them without the laminar flow during this time. There will be additional laminar flow shutdown notices as the Facilities crew make their way through the lab. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From tasyurek at stanford.edu Mon Feb 2 11:53:46 2009 From: tasyurek at stanford.edu (Emel Tasyurek) Date: Mon, 2 Feb 2009 11:53:46 -0800 Subject: highly doped Si pieces/wafer Message-ID: <74eb20160902021153j1cf3f39cl630edb9bbda09905@mail.gmail.com> Hi labmembers, does anyone have some highly doped Si pieces that I could use? I would also be interested in buying a single wafer from someone who is about to buy or has recently bought a 25-batch. n or p does not matter. Thanks, Emel Tasyurek -------------- next part -------------- An HTML attachment was scrubbed... URL: From rissman at stanford.edu Mon Feb 2 12:59:01 2009 From: rissman at stanford.edu (Paul Rissman) Date: Mon, 02 Feb 2009 12:59:01 -0800 Subject: SVTC and Toppan joint presentation - Monday, February 2nd, 3 pm Message-ID: <20090202205904.3BB4338C0E6@smtp-roam.stanford.edu> Reminder - today at 3 pm. --------------------------------------------------------------------------------------------------------------------------------------------------------- Wilbur Catabay of SVTC and representatives of Toppan Photomasks will be here Monday February 2nd at 3 pm in CIS 101 for a joint presentation. Topics to be discussed include: * SVTC company background * Making the transition of your project from SNF to SVTC * Toppan company background * E-beam lithography services at SVTC * Summary and timeline The representatives of SVTC and Toppan will be happy to hear your comments and questions. Refreshments will be served. From raymondawu at yahoo.com Mon Feb 2 21:46:59 2009 From: raymondawu at yahoo.com (Raymond Wu) Date: Mon, 2 Feb 2009 21:46:59 -0800 (PST) Subject: Masking material for KOH etching Message-ID: <22835.16179.qm@web30006.mail.mud.yahoo.com> In general, does anyone know a good masking material?for 45% KOH wet etching on bare silicon wafers? ? Ray -------------- next part -------------- An HTML attachment was scrubbed... URL: From aeonia at stanford.edu Tue Feb 3 18:20:51 2009 From: aeonia at stanford.edu (Hyeun-Su Kim) Date: Tue, 3 Feb 2009 18:20:51 -0800 Subject: Looking for a thermogravimetric Analyzer Message-ID: Hi All, I am looking for your help in hunting an instrument called 'thermogravimetric analyzer'. As far as I understand, it is an instrument that can heat up droplets of liquid and measure the weight loss of them. By doing this, you can measure the sublimation temperature of the liquid. If you know any lab that has this equipment, please let me know. Thank you for your attention. Hyeun-Su -------------- next part -------------- An HTML attachment was scrubbed... URL: From sclaussen at stanford.edu Thu Feb 5 14:05:36 2009 From: sclaussen at stanford.edu (Stephanie Claussen) Date: Thu, 5 Feb 2009 14:05:36 -0800 Subject: Photoresist as an adhesive in wafer bonding Message-ID: <1bd27f6d0902051405l55fcce17xb171eac40e536770@mail.gmail.com> Hi labmembers, We're experimenting with various options for wafer bonding, and someone has told me that photoresist can be used as a resilient adhesive if it is baked for a long period of time post-adhesion. Is there anyone who can provide me with more details on this process? Specifically, I'm interested in the temperature and time you bake the bonded samples and whether the bond holds up to subsequent later liftoff procedures, etc. Thanks so much, Stephanie Claussen -------------- next part -------------- An HTML attachment was scrubbed... URL: From aeonia at stanford.edu Thu Feb 5 15:13:15 2009 From: aeonia at stanford.edu (Hyeun-su Kim) Date: Thu, 5 Feb 2009 15:13:15 -0800 (PST) Subject: metalica log book is missing Message-ID: <531297896.4662831233875595386.JavaMail.root@zm03.stanford.edu> I am about to rub metallica, and I need to see the dep rates as well as my previous process data. If you took it at any reason, please bring it back ASAP. Thank you. From raymondawu at yahoo.com Thu Feb 5 22:31:14 2009 From: raymondawu at yahoo.com (Raymond Wu) Date: Thu, 5 Feb 2009 22:31:14 -0800 (PST) Subject: Si Anisotropic Etch Recipe Message-ID: <657976.17750.qm@web30008.mail.mud.yahoo.com> Does anyone know a recipe?that can?anisotropically etch Si to around 500 nm and that is also resistant to PR? ? Thanks, ? Ray -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Fri Feb 6 08:16:56 2009 From: mtang at stanford.edu (Mary Tang) Date: Fri, 06 Feb 2009 08:16:56 -0800 Subject: Si Anisotropic Etch Recipe/Process Clinic Monday In-Reply-To: <657976.17750.qm@web30008.mail.mud.yahoo.com> References: <657976.17750.qm@web30008.mail.mud.yahoo.com> Message-ID: <498C6278.5090005@stanford.edu> Dear Ray and Labmembers -- I would like to encourage everyone, especially those like Ray, who are in the process of putting together a process flow run sheet for your experiments, to attend the next Process Clinic/SpecMat, which is Monday, February 9, 2-4 pm, in the cubicle area near the main CIS entrance. Process staff will be on hand -- and senior labmembers are very welcome -- to help answer questions or brainstorm your particular process issue. If you are putting together a new process flow runsheet (and I am sure you should all know what a runsheet should look like, right? If you've any doubts, check here for examples: https://spf.stanford.edu/SNF/processes/runsheets), especially if you're a new labmember unfamiliar with the specific resources available at SNF, please come to the clinic. Hope to see you there! Mary Raymond Wu wrote: > Does anyone know a recipe that can anisotropically etch Si to around > 500 nm and that is also resistant to PR? > > Thanks, > > Ray > > -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mihuhou at stanford.edu Sun Feb 8 22:46:12 2009 From: mihuhou at stanford.edu (Ying Chen) Date: Sun, 8 Feb 2009 22:46:12 -0800 (PST) Subject: Anyone knows about Parylene coating around Stanford? Message-ID: <414331657.5267741234161972842.JavaMail.root@zm06.stanford.edu> Thanks a lot! Ying From mtang at stanford.edu Mon Feb 9 08:53:33 2009 From: mtang at stanford.edu (Mary Tang) Date: Mon, 09 Feb 2009 08:53:33 -0800 Subject: Process Clinic, Today @2 Message-ID: <49905F8D.6070904@stanford.edu> Hi all -- All are invited to the Process Clinic today (Monday) from 2-4 pm, in the cubicle area outside Maureen's office. Bring SpecMat requests, process/process runsheet questions, mask files for review, whatever. Keith Best will be here around 2:30 to answer questions about ASML capabilities (and just about anything else under the sun -- he's seen it all.) Hope to see you there -- Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From jprovine at stanford.edu Mon Feb 9 09:20:58 2009 From: jprovine at stanford.edu (J Provine) Date: Mon, 9 Feb 2009 09:20:58 -0800 (PST) Subject: reminder seminar today (2/9) 3-4pm in cis 101x Dennis Yost of Cavendish Kinetics on MEMS Non-Volatile Memory In-Reply-To: <350526176.6723351234199951139.JavaMail.root@zm08.stanford.edu> Message-ID: <501967753.6723971234200058749.JavaMail.root@zm08.stanford.edu> Hello everyone, reminder of the seminar today (2/9) in CIS 101X from 3 to 4pm. Speaker: Dennis Yost of Cavendish Kinetics Title: A MEMS platform: Non Volatile Memory and Beyond Abstract: Being a technology startup focused on device-level intellectual property instead of design IP presents a very broad set of challenges as well as some unique opportunities. The main challenge is overcoming the traditional MEMS challenge of developing a suitable platform technology that can support a wide variety of markets. The emergence of the ?R&D foundry? industry allows for the mainstream IC technologies to be used as platforms for developing process and device technology. The business opportunity arises from the fact that the traditional IC companies are not developing new devices, merely enhancing the performance of the existing ones. The only real exceptions are companies with analog/mixed signal background: STM, TI and ADI are examples of companies that have delivered new devices based on MEMS. This talk will discuss the challenges and approaches to creating a MEMS platform that is capable of delivering multiple technologies in a given flow. That is compatible with existing IC technologies. The first application is focused on using a MEMS switch as a nonvolatile memory. That switch is then used as a building block for creating additional devices using the same process flow to deliver an entire portfolio of products. Biosketch: Dennis Yost joined Cavendish Kinetics in March 2007 as CEO. Since 2006 he has been a member of the Cavendish Kinetics Board of Directors. Prior to joining Cavendish Kinetics, he was Vice President and General Manager of the CMP business unit at Novellus Systems Inc. Prior to Novellus, Dennis was Chief Operating Officer at Lightpath Technologies and was General Manager and Managing Director at Applied Materials Corp. Prior to Applied Materials, he held various engineering management and engineering positions with Texas Instruments Corp. including engineering manager in the Digital Light Products Components Group. Dennis also worked as a process engineer for Intel Corp. Dennis holds a Bachelor of Science and Master of Science in Electrical Engineering degree from Texas A&M University as well as a M.B.A. degree from Southern Methodist University. thanks, j From ahazeghi at stanford.edu Mon Feb 9 09:39:07 2009 From: ahazeghi at stanford.edu (Arash Hazeghi) Date: Mon, 9 Feb 2009 09:39:07 -0800 Subject: High-K lift off and Ebeam resist Message-ID: <001301c98add$4ed69120$ec83b360$@edu> Good morning lab members, I am trying to do lift off with Ebeam resist (ZEP 520) and a high-K (Alumina) + metal (Al) layer, I was wondering if anyone else has done this before and what method they used. Thanks, Arash -------------- next part -------------- An HTML attachment was scrubbed... URL: From huin at altadevices.com Mon Feb 9 10:50:12 2009 From: huin at altadevices.com (Hui Nie) Date: Mon, 9 Feb 2009 10:50:12 -0800 Subject: Any place can do MgF2/ZnSe AR coating nearby In-Reply-To: <414331657.5267741234161972842.JavaMail.root@zm06.stanford.edu> References: <414331657.5267741234161972842.JavaMail.root@zm06.stanford.edu> Message-ID: Welcome any information! From sclaussen at stanford.edu Mon Feb 9 11:13:05 2009 From: sclaussen at stanford.edu (Stephanie Claussen) Date: Mon, 9 Feb 2009 11:13:05 -0800 Subject: long white oven bake Message-ID: <1bd27f6d0902091113w47b85446n54d797ac2a055fbe@mail.gmail.com> Hi everyone, I was hoping to use the white oven in the lithography room for a very long bake (~24 hours) beginning tonight. Mahnaz asked that I send an email out to this list, to make sure no one will be needing it during this period, for example, for a bake of LOL2000. Please let me know if you are going to need it, and I will either postpone or take my samples out while you use it. Thanks, Stephanie -------------- next part -------------- An HTML attachment was scrubbed... URL: From amf at amfitzgerald.com Mon Feb 9 13:51:51 2009 From: amf at amfitzgerald.com (Alissa M. Fitzgerald) Date: Mon, 9 Feb 2009 13:51:51 -0800 Subject: Any place can do MgF2/ZnSe AR coating nearby In-Reply-To: References: <414331657.5267741234161972842.JavaMail.root@zm06.stanford.edu> Message-ID: <002401c98b00$9e13ac00$0600a8c0@minicat> I can recommend Reynard Corporation in southern California, they specialize in optical and AR film coatings. www.reynardcorp.com Contact Beth Kinchyk, (949) 366-8872 Best regards, Alissa Alissa M. Fitzgerald, Ph.D. Managing Member A.M. Fitzgerald & Associates, LLC 655 Skyway Rd. Suite 118 San Carlos, CA 94070 +1 (650) 592-6100 x101 phone +1 (650) 592-6111 fax www.amfitzgerald.com > -----Original Message----- > From: Hui Nie [mailto:huin at altadevices.com] > Sent: Monday, February 09, 2009 10:50 AM > To: labmembers at snf.stanford.edu > Subject: Any place can do MgF2/ZnSe AR coating nearby > > Welcome any information! > > From rschaevitz at stanford.edu Tue Feb 10 12:03:36 2009 From: rschaevitz at stanford.edu (Rebecca Schaevitz) Date: Tue, 10 Feb 2009 12:03:36 -0800 Subject: OSA/SPIE Seminar: Ashok Krishnamoorthy/ Sun Microsystems - Thurs. 2/12, 4pm, Ginzton AP 200 Message-ID: <975904830902101203o40a1f52clfbda58b19ad199d2@mail.gmail.com> The Optical Society of America/SPIE Stanford Student Chapter Presents: *Ashok V. Krishnamoorthy* *SUN Microsystems* *The Integration of Silicon Photonics & VLSI Electronics for Computing Systems Intra-connect* Thursday, Feb. 12, 2009 4:15pm, Ginzton Building, AP 200 Refreshments at 4:00pm *Abstract*: This talk will briefly review the progress and challenges in scaling computing systems and meeting computing systems interconnect needs. We will discuss the potential benefits and challenges for achieving extremely short-reach, low-energy optical-interconnects via the native integration of silicon photonics components with VLSI electronics and introduce the "macrochip" ? a collection of contiguous silicon chips enabled by optical proximity communication. *About our speaker*: Ashok V. Krishnamoorthy received his Ph.D under Prof. Sadik Esener in Applied Physics from UCSD with the thesis topic of the first free-space optically-interconnected CMOS neural network. After working on the research faculty of UCSD, he joined the Advanced Photonics Research Department of Bell Labs, led by Dr. David Miller to investigate methods of integrating optical devices including photodetectors, multiple quantum well modulators, and later VCSELs, to Silicon VLSI circuits. After joining Lucent New Ventures in 1999, he moved on to become President and CEO of AraLight as part of a Lucent Bell Labs spinout. After successfully launching the optical interconnect product and completing several customer trials, he sold the technology in 2003. He then joined SUN Microsystems' Physical Sciences Center and was soon named a Distinguished Engineer by Sun Microsystems and is currently their principal investigator for advanced optical interconnect development and silicon photonics. Ashok and his colleagues have achieved several technical milestones related to applied photonics technology. He also played the lead role in several optoelectronics industry milestones including: the first CMOS-based opto-electronic foundry service to disseminate Optoelectronic-VLSI technology to R&D institutions around the world; the first demonstrated parallel optics transmitter/receiver product using VCSELs with over 100Gb/s throughput, and the first 300meter opto-electronic backplane application demonstration using VCSELs integrated with switches. Dr. Krishnamoorthy has served as member and chair of several conference program committees for the Optical Society of America, the IEEE Laser and Electro-Optics Society (LEOS), and the IEEE Computer Society. He also serves on the technical advisory board for several optical technology start-ups and venture funds. He is an honorary member of Tau Beta Pi, Sigma Xi, and Eta Kappa Nu. For his contributions to optoelectronics, the Eta Kappa Nu society named him an Outstanding Young Electrical Engineer in 1999. He was presented the IEEE LEOS Distinguished Lecturer award for 2002 and 2003. For his technical inventions, he has been granted 40 patents. He has co-authored 150 technical publications in optoelectronics, 6 book chapters and contributed over 60 invited talks at international conferences. He was awarded the 2004 International Prize in Optics by the ICO for his contributions to optical interconnects and received the 2006 Chairman's award for Innovation by Sun Microsystems for his work on silicon photonic systems. He has also won several team awards, including Computerworld's Horizon award for innovation. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Krishnamorthy_Feb12_2009.pdf Type: application/pdf Size: 34805 bytes Desc: not available URL: From dt.schoen at gmail.com Tue Feb 10 12:13:40 2009 From: dt.schoen at gmail.com (David Schoen) Date: Tue, 10 Feb 2009 12:13:40 -0800 Subject: [Stanford Nanosociety Seminar] Friday 02/13, 12pm McCullough 115. Structure Property Relationships in Single Nanowire Devices Message-ID: Stanford Nanoscience & Nanotechnology Society* *Seminar: *Investigating Structure Property Relationships in Compound Semiconductors using Single Nanowire Devices *** ** ** David Schoen (Yi Cui group) *When: **Friday Feb. 13**th** 12pm * *Where: **McCullough Rm 115* *.* *Free Food **(pizza) **served at 11:45am* For more information please visit http://nanosociety.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From Farid.Zuberi at grandisinc.com Tue Feb 10 17:54:21 2009 From: Farid.Zuberi at grandisinc.com (Farid Zuberi) Date: Tue, 10 Feb 2009 17:54:21 -0800 Subject: Missing wafer box Message-ID: <887C381D359942449ABF950AC230469901D52B85B6@PDCSERVER.grandis.local> Hello all, I'm missing one clear box with blue cassette in it has about 18 to 20 bare silicon wafers. I think i forgot to picked up from alpha step. If any one knows or accidently have please let me know. On the top of the box it says Shengyuan wang. Thanks, Farid Zuberi From rparsa at stanford.edu Wed Feb 11 10:21:54 2009 From: rparsa at stanford.edu (Roozbeh Parsa) Date: Wed, 11 Feb 2009 10:21:54 -0800 (PST) Subject: Lecture on the prospects of an academic career - By Professor Behzad Razavi In-Reply-To: <315954818.5804551234376418644.JavaMail.root@zm06.stanford.edu> Message-ID: <1642511018.5804771234376514945.JavaMail.root@zm06.stanford.edu> Dear all, Please join us in a lecture on the prospects of an academic career by Professor Behzad Razavi of UCLA - "Life in the Ivory Tower". In this talk, Professor Razavi will focus on the realities of choosing an academic career; the lecture is followed by a Q&A session. The talk is open to the general public. What: Talk by Professor Razavi When: Thursday February 12, 2009, 11 am Where: CIS-X 101 We hope that it will shed light on some of your questions about choosing an academic career in the future. Arezou Keshavarz on behalf of the PSA-BA board http://psa.stanford.edu/ba -------------- next part -------------- A non-text attachment was scrubbed... Name: PSA-BA_Razavi_2009_02_12.jpg Type: image/jpeg Size: 67794 bytes Desc: not available URL: From bdai at stanford.edu Wed Feb 11 19:07:08 2009 From: bdai at stanford.edu (Bing Dai) Date: Wed, 11 Feb 2009 19:07:08 -0800 Subject: Venders for (111) Si Wafer Message-ID: <005301c98cbe$fdc41210$f94c3630$@edu> Dear labmembers, I'm looking for venders that provide (111) silicon wafers. Could anyone give some information? Thanks very much, Bing From dalyx at stanford.edu Thu Feb 12 11:21:32 2009 From: dalyx at stanford.edu (Dany-Sebastien Ly-Gagnon) Date: Thu, 12 Feb 2009 11:21:32 -0800 Subject: Reminder: OSA/SPIE Seminar: Ashok Krishnamoorthy/ Sun Microsystems - TODAY 4pm, Ginzton AP 200 Message-ID: <7f014b6b0902121121n12ebf468r599f33c2c8fa5b45@mail.gmail.com> The Optical Society of America/SPIE Stanford Student Chapter Presents: *Ashok V. Krishnamoorthy* *SUN Microsystems* *The Integration of Silicon Photonics & VLSI Electronics for Computing Systems Intra-connect* Thursday, Feb. 12, 2009 4:15pm, Ginzton Building, AP 200 Refreshments at 4:00pm *Abstract*: This talk will briefly review the progress and challenges in scaling computing systems and meeting computing systems interconnect needs. We will discuss the potential benefits and challenges for achieving extremely short-reach, low-energy optical-interconnects via the native integration of silicon photonics components with VLSI electronics and introduce the "macrochip" ? a collection of contiguous silicon chips enabled by optical proximity communication. *About our speaker*: Ashok V. Krishnamoorthy received his Ph.D under Prof. Sadik Esener in Applied Physics from UCSD with the thesis topic of the first free-space optically-interconnected CMOS neural network. After working on the research faculty of UCSD, he joined the Advanced Photonics Research Department of Bell Labs, led by Dr. David Miller to investigate methods of integrating optical devices including photodetectors, multiple quantum well modulators, and later VCSELs, to Silicon VLSI circuits. After joining Lucent New Ventures in 1999, he moved on to become President and CEO of AraLight as part of a Lucent Bell Labs spinout. After successfully launching the optical interconnect product and completing several customer trials, he sold the technology in 2003. He then joined SUN Microsystems' Physical Sciences Center and was soon named a Distinguished Engineer by Sun Microsystems and is currently their principal investigator for advanced optical interconnect development and silicon photonics. Ashok and his colleagues have achieved several technical milestones related to applied photonics technology. He also played the lead role in several optoelectronics industry milestones including: the first CMOS-based opto-electronic foundry service to disseminate Optoelectronic-VLSI technology to R&D institutions around the world; the first demonstrated parallel optics transmitter/receiver product using VCSELs with over 100Gb/s throughput, and the first 300meter opto-electronic backplane application demonstration using VCSELs integrated with switches. Dr. Krishnamoorthy has served as member and chair of several conference program committees for the Optical Society of America, the IEEE Laser and Electro-Optics Society (LEOS), and the IEEE Computer Society. He also serves on the technical advisory board for several optical technology start-ups and venture funds. He is an honorary member of Tau Beta Pi, Sigma Xi, and Eta Kappa Nu. For his contributions to optoelectronics, the Eta Kappa Nu society named him an Outstanding Young Electrical Engineer in 1999. He was presented the IEEE LEOS Distinguished Lecturer award for 2002 and 2003. For his technical inventions, he has been granted 40 patents. He has co-authored 150 technical publications in optoelectronics, 6 book chapters and contributed over 60 invited talks at international conferences. He was awarded the 2004 International Prize in Optics by the ICO for his contributions to optical interconnects and received the 2006 Chairman's award for Innovation by Sun Microsystems for his work on silicon photonic systems. He has also won several team awards, including Computerworld's Horizon award for innovation. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Krishnamorthy_Feb12_2009.pdf Type: application/pdf Size: 34805 bytes Desc: not available URL: From rahimes at stanford.edu Thu Feb 12 15:17:51 2009 From: rahimes at stanford.edu (Rahim Esfandyarpour) Date: Thu, 12 Feb 2009 15:17:51 -0800 (PST) Subject: Flash Memory is lost In-Reply-To: <244741530.6017801234480337892.JavaMail.root@zm03.stanford.edu> Message-ID: <1629896304.6019681234480671720.JavaMail.root@zm03.stanford.edu> Hello All, I left my flash memory in the CAD room with most of my designs, few days ago. if anyone has seen it please let me know. Best, Rahim From mvikram at stanford.edu Thu Feb 12 16:29:04 2009 From: mvikram at stanford.edu (Vikram Mukundan) Date: Thu, 12 Feb 2009 16:29:04 -0800 Subject: Vikram Mukundan Ph.D. defense (Tue, 17th Feb, CIS-X Aud) Message-ID: <001101c98d72$134e5a60$f5a540ab@Vikram> Title: Electrostatic Actuators in Aqueous Ionic Media for Applications in Cell Mechanics. University Oral Examination Vikram Mukundan Department of Mechanical Engineering Stanford University Advisor: Beth Pruitt Date: Tuesday, February 17, 2009 Time: 2pm (Refreshments served at 1:45pm) Location: CIS-X 101 (Auditorium) Abstract: Cells generate forces during physiological processes that are essential to cellular structure and function. Measurement of biological forces employ techniques that range from pN at the molecular level to microN at the single cell level. Microelectromechanical Systems (MEMS) have been increasingly used for biological measurements due to appropriate sensitivity, response times, size and force ranges. MEMS techniques that utilize passive sensors or employ external actuators may face constraints when used in ionic solutions. This thesis presents a water immersible MEMS electrostatic actuator for dynamic force sensing of single adherent cells. Operating electrostatic actuators in conducting liquid media requires minimizing ionic shielding and electrochemical corrosion. These primary challenges were overcome by exploiting the finite time interval required for the formation of the electric double layer. A high frequency signal which changes polarity at a faster rate than the relaxation time of the ions was used for actuation. The rectifying nature of electrostatic force and mechanical damping of higher harmonics leads to quasi-static actuation in ionic media. Circuit models were used to evaluate device behavior in a variety of conducting liquids. Comb-drive actuators fabricated in single crystal silicon were demonstrated to operate successfully in highly conducting media such as 150 mM Potassium Chloride and cell culture media and to apply deformations of up to around 10 microns and measuring forces with a resolution of around 300 pN. Single adherent cells were attached to a planar micro-tensile tester which was coupled to underwater actuators for direct on-chip force application. Stiffness and hysteresis properties were measured for Madin-Darby Canine Kidney (MDCK) cells cultured on the device. The dynamic response and relaxation of MDCK cells to applied step forces were also measured to examine their viscoelastic properties. From dt.schoen at gmail.com Fri Feb 13 09:34:46 2009 From: dt.schoen at gmail.com (David Schoen) Date: Fri, 13 Feb 2009 09:34:46 -0800 Subject: [Stanford Nanosociety Seminar] Today 02/13, 12pm McCullough 115. Structure Property Relationships in Single Nanowire Devices Message-ID: Just a Reminder. Stanford Nanoscience & Nanotechnology Society* *Seminar: *Investigating Structure Property Relationships in Compound Semiconductors using Single Nanowire Devices *** ** ** David Schoen (Yi Cui group) *When: TODAY! **Friday Feb. 13**th** 12pm * *Where: **McCullough Rm 115* *.* *Free Food **(pizza) **served at 11:45am* For more information please visit http://nanosociety.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mihuhou at stanford.edu Sat Feb 14 15:39:37 2009 From: mihuhou at stanford.edu (Ying Chen) Date: Sat, 14 Feb 2009 15:39:37 -0800 Subject: Is there a machine in CIS that can CVD Si? Message-ID: <00c001c98efd$802fdbe0$099a0c80@stanford.edu> Thanks a lot! Ying -------------- next part -------------- An HTML attachment was scrubbed... URL: From raymondawu at yahoo.com Sun Feb 15 11:59:31 2009 From: raymondawu at yahoo.com (Raymond Wu) Date: Sun, 15 Feb 2009 11:59:31 -0800 (PST) Subject: Does anyone know how to get the Kapton tape residue off the wafer after peeling it? Message-ID: <803788.7754.qm@web30006.mail.mud.yahoo.com> Thanks a lot! ? Ray -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Tue Feb 17 16:20:50 2009 From: mtang at stanford.edu (Mary Tang) Date: Tue, 17 Feb 2009 16:20:50 -0800 Subject: Laminar flow out over stsdep/metalica Thursday am Message-ID: <499B5462.5000803@stanford.edu> Hi all -- Facilities will be working on Transfer Fan 3 on Thursday morning, from 6:30-8:30. This means the laminar flow hoods will not be operational during that time above the following equipment: sts dep, metalica, epi1, p2, alphastep, ellipsometer. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From xrjiang at stanford.edu Tue Feb 17 18:10:21 2009 From: xrjiang at stanford.edu (Xirong Jiang) Date: Tue, 17 Feb 2009 18:10:21 -0800 Subject: Xirong Jiang Ph.D. Oral Examination (Friday February 20, 10am, Physics/ Astrophysics 102/103) Message-ID: <8681d8580902171810i197a2dbarf0bbc20a0e999aa3@mail.gmail.com> *Title: Study of Catalysts for Solid Oxide Fuel Cells and Direct Methanol Fuel Cells* University Oral Examination Xirong Jiang Physics Department Advisor: Prof. Stacey Bent Date: Friday, February 20, 2009 Time: 10 am (Refreshments served at 9:45 am) Locations: Physics/Astrophysics 102/103 (connected to the Varian building) Abstract: Fuel cells offer the enticing promise of cleaner electricity with lower environmental impact than traditional energy conversion technologies. Driven by the interest in power sources for portable electronics, and distributed generation and automotive propulsion markets, active development efforts in the technologies of both solid oxide fuel cell (SOFC) and direct methanol fuel cell (DMFC) devices have achieved significant progress. However, current catalysts for fuel cells are either of low catalytic activity or extremely expensive, presenting a key barrier toward the widespread commercialization of fuel cell devices. In this thesis, atomic layer deposition (ALD), a novel thin film deposition technique, will be employed to apply catalytic Pt to both SOFC and DMFC to increase the activity and utilization levels of the catalysts while simultaneously reducing the catalyst loading. For SOFCs, we are exploring the use of ALD for the fabrication of electrode components, including an ultra-thin Pt film for use as the electrocatalyst, and a Pt mesh structure for a current collector for SOFCs, aiming for precise control over the catalyst loading and catalyst geometry, and enhancement in the current collect efficiency. We choose Pt since it has high chemical stability and excellent catalytic activity for the O2 reduction reaction and the H2 oxidation reaction even at low operating temperatures. Working SOFC fuel cells have been fabricated with ALD-deposited Pt thin films as an electrode/catalyst layer. The measured fuel cell performance reveals that comparable peak power densities are achieved for ALD-deposited Pt anodes with only one-fifth of the Pt loading relative to DC-sputtered counterpart. In addition to the continuous electrocatalyst layer, a micro-patterned Pt structure has been developed via the technique of area selective ALD. By coating yttria-stabilized zirconia, a typical solid oxide electrolyte, with patterned (octadecyltrichlorosilane) ODTS self-assembled monolayers (SAMs), Pt thin films are grown selectively on the SAM-free surface regions. Features with sizes as small as 2 mm have been deposited by this combined ALD-mCP method. The area selective atomic layer deposited micro-patterned Pt structure has been applied to SOFC as a current collector grid/patterned catalyst for the fuel cells. An improvement in the fuel cell performance by a factor of 10 has been observed using the Pt current collector grids/patterned catalyst integrated onto cathodic La0.6Sr0.4Co0.2Fe0.8O3-?. To improve the utilization, stability and efficiency of catalysts for methanol oxidation for DMFCs, two strategies have been employed in this thesis. One approach is to use a core-shell structured catalyst, where ALD Pt is used to decorate dc-sputtered metal (Pd and Ru) as core-shell catalysts toward methanol oxidation. The activity of the metal catalysts is enhanced by the Pt shell. In addition, Pt decorated Ru is found to be more active than Pt decorated Pd, likely because water dehydrogenation, needed to provide a -OH to oxidize the CO, is more facile on Ru than on Pd. Another strategy we have employed is to replace or alloy Pt with Ru where both dc-sputtering and atomic layer deposition have been employed to fabricate PtRu catalysts of various Ru contents and tested as catalysts for methanol oxidation. The results indicate that the optimal stoichiometry of the alloys measured in 1 M MeOH and 16.6 M MeOH is Ru1Pt3 and Ru1Pt1, respectively. Both strategies are shown to reduce the Pt loading while achieving better utilization of the catalyst. -------------- next part -------------- An HTML attachment was scrubbed... URL: From fengj at stanford.edu Wed Feb 18 12:55:21 2009 From: fengj at stanford.edu (Jia Feng) Date: Wed, 18 Feb 2009 12:55:21 -0800 Subject: Jia Feng's University Oral Exam Message-ID: <1C90094B07B34D5B9DB0B00F85416A8C@JiaPC> Stanford University Ph.D. Oral Examination High-Performance Germanium-on-Insulator MOSFETs for Monolithic Three-Dimensional Integrated Circuits Based on Rapid Melt Growth Jia Feng Advisor: Prof. James D. Plummer Department of Electrical Engineering Date: Monday, Feb. 23, 2009 Time: 2:00 pm (Refreshments served at 1:30 pm) Location: Packard 202 As silicon CMOS devices scaled down to the nanometer regime, the signal delay and power consumption caused by interconnects have become increasingly important factors limiting the overall performance of integrated circuits (ICs). By stacking the circuits in the vertical direction, we can reduce the number and length of interconnects as well as integrating more functionalities on one chip. One of the major challenges in fabricating monolithic three-dimensional ICs (3D-ICs) is that when processing the upper layers of devices we cannot raise the temperature of the underlying metal interconnects above 400 oC. Germanium-on-insulator (GeOI) MOSFETs have become promising for 3D-ICs owing to their low processing temperatures. We have studied the rapid melt growth (RMG) method, which was invented by the Plummer group in 2003, and its application in the fabrication of monolithic 3D-ICs. Using simulations incorporating undercooling and random nucleation, we have found that in the RMG process the temperature of the liquid Ge is less than 1 K below the melting point before it crystallizes. In this temperature range, random nucleation probability is extremely small and no nucleation events occurred in the simulation, which agrees well with our previous experimental results and answers why we can obtain GeOI with high crystal quality by RMG. Then the RMG method was extended to 3D-IC fabrication by replacing rapid thermal annealing with laser annealing that can potentially melt Ge while avoiding heating the underlying metal interconnects above 400 oC. We investigated different schemes of laser annealing by simulation and experiment. Among them, scanning CW laser annealing has been found to be the most promising in terms of crystal quality. We have carried out experiments to study the fabrication of high-performance GeOI MOSFETs. We demonstrated the monolithic integration of GeOI p-FETs with bulk Si n-FETs based the RMG method. In order to solve the problem of high leakage current, we fabricated GeOI FinFETs and gate-all-around (GAA) MOSFETs. The leakage current has been successfully reduced, leading to 4 orders of magnitude improvement on the on/off ratio. In the GAA MOSFET experiments, we also studied low-temperature device processes for monolithic 3D-ICs. -------------- next part -------------- An HTML attachment was scrubbed... URL: From bdai at stanford.edu Wed Feb 18 15:21:51 2009 From: bdai at stanford.edu (Bing Dai) Date: Wed, 18 Feb 2009 15:21:51 -0800 Subject: Ebeam Lithography on SiN membrane Message-ID: <003a01c9921f$ae36fad0$0aa4f070$@edu> Dear labmembers, I'm wondering if anyone have experience with ebeam lithography on SiN membranes? Our chips have ~200nm SiN membrane on top of silicon. What's the relation between spin speed and resist thickness? And what's the easy way to measure the resist thickness in the fab? I found there's no standard program in Nanometrics for measuring resist on SiN membrane. Any input will be appreciated. Thanks, Bing From sbasumal at stanford.edu Wed Feb 18 15:59:08 2009 From: sbasumal at stanford.edu (Shrestha Basu Mallick) Date: Wed, 18 Feb 2009 15:59:08 -0800 Subject: Laser cutting of wafers Message-ID: <499CA0CC.8060009@stanford.edu> Hi all, I have some 150 mm SOI wafers that I want to send out for laser-cutting down to 100 mm. So far from talking to people, I know that Silicon Quest and Ultrasil are a couple of places that will do it. However, it seems that some of these places use resist/tape to protect the surface of the wafers which can leave residue later even after cleaning. I would like to keep the surface of my wafers as clean as possible. Does anybody have sort of experience with the above problem? Also, does anybody have any recommendations for which place is preferable? Thanks in advance for all suggestions -Shrestha From shott at stanford.edu Thu Feb 19 10:02:30 2009 From: shott at stanford.edu (John Shott) Date: Thu, 19 Feb 2009 10:02:30 -0800 Subject: Disk usage .... Message-ID: <499D9EB6.107@stanford.edu> SNF Lab Members: Not too long ago, we increased the user disk partition from something like 6 GB to more than 50 GB .... and we are already 95% full! If we hit 100% bad things will happen. Particularly if you are a big user .... as indicated by the list below .... can you look through your files and eliminate things that aren't needed? This is an ordered list of disk usage, in kilobytes, of folks that are using more than 200 MB. 1350350 mahnaz 703476 eenriquez 645514 pcastle 613517 naiqian 494714 maurice 443374 mvikram 429176 chen0622 418726 jperez 413826 gunjim 411515 gyama 405825 salazarj 371267 hyunjoo 350713 ifushman 343827 acopland 339883 ndhuang 332442 akhan 327578 bchui 321444 dgunning 315496 vossough 312744 true 308809 sdogbe 256099 mislam 255568 ywidjaja 247530 mcvittie 235379 vlordi 216306 takuyan 215863 pnataraj 212200 dinhthuc 209140 rostam Thanks for your hekp, John From chongxie at stanford.edu Fri Feb 20 11:00:43 2009 From: chongxie at stanford.edu (Chong Xie) Date: Fri, 20 Feb 2009 11:00:43 -0800 (PST) Subject: PDMS Dry etching In-Reply-To: <337894801.1363781235156429210.JavaMail.root@zm02.stanford.edu> Message-ID: <733183661.1363851235156443816.JavaMail.root@zm02.stanford.edu> Dear labmembers, I am trying to do a little dry etching on PDMS (1 um or so). A quick search tells me O2 CF4 mixture will do the job, but it will be wonderful that anyone could tell me which machine to go and some parameters. Any input will be helpful. Thanks in advance and have a good weekend! chong From mbaran at stanford.edu Fri Feb 20 13:46:08 2009 From: mbaran at stanford.edu (Maureen Baran) Date: Fri, 20 Feb 2009 13:46:08 -0800 Subject: SNF Bake Sale Message-ID: <20090220214608.E8CB351C679@smtp2.stanford.edu> The SNF Staff needs your help in kicking off the first in a series of SNF Bake Sales to help support our fellow lab member and great friend to the staff, Jasmine Hasi participate in her FIRST "Breast Cancer 3 Day Walk Benefiting Susan G. Komen for the Cure". (I think that was a run-on sentence however) she has decided to (unselfishly) devote the majority of her free time for the next several months to train for this 3 day challenge. This challenge will be a 60 mile San Francisco Bay Area Journey that will begin on Friday, October 2nd and continue each day for 20 mile to its conclusion on Sunday, October 4th. We have picked Tuesday, February 24th - Mari Gras (Fat Tuesday) to kick off the series of bake sales at SNF. There are several ways you can support Jasmine's journey either by donating a bake good to the bake sale and or bring lots of money to purchase all the wonderful treats we will have and our all time favorite that works well, is a cash donation to the effort. Please mark your calendar for all the upcoming bake sales starting with Tuesday, February 24th followed by: St. Patrick's Day - Tuesday, March 17th Tax Day - Wednesday, April 15th Cinco De Mayo - Tuesday, May 5th The location of our first bake sale will be in office 146. Thank you in advance for any help you can give us. Sincerely, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From raneeyoo at stanford.edu Fri Feb 20 16:51:45 2009 From: raneeyoo at stanford.edu (Kyeongran Yoo) Date: Fri, 20 Feb 2009 16:51:45 -0800 (PST) Subject: Ni etchant? Message-ID: <1712824141.1211501235177505785.JavaMail.root@zm06.stanford.edu> Dear labmembers, I am wondering about Ni wet etchant over PR masking. If you know, could you please let me know? thank you so much and have a nice weekend! best, Kyeongran From mtang at stanford.edu Sun Feb 22 23:19:35 2009 From: mtang at stanford.edu (Mary Tang) Date: Sun, 22 Feb 2009 23:19:35 -0800 Subject: Process Clinic, Monday, 2/23 @ 2 Message-ID: <49A24E07.8060205@stanford.edu> Hi all -- All are invited to the Process Clinic today (Monday) from 2-4 pm, in the cubicle area outside Maureen's office. Bring SpecMat requests, process/process runsheet questions, mask files for review, whatever. Keith Best will be here to answer questions about ASML capabilities (and just about anything else we do in the lab, as he's seen it all.) Hope to see you there -- Your SNF Staff From mtang at stanford.edu Sun Feb 22 23:30:47 2009 From: mtang at stanford.edu (Mary Tang) Date: Sun, 22 Feb 2009 23:30:47 -0800 Subject: A good cause - on behalf of a fellow labmember Message-ID: <49A250A7.6000407@stanford.edu> Dear labmembers -- I'm posting this on behalf of a fellow labmember. Chris McGuiness, will be traveling to New Zealand on March 7 to raise money for the Shriner's Hospital, an organization dedicated to helping children with orthopedic conditions. It's hard to imagine that Chris was once a patient, as we all know him now as an avid rock climber and Iron Man competitor. To learn about Chris' story and how you can help him, go to: http://www.stanford.edu/~cmcg Good luck, Chris! From fengj at stanford.edu Mon Feb 23 11:55:11 2009 From: fengj at stanford.edu (Jia Feng) Date: Mon, 23 Feb 2009 11:55:11 -0800 Subject: Reminder: Jia Feng's University Oral Exam, Today, 2pm, Packard 202 In-Reply-To: <1C90094B07B34D5B9DB0B00F85416A8C@JiaPC> References: <1C90094B07B34D5B9DB0B00F85416A8C@JiaPC> Message-ID: <841487469FE7444C8F64F52D53256E76@JiaPC> ----- Original Message ----- From: Jia Feng To: cis-people at cis.stanford.edu Cc: labmembers at snf.stanford.edu Sent: Wednesday, February 18, 2009 12:55 PM Subject: Jia Feng's University Oral Exam Stanford University Ph.D. Oral Examination High-Performance Germanium-on-Insulator MOSFETs for Monolithic Three-Dimensional Integrated Circuits Based on Rapid Melt Growth Jia Feng Advisor: Prof. James D. Plummer Department of Electrical Engineering Date: Monday, Feb. 23, 2009 Time: 2:00 pm (Refreshments served at 1:30 pm) Location: Packard 202 As silicon CMOS devices scaled down to the nanometer regime, the signal delay and power consumption caused by interconnects have become increasingly important factors limiting the overall performance of integrated circuits (ICs). By stacking the circuits in the vertical direction, we can reduce the number and length of interconnects as well as integrating more functionalities on one chip. One of the major challenges in fabricating monolithic three-dimensional ICs (3D-ICs) is that when processing the upper layers of devices we cannot raise the temperature of the underlying metal interconnects above 400 oC. Germanium-on-insulator (GeOI) MOSFETs have become promising for 3D-ICs owing to their low processing temperatures. We have studied the rapid melt growth (RMG) method, which was invented by the Plummer group in 2003, and its application in the fabrication of monolithic 3D-ICs. Using simulations incorporating undercooling and random nucleation, we have found that in the RMG process the temperature of the liquid Ge is less than 1 K below the melting point before it crystallizes. In this temperature range, random nucleation probability is extremely small and no nucleation events occurred in the simulation, which agrees well with our previous experimental results and answers why we can obtain GeOI with high crystal quality by RMG. Then the RMG method was extended to 3D-IC fabrication by replacing rapid thermal annealing with laser annealing that can potentially melt Ge while avoiding heating the underlying metal interconnects above 400 oC. We investigated different schemes of laser annealing by simulation and experiment. Among them, scanning CW laser annealing has been found to be the most promising in terms of crystal quality. We have carried out experiments to study the fabrication of high-performance GeOI MOSFETs. We demonstrated the monolithic integration of GeOI p-FETs with bulk Si n-FETs based the RMG method. In order to solve the problem of high leakage current, we fabricated GeOI FinFETs and gate-all-around (GAA) MOSFETs. The leakage current has been successfully reduced, leading to 4 orders of magnitude improvement on the on/off ratio. In the GAA MOSFET experiments, we also studied low-temperature device processes for monolithic 3D-ICs. -------------- next part -------------- An HTML attachment was scrubbed... URL: From mihuhou at stanford.edu Mon Feb 23 18:51:33 2009 From: mihuhou at stanford.edu (Ying Chen) Date: Mon, 23 Feb 2009 18:51:33 -0800 Subject: Can we do low temperature (lower than 200C) PECVD of doped Si in CIS? Message-ID: <002c01c9962a$cd9f1ec0$4d6318ac@stanford.edu> Thanks a lot! Ying -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Tue Feb 24 08:28:26 2009 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 24 Feb 2009 08:28:26 -0800 Subject: Found Cell Phone in the Gowning Room Message-ID: <20090224162827.78C1C200D3A@smtp3.stanford.edu> Dear All, A cell phone was given to me because it has been sitting in the gowning room since yesterday morning ringing off and on. If you think it is yours please send me a note with a short description of it. Thank you, Maureen Maureen Baran Stanford Nanofabrication Facility Lab Services Administrator mbaran at stanford.edu 650-725-3664 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Wed Feb 25 09:20:28 2009 From: mtang at stanford.edu (Mary Tang) Date: Wed, 25 Feb 2009 09:20:28 -0800 Subject: Cleanliness/Contamination Meeting, Friday, 2/27, 3 pm Message-ID: <49A57DDC.5040307@stanford.edu> Dear Labmembers -- Just a reminder that there will be a Cleanliness/Contamination meeting this Friday, 2/27, at 3 pm in CIS 101. The topics of discussion will be: 1. Quantifying contamination (lifetime testing). 2. Equipment groups and materials capability in Etch. 3. New equipment update (such as ALD) 4. Semiclean metal deposition and PVD ("clean" Cr, Ge, etc.) 5. More capable "gold" RTA 6. Documentation of contamination risk issues (going beyond "clean", "semiclean" and "gold.") - Summary of the last meeting can be found on the wiki: https://spf.stanford.edu/SNF/processes/cleantamination-group/mtg-3 - Labmembers with broader materials processing needs are welcome to attend and bring up issues. If you can't attend, please send a representative or contact Ed, John, Peter, Jim or me. - We will try to be more broadly strategic in this discussion. The technical details of implementation/characterization are being transferred over to the Quality Circles (such as STS etch in the Etch QC, Semiclean metal requests in the Metal QC.) Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From envy at ee.ucla.edu Wed Feb 25 13:32:54 2009 From: envy at ee.ucla.edu (Girish) Date: Wed, 25 Feb 2009 13:32:54 -0800 (PST) Subject: AZ 5214 Message-ID: HI Does anyone have unexpired AZ 5214 EIR resist that I can borrow? Thanks Girish From mmessana at stanford.edu Wed Feb 25 17:29:12 2009 From: mmessana at stanford.edu (Matthew W. Messana) Date: Wed, 25 Feb 2009 17:29:12 -0800 (PST) Subject: Lost Money Message-ID: <1068001260.2200551235611752580.JavaMail.root@zm03.stanford.edu> I found some cash in the gowning room. If you lost some and you think it was in the gowning room, send me an email and I'll get it back to you. Matt From shott at stanford.edu Wed Feb 25 19:22:37 2009 From: shott at stanford.edu (John Shott) Date: Wed, 25 Feb 2009 19:22:37 -0800 Subject: Disk usage .... part deux .... Message-ID: <49A60AFD.9010401@stanford.edu> SNF Lab Members: A number of you have noted that you seem to be using more disk space than you think you have in actual files. It turns out that a number of you have significant amounts of space consumed in your Mozilla/Firefox/Netscape caches. Probably 100 or more of you have over 50 MB in your cache and probably 300 more of you have between 10 MB and 50 MB. Since most of us aren't aware of exactly what we have in our cache, that's a lot of wasted space. So, the next time you are in the lab, I'd appreciate it if you would clean up your cache. If you are a Mozilla user, you should be able to open the Preferences item under the Edit menu. Under "Advanced" you should find an item labeled "Cache" and on that panel should be a button labeled "Clear Cache" that will empty the contents of your cache. Firefox should be fairly similar: there is also a Preferences item under the Edit menu. On the preferences panel, there is an icon labeled "Advanced". Click on that and then on the "Network" tab on the panel that appears and you will also be able to clear the cache. Thank you for your help .... most of us get little added value from the stuff in our cache and we'll all be happier if storage isn't an issue for those things that need to be stored on our machines. Thank you for your continued support, John From gloria at kovio.com Wed Feb 25 20:14:35 2009 From: gloria at kovio.com (Gloria Wong) Date: Wed, 25 Feb 2009 20:14:35 -0800 Subject: Dry Etch for TiN Message-ID: <0A734412B02624499172B7366A97336B1BFDC16B94@server.print-this.com> Dear Labmembers, I am looking for a dry etch for TiN. Does anyone have experience with this? Thanks in advance, Gloria -------------- next part -------------- An HTML attachment was scrubbed... URL: From megrubbs at stanford.edu Thu Feb 26 11:51:55 2009 From: megrubbs at stanford.edu (Melody Ellen Grubbs) Date: Thu, 26 Feb 2009 11:51:55 -0800 (PST) Subject: Thin, terraced SiO2/Si substrates for MOS capacitors In-Reply-To: <1637464139.146531235677724661.JavaMail.root@zm02.stanford.edu> Message-ID: <174256276.147461235677915501.JavaMail.root@zm02.stanford.edu> Hello, Does anyone have a process for making MOS capacitor quality, 10-1 nm thick stepped SiO2 on Si? The lateral step dimension just needs to be such that all 10 steps can be accommodated on a 4" wafer. Also, any information on how to make wedding cake (5-1 nm) SiO2 would be helpful as well. Thanks in advance, Melody Grubbs PhD Candidate Materials Science and Engineering Stanford University From mtang at stanford.edu Thu Feb 26 15:22:17 2009 From: mtang at stanford.edu (Mary Tang) Date: Thu, 26 Feb 2009 15:22:17 -0800 Subject: Cleanliness/Contamination Meeting, Friday, 2/27, 3 pm in CIS 101 Message-ID: <49A72429.2070408@stanford.edu> Hi all - Just a reminder of the cleanliness/contamination meeting Friday, 3 pm, in CIS 101. Summary from the last meeting can be found here: https://spf.stanford.edu/SNF/processes/cleantamination-group/mtg-4 (sorry, the last email pointed to an older summary.) Topics for discussion: 1. Carbon nanotube furnace. Albert 2. Quantifying contamination (lifetime testing). Jim McV 3. Equipment groups and materials capability in Etch. Ed, Jim McV 4. Semiclean metal deposition and PVD ("clean" Cr, Ge, etc.) Ed, Peter 5. More capable "gold" RTA. Ed If there's time: 6. New equipment update (such as ALD) 7. Documentation of contamination risk issues (going beyond "clean", "semiclean" and "gold.") Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From linyouc at stanford.edu Thu Feb 26 15:41:47 2009 From: linyouc at stanford.edu (Linyou Cao) Date: Thu, 26 Feb 2009 15:41:47 -0800 (PST) Subject: [Stanford Nano Society Seminar] Friday 02/27, 12pm, McCullough 115. A Comparative Survey of Plasmonic Waveguides and Optical Antennas In-Reply-To: <1411923877.185351235691372427.JavaMail.root@zm06.stanford.edu> Message-ID: <562477448.186721235691707801.JavaMail.root@zm06.stanford.edu> Stanford Nanoscience & Nanotechnology Society Seminar: A Comparative Survey of Plasmonic Waveguides and Optical Antennas? S. Ekin Kocabas ? (Prof. David A.B. Miller group) When: Friday Feb . 27 th ? 12pm Where: McCullough Rm 115 . Free Food (pizza) served at 11:45am For more information please visit http:// nanosociety .stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mahnaz at stanford.edu Thu Feb 26 15:32:56 2009 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Thu, 26 Feb 2009 15:32:56 -0800 Subject: TEST WAFERS is a must Message-ID: <49A726A8.60301@stanford.edu> Hello all, Few of you have complained about the the ring after development left on the wafer. With the lack of humidity control I am not sure what to tell you but please run a test wafer and develop it and look at it to make sure things are okay. I will try my best to run few wafers through litho area and confirm things. Here is the quote from facility. mahnaz We were informed this morning by Cogen that they shut down the pump that supply tower water to our glycol chiller yesterday for maintenance. It will be down for about ten days. This mean that we won't have dehumidification capability to the photolith area while the pump is down. From shott at stanford.edu Thu Feb 26 16:08:09 2009 From: shott at stanford.edu (John Shott) Date: Thu, 26 Feb 2009 16:08:09 -0800 Subject: Faint smell in building and lab .... Message-ID: <49A72EE9.1090604@stanford.edu> Lab Members: Nancy pointed out the faint "propane-like" smell in the lab that is most noticeable in and near the gowning area. Mary and I have conducted an extensive walking and sniffing tour and believe that it is something that is emanating from the CoGen plant next door. At this point we don't know what it is, but have called the plumbing shop and asked them to come out and see if they can track it down. The odor is actually stronger outdoors near the intersection of Via Ortega and Via Pueblo than it is in the building or the lab. We will keep you posted if/when we learn anything further but wanted to at least alert you to this odor, assure that it is not one of our "problem gases", and let you know what we know at the moment. Thank you for your continued support, John From shott at stanford.edu Thu Feb 26 16:37:54 2009 From: shott at stanford.edu (John Shott) Date: Thu, 26 Feb 2009 16:37:54 -0800 Subject: Smell in building/lab ...update. Message-ID: <49A735E2.7010107@stanford.edu> SNF Lab Members: Apparently Cogen is cleaning their cooling towers that are directly across the street from us. That operation began yesterday morning and is scheduled to be done by 5 p.m. today. So, hopefully, we will not be smelling that tomorrow once the cooling towers are filled with water and back in operation. Of course, that doesn't tell us exactly what the smell is, but I will ask Leonard Chan to follow up with Cogen to see exactly what that stuff is. Thank you for your continued support, John From mahnaz at stanford.edu Fri Feb 27 12:34:34 2009 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 27 Feb 2009 12:34:34 -0800 Subject: Yellow cabinets Message-ID: <49A84E5A.9080209@stanford.edu> Hello all, Today Mario and I spend some time to clean up some chemicals and relabel some bottles that during the inspection was flagged and we needed urgently to take care of them. I came across so many old chemicals and so many chemicals with yellow tag which is missing date, your name, or the name of chemical is missing. Y*ou have till Friday March 12th to take care of your Bottles, if needed come and get a new yellow tag and redo the label ( in many cases is needed).* *On Friday 13th *I will get rid of any bottles that does not have the proper information on it. by the way I need to be able to read it. Please do not send me email and telling me you can not because you are away on a conference...., as it is I am 150 emails behind. Find a labmember to help you with it. mahnaz