Reminder: Jia Feng's University Oral Exam, Today, 2pm, Packard 202

Jia Feng fengj at
Mon Feb 23 11:55:11 PST 2009

----- Original Message ----- 
  From: Jia Feng 
  To: cis-people at 
  Cc: labmembers at 
  Sent: Wednesday, February 18, 2009 12:55 PM
  Subject: Jia Feng's University Oral Exam

  Stanford University Ph.D. Oral Examination


  High-Performance Germanium-on-Insulator MOSFETs for Monolithic Three-Dimensional Integrated Circuits Based on Rapid Melt Growth


  Jia Feng

  Advisor: Prof. James D. Plummer

  Department of Electrical Engineering


  Date: Monday, Feb. 23, 2009

  Time: 2:00 pm (Refreshments served at 1:30 pm)

  Location: Packard 202


     As silicon CMOS devices scaled down to the nanometer regime, the signal delay and power consumption caused by interconnects have become increasingly important factors limiting the overall performance of integrated circuits (ICs). By stacking the circuits in the vertical direction, we can reduce the number and length of interconnects as well as integrating more functionalities on one chip. One of the major challenges in fabricating monolithic three-dimensional ICs (3D-ICs) is that when processing the upper layers of devices we cannot raise the temperature of the underlying metal interconnects above 400 oC. Germanium-on-insulator (GeOI) MOSFETs have become promising for 3D-ICs owing to their low processing temperatures. We have studied the rapid melt growth (RMG) method, which was invented by the Plummer group in 2003, and its application in the fabrication of monolithic 3D-ICs.

     Using simulations incorporating undercooling and random nucleation, we have found that in the RMG process the temperature of the liquid Ge is less than 1 K below the melting point before it crystallizes. In this temperature range, random nucleation probability is extremely small and no nucleation events occurred in the simulation, which agrees well with our previous experimental results and answers why we can obtain GeOI with high crystal quality by RMG.

     Then the RMG method was extended to 3D-IC fabrication by replacing rapid thermal annealing with laser annealing that can potentially melt Ge while avoiding heating the underlying metal interconnects above 400 oC. We investigated different schemes of laser annealing by simulation and experiment. Among them, scanning CW laser annealing has been found to be the most promising in terms of crystal quality.

     We have carried out experiments to study the fabrication of high-performance GeOI MOSFETs. We demonstrated the monolithic integration of GeOI p-FETs with bulk Si n-FETs based the RMG method. In order to solve the problem of high leakage current, we fabricated GeOI FinFETs and gate-all-around (GAA) MOSFETs. The leakage current has been successfully reduced, leading to 4 orders of magnitude improvement on the on/off ratio. In the GAA MOSFET experiments, we also studied low-temperature device processes for monolithic 3D-ICs.
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