Oral defense announcement - Daniel Witte

Daniel Witte dwitte at stanford.edu
Mon May 18 14:03:46 PDT 2009

Rapid laser crystallization of semiconductors for three-dimensional integration

Stanford University PhD Dissertation Defense

Daniel Witte (dwitte at stanford.edu)
Research Advisor: R. Fabian W. Pease
Department of Electrical Engineering

Time: Tuesday, May 26 @ 9.30 a.m. (refreshments served at 9:00 a.m.)

Location: Clark Center S360 (Third floor, through Peet's Coffee & Tea)


Three-dimensional integration of semiconductor devices can yield
advantages in circuit density, power consumption, and speed over
conventional integrated circuit (IC) technology in which all
transistors are fabricated in one plane. 3D integration allows circuit
functions to be split across multiple layers, which – for certain
kinds of circuits – allows significant reductions in average wire
length. Since wires are the dominant factor in determining logic
delay, this can result in faster systems. Vertical interconnect
densities of more than a million per square millimeter are critical to
achieving this advantage, and to do this, a monolithic approach is
required where circuit layers are fabricated sequentially on a single

The critical operation is obtaining single-crystal, device-quality
semiconductor material on upper circuit layers. We show that,
beginning from an amorphous silicon film deposited at low temperature
on a silicon dioxide substrate, a rapid laser crystallization process
using a 532nm Nd:YAG laser can form preferentially oriented crystals
with a <001> out-of-plane orientation. Best results were achieved with
pulse lengths 2ms and greater, on a thermally insulating
quartz substrate. By patterning the amorphous silicon film into neck
structures, a single <001> crystallite can be selected to seed a
finger region 10µm in length and several microns wide. Carrier
mobility in these crystals can be above 900 cm^2/Vs for electrons and
250 cm^2/Vs for holes, and is comparable to SOI reference material.
These regions could be used for fabrication of devices, or as seed
material for further crystallization. A technique such as rapid melt
growth (RMG) could be used to propagate these crystals over an entire
die. Simulation shows that this can be done without damaging circuit
layers underneath, by keeping their temperature below 400 degrees
Celsius. The combination of preferentially oriented seed
crystallization with an RMG approach would allow the fabrication of
multiple circuit layers on a single wafer in a sequential, monolithic
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