PhD Orals - Filip Crnogorac, FRIDAY, Nov. 20; 1:00pm

Filip Crnogorac filip at
Mon Nov 16 12:26:55 PST 2009

Please join me for my defense on FRIDAY, 1pm at Clark Auditorium.
Looking forward to seeing you there,

“Semiconductor Crystal Islands for 3-Dimensional Integration”

Stanford University PhD Dissertation Defense

Filip Crnogorac (filip at
Research Advisor: R. Fabian W. Pease
Department of Electrical Engineering

Time: Friday, November 20th, @ 1:00 pm
(refreshments served at 12:45 pm)

Location: Clark Center Auditorium
(Basement, entrance across from Nexus)


The critical operation needed to achieve 3-dimensional integrated  
circuits is obtaining single-crystal, device-quality semiconductor  
material on upper circuit layers without damaging circuits below  
(400°C temperature limit). Simulation shows that microsecond pulse  
532nm Nd:YAG laser can melt and crystallize amorphous Si or Ge layers  
without heating the circuit layers underneath. However, experimental  
results of unseeded (graphoepitaxy) and seeded (RMG) crystallization  
of Si and Ge indicate that much longer pulse lengths are required for  
high quality single crystal formation, rendering the approach not 3DIC  

A more straightforward approach is to directly attach high quality  
crystal islands for upper layer device fabrication. A variety of  
viable low-temperature (≤400°C) bonding methods have been  
investigated: fusion bonding (SiO2-SiO2, Si-SiO2, Ge-SiO2), thermo-
compressive bonding (Cu-Cu, Ti-Ti), as well as AlGe eutectic bonding.  
The unique advantages of AlGe technique for 3DICs are reported for the  
first time. They include superior bond strength, low void formation,  
no roughness requirement, use of thin films and CMOS friendly  
materials. Finally, we present a full 3DIC compatible process of  
obtaining single crystal Si or Ge islands for upper layer device  
fabrication via SmartCut(TM) and CMP finish.


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