Reminder: EE PhD Oral Defense - Chia-Yu Chen, Monday, May 3, 2010; 9-11am, CIS-X Auditorium

Chia-Yu Chen yu0528 at
Fri Apr 30 16:26:17 PDT 2010

Stanford University Ph.D. Dissertation Defense 

Title: “Low frequency noise in advanced MOS transistors” 
Chia‐Yu Chen
Department of Electrical Engineering
Research Advisor: Prof. Robert W. Dutton
Date: Monday, May 3rd, 2010
Time: 9:00 am (Refreshments beforehand)
Location: CIS‐X 101 (Auditorium)

When scaling down device size and power supply, noise becomes more and more important in the future IC technology. However there are still fundamental issues in low frequency (LF) noise. This talk will address the fundamental mechanism of LF noise in advanced MOSFETs, which includes two parts: 

(a) Low frequency noise in hetero‐MOSFETs: 
The study starts from LF noise in p‐type Si/SiGe/Si buried channel MOSFETs and in standard surface channel p‐type MOSFETs. Through the comparison between buried channel and surface channel MOSFETs the effects from surface and from bulk are separated and the detailed LF noise mechanisms in the whole gate bias conditions can be discussed. To clarify the LF noise origin advanced TCAD simulations and noise characterization are used and a complete picture of LF noise mechanism in MOSFETs is provided. 
(b) Low frequency noise in scaled MOSFETs: 
In the second part of talk we studied LF noise in scaled MOSFETs. When scaling down the device size to nano‐meter level LF noise becomes different and random telegraph noise (RTN) is observed. Through measurements in different gate bias conditions and TCAD simulations a complete picture of LF noise origin in scaled MOSFETs is suggested. 

This study lays groundwork for device LF noise performance optimization and provides physical insights of LF noise for IC designers. 

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