PhD Oral Examination - Gaurav Thareja, Friday (tomorrow), August 20, 2010; 1:00 p.m. (food at 12:40p), Allen Bldg. 101X

Gaurav Thareja gthareja at stanford.edu
Thu Aug 19 15:49:17 PDT 2010


Surface Passivation and Source/Drain Junction Engineering in Germanium Field-Effect Transistors for High Performance CMOS
(PDF attached)

Gaurav Thareja
Advisor: Prof. Yoshio Nishi
Co-Advisor: Prof. Krishna Saraswat
PhD Committee - Prof. Paul McIntyre, Prof. Jelena Vuckovic

Date: Friday, Aug 20th, 2010
Time: 1:00pm (Food at 12:40p)
Location: Allen Auditorium (101X)
http://cis.stanford.edu/misc/directions.html

Germanium (Ge) has emerged as an important materials platform during
recent years. With its high carrier mobility and the ability to detect
and emit photons at telecommunications wavelengths, Ge is an
attractive candidate for applications in both high performance
electronics and optoelectronics. Moreover due to its compatibility
with conventional CMOS fabrication, it can be processed using the
standard manufacturing techniques that are currently used for silicon.

However Ge does present a number of unique challenges that must be
overcome, including issues of surface passivation, low n-type dopant
solubility, and high dopant diffusivity.

In this talk, I will present my work summarizing three different
contributions to Ge MOS technology:

 (1) Ultra-thin GeO2 interfacial layers formed on Ge using Slot Plane
Antenna (SPA) radical oxidation including substrate orientation
independent growth rate and low interface state density (2E11
cm-2eV-1). Drive current enhancement and EOT reduction for planar Ge
MOSFETs will be demonstrated along with results of conformal oxidation
of three dimensional structures applied to Gate All Around (GAA)
MOSFETs.

(2) Ultra Shallow Junctions (USJ) [sub-10 nm junction depth] for Ge
using Plasma Immersion Ion Implantation (P-III). USJ are required in
order to reduce the Drain Induced Barrier Lowering (DIBL) effect in
high-performance short-channel transistors for the sub-22nm ITRS node.

(3) High n-type dopant activation (> 1E20 cm-3) using Laser Thermal
Processing (LTP). Theoretical modeling of LTP for Ge will be presented
along with well behaved n+/p Ge diodes (Ion/Ioff > 1E5, ideality
factor (η) < 1.2, low sheet/contact resistance 7E-7 ohm-cm2) and
MOSFETs
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