From mcvittie at cis.Stanford.EDU  Mon Mar  1 09:22:32 2010
From: mcvittie at cis.Stanford.EDU (Jim McVittie)
Date: Mon, 1 Mar 2010 09:22:32 -0800 (PST)
Subject: Ti etching in drytek1 or 4
In-Reply-To: <243970671.4555631267421553300.JavaMail.root@zm08.stanford.edu>
Message-ID: <Pine.LNX.4.44.1003010916550.25761-100000@cis.Stanford.EDU>

Hi,

Years ago, I used the poly etch process on Drytek 2 to etch Ti which was
on Al.  The Ti etch rate was about 200 A/m. If the laser endpoint is
working, you can see the reflectivity change at the interface. You can
confirm that the Ti is gone using the Nanospec in reflectivity mode.

   Jim 

On Sun, 28 Feb 2010, Kyung Hoae Koo wrote:

> 
> Hi labmembers
> 
> Has anybody etched Ti in drytek1 or 4? In Wiki, it says drytek1 or 4 can be used for Ti etching. But it doesn't specify about gas and etch rate. My samples are gold contaminated so I can't use p5000. If there are any tool for Au contaminated Ti etching rather than drytek, please let me know. Thank you in advance. 
> 
> Kyunghoae 
> 

-- 
--------------------------------------------------------------
James (Jim) P. McVittie, Ph.D.	        Sr. Research Scientist 
Paul G. Allen Building                  Electrical Engineering
Stanford Nanofabrication Facility       jmcvittie at stanford.edu
Stanford University             	Office: (650) 725-3640
Rm. 336X, 330 Serra Mall		Lab: (650) 721-6834
Stanford, CA 94305-4075			Fax: (650) 723-4659 




From tfung at silexos.com  Mon Mar  1 11:03:20 2010
From: tfung at silexos.com (Tracy Fung)
Date: Mon, 1 Mar 2010 11:03:20 -0800
Subject: STS nitride recipe
Message-ID: <004101cab971$dc192980$944b7c80$@com>

Does anyone have experience with recipes for silicon nitride using STS
PECVD?  

I'm currently using the standard ammonia recipe, are there any other
standard recipes that uses nitrogen?

 

Tracy Fung

 

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From mcvittie at cis.Stanford.EDU  Mon Mar  1 11:27:00 2010
From: mcvittie at cis.Stanford.EDU (Jim McVittie)
Date: Mon, 1 Mar 2010 11:27:00 -0800 (PST)
Subject: STS nitride recipe
In-Reply-To: <004101cab971$dc192980$944b7c80$@com>
Message-ID: <Pine.LNX.4.44.1003011123440.25761-100000@cis.Stanford.EDU>

Tracy,

The SNF has just ordered a low temperature PECVD system from Plasma-Therm
which deposits nitride at below 100C using N2 with SiH4. The Tool will be
delivered in June. It also has a low temp oxide dep process.

	Jim 

On Mon, 1 Mar 2010, Tracy Fung wrote:

> Does anyone have experience with recipes for silicon nitride using STS
> PECVD?  
> 
> I'm currently using the standard ammonia recipe, are there any other
> standard recipes that uses nitrogen?
> 
>  
> 
> Tracy Fung
> 
>  
> 
> 

-- 
--------------------------------------------------------------
James (Jim) P. McVittie, Ph.D.	        Sr. Research Scientist 
Paul G. Allen Building                  Electrical Engineering
Stanford Nanofabrication Facility       jmcvittie at stanford.edu
Stanford University             	Office: (650) 725-3640
Rm. 336X, 330 Serra Mall		Lab: (650) 721-6834
Stanford, CA 94305-4075			Fax: (650) 723-4659 




From robinhmb at yahoo.com  Mon Mar  1 12:10:00 2010
From: robinhmb at yahoo.com (Robin King)
Date: Mon, 1 Mar 2010 12:10:00 -0800 (PST)
Subject: STS nitride recipe
In-Reply-To: <Pine.LNX.4.44.1003011123440.25761-100000@cis.Stanford.EDU>
Message-ID: <696101.47446.qm@web111507.mail.gq1.yahoo.com>

Can someone tell us the expected date for it to be installed, characterized and available to users?  That would be useful info, thanks. 

--- On Mon, 3/1/10, Jim McVittie <mcvittie at cis.Stanford.EDU> wrote:

> From: Jim McVittie <mcvittie at cis.Stanford.EDU>
> Subject: Re: STS nitride recipe
> To: "Tracy Fung" <tfung at silexos.com>
> Cc: labmembers at snf.stanford.edu
> Date: Monday, March 1, 2010, 11:27 AM
> Tracy,
> 
> The SNF has just ordered a low temperature PECVD system
> from Plasma-Therm
> which deposits nitride at below 100C using N2 with SiH4.
> The Tool will be
> delivered in June. It also has a low temp oxide dep
> process.
> 
> ??? Jim 
> 
> On Mon, 1 Mar 2010, Tracy Fung wrote:
> 
> > Does anyone have experience with recipes for silicon
> nitride using STS
> > PECVD?? 
> > 
> > I'm currently using the standard ammonia recipe, are
> there any other
> > standard recipes that uses nitrogen?
> > 
> >? 
> > 
> > Tracy Fung
> > 
> >? 
> > 
> > 
> 
> -- 
> --------------------------------------------------------------
> James (Jim) P. McVittie, Ph.D.??? ?
> ? ? ? Sr. Research Scientist 
> Paul G. Allen Building? ? ? ? ?
> ? ? ? ? Electrical Engineering
> Stanford Nanofabrication Facility? ?
> ???jmcvittie at stanford.edu
> Stanford University? ? ? ? ?
> ?????? Office: (650) 725-3640
> Rm. 336X, 330 Serra Mall???
> ??? Lab: (650) 721-6834
> Stanford, CA 94305-4075???
> ??? ??? Fax: (650) 723-4659 
> 
> 
> 


From mcvittie at cis.Stanford.EDU  Mon Mar  1 12:57:01 2010
From: mcvittie at cis.Stanford.EDU (Jim McVittie)
Date: Mon, 1 Mar 2010 12:57:01 -0800 (PST)
Subject: STS nitride recipe
In-Reply-To: <696101.47446.qm@web111507.mail.gq1.yahoo.com>
Message-ID: <Pine.LNX.4.44.1003011248320.25761-100000@cis.Stanford.EDU>

Robin,

The orders for all the new tools just went out a few weeks and we are
still working on where they will be positioned. It is looking like serval
of existing tools will need to be moved. Once what we have settled on the 
positions and what has to be moved, we can start figuring what all has to 
be done and how long it will take. At this point it would be foolish to 
commit to a date when the new tools will be available to users. We are 
hoping they will be up by the end of summer but the permitting and details 
will dicate the true date.

	Jim 

On Mon, 1 Mar 2010, Robin King wrote:

> Can someone tell us the expected date for it to be installed, characterized and available to users?  That would be useful info, thanks. 
> 
> --- On Mon, 3/1/10, Jim McVittie <mcvittie at cis.Stanford.EDU> wrote:
> 
> > From: Jim McVittie <mcvittie at cis.Stanford.EDU>
> > Subject: Re: STS nitride recipe
> > To: "Tracy Fung" <tfung at silexos.com>
> > Cc: labmembers at snf.stanford.edu
> > Date: Monday, March 1, 2010, 11:27 AM
> > Tracy,
> > 
> > The SNF has just ordered a low temperature PECVD system
> > from Plasma-Therm
> > which deposits nitride at below 100C using N2 with SiH4.
> > The Tool will be
> > delivered in June. It also has a low temp oxide dep
> > process.
> > 
> > ??? Jim 
> > 
> > On Mon, 1 Mar 2010, Tracy Fung wrote:
> > 
> > > Does anyone have experience with recipes for silicon
> > nitride using STS
> > > PECVD?? 
> > > 
> > > I'm currently using the standard ammonia recipe, are
> > there any other
> > > standard recipes that uses nitrogen?
> > > 
> > >? 
> > > 
> > > Tracy Fung
> > > 
> > >? 
> > > 
> > > 
> > 
> > -- 
> > --------------------------------------------------------------
> > James (Jim) P. McVittie, Ph.D.??? ?
> > ? ? ? Sr. Research Scientist 
> > Paul G. Allen Building? ? ? ? ?
> > ? ? ? ? Electrical Engineering
> > Stanford Nanofabrication Facility? ?
> > ???jmcvittie at stanford.edu
> > Stanford University? ? ? ? ?
> > ?????? Office: (650) 725-3640
> > Rm. 336X, 330 Serra Mall???
> > ??? Lab: (650) 721-6834
> > Stanford, CA 94305-4075???
> > ??? ??? Fax: (650) 723-4659 
> > 
> > 
> >
> 

-- 
--------------------------------------------------------------
James (Jim) P. McVittie, Ph.D.	        Sr. Research Scientist 
Paul G. Allen Building                  Electrical Engineering
Stanford Nanofabrication Facility       jmcvittie at stanford.edu
Stanford University             	Office: (650) 725-3640
Rm. 336X, 330 Serra Mall		Lab: (650) 721-6834
Stanford, CA 94305-4075			Fax: (650) 723-4659 




From tryon16 at stanford.edu  Tue Mar  2 11:06:03 2010
From: tryon16 at stanford.edu (Larkhoon Leem)
Date: Tue, 2 Mar 2010 11:06:03 -0800
Subject: EE PhD Oral Examination - Larkhoon Leem, Wednesday, March 3rd, 2010, 
	3:00pm
Message-ID: <b2a6a2fa1003021106k7422bcfay25041b1b8afb6cfc@mail.gmail.com>

Magnetic Coupled Spin-Torque Device for Non-volatile Logic Applications

Stanford University Ph.D. Thesis Defense

Larkhoon Leem (tryon16 at stanford.edu)
Research Advisor: Professor James S. Harris
Department of Electrical Engineering

March 3, 2010 @ 3:00pm
(Refreshements served at 2:45pm)
Allen 101X Auditorium

Abstract

    Power consumption has become the key constraint in chip design,
since the MOSFET threshold voltage (VT) and hence the supply voltage
(Vdd) can no longer be scaled. This trend calls for new device
concepts such as Spintronics devices that are fundamentally different
from CMOS. However, the MOSFET-type Spintronics transistor has not
been demonstrated due to the technical difficulties in transporting
and detecting spin information. In this talk, I present an alternative
Spintronics logic device, Magnetic Coupled Spin Torque Device (MCSTD),
which is free from spin-injection, transport and detection problems.
It leverages spin torque transfer effect and magnetic dipole coupling
between spin-torque devices to modulate its magnetization reversal
energy barrier. Its device switching speed, signal inversion and
signal level restoration capabilities will be discussed. For device to
device level spin communication, MCSTD uses a novel interconnection
technique that efficiently converts spin (or magneto-resistance)
information to current amplitude difference information, which is then
converted back to spin information at the subsequent gates. In
micro-magnetic simulations, MCSTD-based NAND, NOR, XOR gates and a
three-stage ring oscillator have been demonstrated to estimate
realistic device speed and power consumption. The fabrication of 20nm
gap MCSTDs has been successfully completed in two different types of
spin-torque devices, i.e., Magnetic Tunnel Junction (MTJ) and
Spin-Valve (SV). They demonstrated the switching voltage modulation
depending on the magnetic moments of the input spin-torque devices.
The amount of voltage shifts ranged between 40~100mV, which is well
above thermal fluctuations. In addition, non-volatility of MCSTD opens
up very unique potential applications in future power management
techniques and smart sensor technologies. For example, MCSTDs can
replace SRAMs and pass gate transistors in reconfigurable logics such
as Field Programmable Gate Array (FPGA). Instant-on/off nature of
MCSTD enables low overhead system-level power gating scheme for
embedded devices. Also, MCSTD can be used as a magnetic sensor with
in-situ logic operations for error-resilient DNA microarray sensors.


From bayoung at stanford.edu  Tue Mar  2 16:51:16 2010
From: bayoung at stanford.edu (Betty Young)
Date: Tue, 2 Mar 2010 16:51:16 -0800 (PST)
Subject: EE PhD Oral Examination - Larkhoon Leem, Wednesday, March 3rd,
 2010,  3:00pm
In-Reply-To: <b2a6a2fa1003021106k7422bcfay25041b1b8afb6cfc@mail.gmail.com>
Message-ID: <1880475315.5244911267577476165.JavaMail.root@zm08.stanford.edu>


----- Original Message -----
From: "Larkhoon Leem" <tryon16 at stanford.edu>
To: labmembers at snf.stanford.edu
Sent: Tuesday, March 2, 2010 11:06:03 AM GMT -08:00 US/Canada Pacific
Subject: EE PhD Oral Examination - Larkhoon Leem, Wednesday, March 3rd, 2010,  3:00pm

Magnetic Coupled Spin-Torque Device for Non-volatile Logic Applications

Stanford University Ph.D. Thesis Defense

Larkhoon Leem (tryon16 at stanford.edu)
Research Advisor: Professor James S. Harris
Department of Electrical Engineering

March 3, 2010 @ 3:00pm
(Refreshements served at 2:45pm)
Allen 101X Auditorium

Abstract

    Power consumption has become the key constraint in chip design,
since the MOSFET threshold voltage (VT) and hence the supply voltage
(Vdd) can no longer be scaled. This trend calls for new device
concepts such as Spintronics devices that are fundamentally different
from CMOS. However, the MOSFET-type Spintronics transistor has not
been demonstrated due to the technical difficulties in transporting
and detecting spin information. In this talk, I present an alternative
Spintronics logic device, Magnetic Coupled Spin Torque Device (MCSTD),
which is free from spin-injection, transport and detection problems.
It leverages spin torque transfer effect and magnetic dipole coupling
between spin-torque devices to modulate its magnetization reversal
energy barrier. Its device switching speed, signal inversion and
signal level restoration capabilities will be discussed. For device to
device level spin communication, MCSTD uses a novel interconnection
technique that efficiently converts spin (or magneto-resistance)
information to current amplitude difference information, which is then
converted back to spin information at the subsequent gates. In
micro-magnetic simulations, MCSTD-based NAND, NOR, XOR gates and a
three-stage ring oscillator have been demonstrated to estimate
realistic device speed and power consumption. The fabrication of 20nm
gap MCSTDs has been successfully completed in two different types of
spin-torque devices, i.e., Magnetic Tunnel Junction (MTJ) and
Spin-Valve (SV). They demonstrated the switching voltage modulation
depending on the magnetic moments of the input spin-torque devices.
The amount of voltage shifts ranged between 40~100mV, which is well
above thermal fluctuations. In addition, non-volatility of MCSTD opens
up very unique potential applications in future power management
techniques and smart sensor technologies. For example, MCSTDs can
replace SRAMs and pass gate transistors in reconfigurable logics such
as Field Programmable Gate Array (FPGA). Instant-on/off nature of
MCSTD enables low overhead system-level power gating scheme for
embedded devices. Also, MCSTD can be used as a magnetic sensor with
in-situ logic operations for error-resilient DNA microarray sensors.


From lelewang at stanford.edu  Wed Mar  3 14:37:45 2010
From: lelewang at stanford.edu (Lele Wang)
Date: Wed, 3 Mar 2010 14:37:45 -0800 (PST)
Subject: Boron predeposition in Tylan5
Message-ID: <2132056469.3236781267655865207.JavaMail.root@zm01.stanford.edu>

Hi all,
Has anyone used tylan5 for predeposition of boron and measured the right sheet resistance? I did a predeposition at 1000 degree for 30 minutes, but get an unexpected high sheet resistance, about 800 OHMS/SQ. Then I did a dry oxidation at 900 degree for 30 minutes and did a BOE etching for 1 minute, but the resistance is still high, about 800 OHMS/SQ, should be less than 100 OHMS/SQ. What are the right steps before measure the resistance? Thanks.

Best,
Lele


From pradeep.nataraj at gmail.com  Wed Mar  3 15:56:09 2010
From: pradeep.nataraj at gmail.com (Pradeep Nataraj)
Date: Wed, 3 Mar 2010 15:56:09 -0800
Subject: Boron predeposition in Tylan5
In-Reply-To: <2132056469.3236781267655865207.JavaMail.root@zm01.stanford.edu>
References: <2132056469.3236781267655865207.JavaMail.root@zm01.stanford.edu>
Message-ID: <4d185dc91003031556i2cdb287br1a484eddaebb6a67@mail.gmail.com>

Lele,

I used to  950c for 30 min and Wet ox 15 min at 1000C and able to get
40Ohms/Sq. Even though my last run was came out high like around 150Ohms/Sq
which was 3 weeks ago.
There is some thing goig on with the tube,need to be fixed.

Pradeep

On 3/3/10, Lele Wang <lelewang at stanford.edu> wrote:
>
> Hi all,
> Has anyone used tylan5 for predeposition of boron and measured the right
> sheet resistance? I did a predeposition at 1000 degree for 30 minutes, but
> get an unexpected high sheet resistance, about 800 OHMS/SQ. Then I did a dry
> oxidation at 900 degree for 30 minutes and did a BOE etching for 1 minute,
> but the resistance is still high, about 800 OHMS/SQ, should be less than 100
> OHMS/SQ. What are the right steps before measure the resistance? Thanks.
>
> Best,
>
> Lele
>
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From bhardin at stanford.edu  Thu Mar  4 11:31:34 2010
From: bhardin at stanford.edu (Brian E Hardin)
Date: Thu, 4 Mar 2010 11:31:34 -0800
Subject: Nanosociety Meeting Friday @ 12:15pm, McCullough 115: Looking under 
	the bed: a study of nanowire properties that are often ignored
Message-ID: <69e1b16c1003041131k224e6990wf2c2568cbdfc2b1a@mail.gmail.com>

Erik Garnett will be discussing his recent work (published in Nature
Nanotechnology) about dopant profiling and surface analysis of Si nanowires.
The talk will began at 12:15pm in McCullough 115. Pizza will be served.


*Looking under the bed: a study of nanowire properties that are often
ignored*


*Erik Garnett
*

Material Science and Engineering

Postdoc in McGehee, Brongersma, and Cui Groups


*Abstract
*
Nanowires have received tremendous research attention in the last decade and
have been used to make solar cells, thermoelectrics, sensors, transistors,
batteries and resonators, often with improved properties over bulk devices.
However, there has been very littlle attention given to characterizing the
dopant distribution and surface state density, which are known to affect the
electrical properties in bulk devices and should impact nanoscale devices
even more due to the large surface to volume ratio.  The standard methods
for extracting nanowire doping concentration from field effect transistors
rely on several untested assumptions, while surface states are almost always
ignored in calculations.  This talk will discuss capacitance-voltage
measurements performed on individual silicon nanowires to extract the radial
dopant distribution and surface state density.  The standard assumptions
used in nanoelectronics research will be analyzed in the context of the
capacitance-voltage measurement results.
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From goldhab at stanford.edu  Sun Mar  7 22:38:19 2010
From: goldhab at stanford.edu (David Goldhaber-Gordon)
Date: Sun, 7 Mar 2010 22:38:19 -0800 (PST)
Subject: Nano workshop at Stanford, May 14
In-Reply-To: <1097109332.906861268030049794.JavaMail.root@zm08.stanford.edu>
Message-ID: <1808482981.907401268030299752.JavaMail.root@zm08.stanford.edu>

Dear SNF Labmembers,

On Friday May 14, Stanford's Center for Probing the Nanoscale will
present its 6th Annual Nanoprobes Workshop, on Stanford campus at the
Bechtel Conference Center. Nine outstanding speakers will describe
cutting-edge developments in imaging nanoscale electronic, magnetic,
optical, and chemical phenomena. This will be followed by a
student/postdoc poster session. You and your colleagues are warmly
invited to attend the workshop. Students are encouraged to present
posters -- we typically have many industry attendees who appreciate
having students explain their exciting work.

The website is open for registration till May 1. Details about
registration and speakers are below. Students and postdocs are free
but must register. Also see attached program.

Questions:
Laraine Lietz-Lucas, lietz at stanford.edu

Best wishes,
David Goldhaber-Gordon
Deputy Director, Center for Probing the Nanoscale, an NSF Nanoscale
Science and Engineering Center

Details:

Registration http://www.stanford.edu/group/cpn/research/anworkshop_reg.html

Registration Fee Structure:

Industry - $100
Academic and Government (except CPN Investigators) - $50
Community College, K-12, and Museum Personnel - $25
Students and CPN investigators are free but must register

Speakers:

Alexander Balatsky, Los Alamos National Laboratory
"Dirac Materials"

Irfan Siddiqi, University of California, Berkeley
"Noiseless Amplification in Superconducting Nanoscale Magnetometers"

Tetsuo Hanaguri, RIKEN Advanced Science Institute, Saitama, Japan
"Spectroscopic-Imaging STM at High Magnetic Fields"

Ray Ashoori, MIT
"Extremely High Energy Resolution Spectroscopy of Two-Dimensional Electronic Systems"

Roya Maboudian, University of California, Berkeley
"Probing Interfacial Contact via MEMS-based Instrumentation"

Wilson Ho, University of California, Irvine
"Single Spin Phenomena"

David A. Muller, Cornell University
"Atomic-Resolution Imaging of the Physical and Electronic Structure of Nano-Devices"

Keith Schwab, California Institute of Technology

Andreas Heinrich, IBM
"Measuring Spin Relaxation Times of Single Atoms with Nanosecond Time Resolution" 
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From mtang at stanford.edu  Mon Mar  8 08:44:31 2010
From: mtang at stanford.edu (Mary Tang)
Date: Mon, 08 Mar 2010 08:44:31 -0800
Subject: SNF Process Clinic, 2 pm today (Monday)
Message-ID: <4B95296F.4030709@stanford.edu>

Greetings labmembers --


Just a reminder that there is a Process Clinic today (Monday) from 2-4 
pm in the cubicle area outside of Maureen's office.  Staff and senior 
labmembers will be on hand to answer questions and brainstorm ideas to 
address process issues.  Bring your ideas, process questions, your 
process runsheets, device layouts, and whatever else.


Your SNF staff

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu



From pruitt at stanford.edu  Mon Mar  8 10:50:48 2010
From: pruitt at stanford.edu (Beth Pruitt)
Date: Mon, 8 Mar 2010 10:50:48 -0800
Subject: MEMS/neuroscience seminar -Thurs 4:15pm
Message-ID: <p06230954c7baf70b26ec@[10.32.146.126]>

CMOS MEMS for Mechanical Sensing and Neuroscience
Oliver Paul, Department of Microsystems Engineering (IMTEK)
University of Freiburg, Germany

Thursday March 11, 4:15pm
Bldg 60,  Room 120 (Main Quad next to Memorial Church)
http://campus-map.stanford.edu/

Piezoresistive mechanical sensing is currently experiencing a 
renaissance stimulated by such novel developments as piezoresistive 
field effect transistors with multiple source-drain contacts and 
sensor elements for the measurement of out-of-plane components of the 
stress tensor. The first part of the talk will present these sensors 
elements from their foundations to the realization of smart sensor 
systems for applications including smart orthodontic brackets, a 
three-dimensional surface coordinate measurement system, and sensor 
chips for packaging reliability studies. The second part is dedicated 
to results of the EU-financed project NeuroProbes, where 
intracortical neural probes for electrical and chemical sensing and 
stimulation have been developed by a consortium of 15 partners. 
CMOS-integrated microneedle probes with up to 188 electrode sites 
have advanced the state of the art in spatial resolution by such 
probes, enabling a richer picture of intracortical communication 
processes to be obtained. Finally, these two lines of research will 
be merged by the description of microneedle-shaped stress sensor 
arrays. These structures are designed to help neuroscientists to 
understand and minimize the mechanical probe-brain interaction during 
penetration and acute and chronic experiments.
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From duygu at stanford.edu  Mon Mar  8 11:11:04 2010
From: duygu at stanford.edu (Duygu Kuzum)
Date: Mon, 8 Mar 2010 11:11:04 -0800 (PST)
Subject: Seminar-Tailored Functional Oxides for Memory Applications
In-Reply-To: <757247400.7078771256780106710.JavaMail.root@zm03.stanford.edu>
Message-ID: <1727610690.5510511268075464704.JavaMail.root@zm03.stanford.edu>

Tailored Functional Oxides for Memory Applications

Dr. Koen Martens

Friday, March 12th, 2010, 2:30 pm 
CISX Auditorium 

Abstract:

In this project at IMEC the goal is to evaluate the possible use of Metal-Insulator Transition (MIT) materials for use in memory and transistor applications.  The first material of choice, one of the most prominent metal-to-insulator transition materials is the transition metal oxide vanadium oxide.  Several phases of this oxide exhibit a transition between a metallic and semiconducting state with changing temperature, doping content or by applying a light pulse or electric field.  The physical nature of this MIT phenomenon is under debate.  The question is whether the MIT in e.g. VO2 is caused by a Peierls (phonon assisted) or Mott transition (due to an electron correlation effect).  Harnessing a purely electronic Mott transition in a memory would imply a number of significant benefits: 1) very fast operation (< ~ps) 2) excellent scalability (uniformity, no filament formation as in typical RRAM) 3) good endurance (no material transport). In this project we aim to develop thin films of MIT materials (vanadium oxide), integrate them into MIM and TFT-type devices, characterize their properties and evaluate their potential for memory and transistor applications.   

V2O5 films are grown by means of ALD and V films are grown by means of DC sputtering.  The ALD process has been shown to be conformal in 100nm size contact holes for integration into MIM capacitors.  Reduction of the obtained V2O5 films to V6O13 and VO2 (B) phases has been shown to be possible by means of reducing thermal treatments in FGA and N2 ambient.  The influence of the substrate will be discussed.  However, the VO2 M1 phase, which shows the MIT at 68C, is not obtainable in this way by means of reduction in these gases at atmospheric pressure. Vanadium metal films have been oxidized.  At atmospheric pressure V2O5 is obtained, as expected.  Morphology issues and reduction behavior will be treated regarding oxidized vanadium films. Alternative ALD processes and annealing treatments will be discussed as well as electrical properties of the vanadium oxide films.       


Biography:

Koen Martens received the B.S. and M.S. degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 2001 and 2004. In january 2009 he obtained a PhD degree on the topic of germanium MOSFETs at the Katholieke Universiteit Leuven, Belgium and at IMEC.  In 2006 he was on an internship at Stanford University working on the electrical characterization of germanium MOSFETs.  Currently he is working as an FWO sponsored postdoctoral researcher on functional oxides with tailored properties for nanoelectronics with a focus on oxides showing a metal-to-insulator transition and RRAM.  


From lwchang at stanford.edu  Wed Mar 10 23:20:10 2010
From: lwchang at stanford.edu (Li-Wen Chang)
Date: Wed, 10 Mar 2010 23:20:10 -0800
Subject: PhD Oral Examination - Li-Wen Chang, Wednesday, March 17th, 2010, 
	1:00pm
In-Reply-To: <8ab79e461003090058g70d6e47bw5358db9e48a52c3@mail.gmail.com>
References: <8ab79e461003090058g70d6e47bw5358db9e48a52c3@mail.gmail.com>
Message-ID: <8ab79e461003102320u2975e774td31fe3b222bfd982@mail.gmail.com>

Device / Circuit Fabrication Using Diblock Copolymer Lithography

PhD Oral Examination
Speaker: Li-Wen Chang, Department of Materials Science and
Engineering, Stanford University
PhD Advisor: Prof. H.-S. Philip Wong

Time: 1pm (refreshments served at 12:45pm)
Date: Wednesday, March 17, 2010
Location: Allen 101X Auditorium

Abstract:
Silicon technology scaling has been continued for decades in order to
make smaller and faster devices. The scaling roadmap is essentially
enabled by the evolution of lithography technology. As conventional
lithography is reaching its resolution limit, there is still no
apparent solution for printing feature sizes beyond the 22 nm node. In
view of the escalating cost for improving the lithography tool,
industry is now using double patterning technique to enhance the
feature density without the need to change the infrastructure. As one
of the candidates for the Next Generation Lithography, block copolymer
lithography, ?has showcased its capability of delivering
self-assembled array of nanoscale features ranging from 30nm to 10nm,
through a self-assembly process.

Although ITRS projects block copolymer lithography to be used on 16 nm
technology node, no block copolymer lithography integration with
conventional CMOS process has been demonstrated. In this work, we
fabricated the top-gated FETs / inverters with 20 nm contact holes
patterned using block copolymer lithography. It is employed as a
double patterning technique with the second layer photoresist replaced
by block copolymers. The synergy of the conventional top-down
lithography with bottom-up self-assembly not only relaxes the pattern
dimension of the first layer generated by conventional lithography,
but also delivers final feature size that is solely determined by the
block copolymer systems. Alignment of the self-assembled contact holes
to the MOSFET source and drain is achieved with a unique guiding
layer. The self-assembly process is integrated with an existing CMOS
process flow using conventional tools on a full wafer level. The
design rule derivation for future device / circuit design integrating
bock copolymer lithography is also addressed.


From linyouc at stanford.edu  Thu Mar 11 22:50:13 2010
From: linyouc at stanford.edu (Linyou Cao)
Date: Thu, 11 Mar 2010 22:50:13 -0800 (PST)
Subject: FWD: available postdoc position on ultrafast optics
In-Reply-To: <1858998398.2268411267740665285.JavaMail.root@zm06.stanford.edu>
Message-ID: <112711095.4023431268376613100.JavaMail.root@zm06.stanford.edu>


We are writing to seek several postdoctoral associates for attosecond 
investigations of nanomaterials.  Through the good fortune of a Keck 
Foundation grant and a Senior Faculty Defense Fellowship (NSSEFF - 
Leone), we are building additional laboratories to produce isolated 
attosecond pulses by high harmonic generation and to use these pulses 
to study transient absorption and photoelectron spectroscopy of 
semiconductor and metal nanoparticles.   Problems range from plasmon 
oscillations and dephasing to exciton formation and decay. 
Successful candidates will ideally be adept with or willing to learn: 
carrier envelope phase stabilized lasers, high harmonic generation, 
and x-ray optical hardware, the building and maintaining of 
substantial vacuum equipment for the investigations, and solid state 
scientific expertise.  There are almost certainly opportunities in 
our operational gas phase attosecond laboratories as well. 
Interested candidates should write to either or both of us, send a CV 
and an email with a summary of graduate grades, and have three 
letters of reference sent to us by email.


Steve Leone (srl at berkeley.edu)

Dan Neumark (neumark at berkeley.edu)
-- 
===================================
Stephen R. Leone
209 Gilman Hall
Department of Chemistry
University of California
Berkeley, CA 94720

Professor of Chemistry and Physics
Director, Chemical Dynamics Beamline
	Lawrence Berkeley National Laboratory

Ph. 510-643-5467
Fax  510-643-1376
LBNL ph. 510-486-4754

Leone Group Web Page:

http://www.cchem.berkeley.edu/leonegrp/

Chemical Dynamics Beamline

http://www.chemicaldynamics.lbl.gov/


From duygu at stanford.edu  Thu Mar 11 23:40:37 2010
From: duygu at stanford.edu (Duygu Kuzum)
Date: Thu, 11 Mar 2010 23:40:37 -0800 (PST)
Subject: Reminder: (Friday, 2:30 pm)  Seminar-Tailored Functional Oxides for
 Memory Applications
In-Reply-To: <1727610690.5510511268075464704.JavaMail.root@zm03.stanford.edu>
Message-ID: <861895802.6522561268379637952.JavaMail.root@zm03.stanford.edu>

Tailored Functional Oxides for Memory Applications

Dr. Koen Martens

Friday, March 12th, 2010, 2:30 pm 
CISX Auditorium 

Abstract:

In this project at IMEC the goal is to evaluate the possible use of Metal-Insulator Transition (MIT) materials for use in memory and transistor applications.  The first material of choice, one of the most prominent metal-to-insulator transition materials is the transition metal oxide vanadium oxide.  Several phases of this oxide exhibit a transition between a metallic and semiconducting state with changing temperature, doping content or by applying a light pulse or electric field.  The physical nature of this MIT phenomenon is under debate.  The question is whether the MIT in e.g. VO2 is caused by a Peierls (phonon assisted) or Mott transition (due to an electron correlation effect).  Harnessing a purely electronic Mott transition in a memory would imply a number of significant benefits: 1) very fast operation (< ~ps) 2) excellent scalability (uniformity, no filament formation as in typical RRAM) 3) good endurance (no material transport). In this project we aim to develop thin films of MIT materials (vanadium oxide), integrate them into MIM and TFT-type devices, characterize their properties and evaluate their potential for memory and transistor applications.   

V2O5 films are grown by means of ALD and V films are grown by means of DC sputtering.  The ALD process has been shown to be conformal in 100nm size contact holes for integration into MIM capacitors.  Reduction of the obtained V2O5 films to V6O13 and VO2 (B) phases has been shown to be possible by means of reducing thermal treatments in FGA and N2 ambient.  The influence of the substrate will be discussed.  However, the VO2 M1 phase, which shows the MIT at 68C, is not obtainable in this way by means of reduction in these gases at atmospheric pressure. Vanadium metal films have been oxidized.  At atmospheric pressure V2O5 is obtained, as expected.  Morphology issues and reduction behavior will be treated regarding oxidized vanadium films. Alternative ALD processes and annealing treatments will be discussed as well as electrical properties of the vanadium oxide films.       


Biography:

Koen Martens received the B.S. and M.S. degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 2001 and 2004. In january 2009 he obtained a PhD degree on the topic of germanium MOSFETs at the Katholieke Universiteit Leuven, Belgium and at IMEC.  In 2006 he was on an internship at Stanford University working on the electrical characterization of germanium MOSFETs.  Currently he is working as an FWO sponsored postdoctoral researcher on functional oxides with tailored properties for nanoelectronics with a focus on oxides showing a metal-to-insulator transition and RRAM.  



From shott at stanford.edu  Fri Mar 12 15:48:38 2010
From: shott at stanford.edu (John Shott)
Date: Fri, 12 Mar 2010 15:48:38 -0800
Subject: Mac OS Remote Coral user question
Message-ID: <4B9AD2D6.1010800@stanford.edu>

SNF Lab Members:

As Java 5 had reached its end of life in terms of support from 
Sun/Oracle, we are getting close to upgrading the Coral servers and 
Remote Coral clients to Java 6.

Preliminary indications are that this will be an improvement for 
virtually everyone and we already know that Remote Coral runs just fine 
on Windows, Linux, and Solaris platforms with Java 6.  The only question 
is related to Java 6 availability on the Mac OS X platform.

Apple does support JDK 6 (AKA Java 6) on 64-bit Intel architectures 
running at least Mac OS X 10.5 (Update 2 or later, I think) but does not 
on 32-bit machines.

> but Apple only released the Apple JDK 6 for Mac OS X 10.5/Leopard with 
> 64-bit CPUs.

I am trying to figure out how many of you are running a JDK6-compatible 
Max OS X platform and how many are not.

If you run Remote Coral on a Mac, can you let me know what version of OS 
X you are running, what version of Java is currently installed, and, if 
you know, whether it is a 32- or 64-bit machine (or maybe the model 
number would allow us to track that down).

Thanks,

John






From jwpchen at stanford.edu  Sat Mar 13 16:33:05 2010
From: jwpchen at stanford.edu (Peter Chen)
Date: Sat, 13 Mar 2010 16:33:05 -0800
Subject: Seminar-- J Provine from Halcyon Molecular, Tues, 3/16, 4:00 pm,Allen
 101X
Message-ID: <4B9C2EC1.6020306@stanford.edu>

Tuesday, March 16, 2009
4:00 pm
Allen 101X Auditorium

A Start-Up?s Efforts in DNA Sequencing via Electron Microscopy

J Provine, PhD
Halcyon Molecular / Stanford University

Abstract--
There has been significant progress in the past decade to improve the 
speed and accuracy of genomic sequencing.  This technological effort is 
reaching critical mass as many commercial and academic efforts have 
continued to increase the pace of innovation.  The goal for all those 
concerned is how to get a complete read of every single base in a genome 
for low cost (i.e., < $1000) and at high speed (i.e., less than 1 hour). 
  In this talk, I will introduce some of the major challenges and 
players in this effort, discuss our work at Halcyon Molecular and in 
particular the role of nanostructures and micromachining, and finally 
give a few short thoughts and lessons learned as a young academic trying 
to help a start-up.

Biography--
J Provine received BA (in Physics), BS (Electrical Engineering), and 
Masters (also Electrical Engineering) degrees from Rice University in 
1998 and 1999.  He then received his PhD in Electrical Engineering from 
Cornell University in 2005 for work on all optical wavelength routers. 
During his PhD he was able to work at the Berkeley Sensor & Actuator 
Center where he also was a post-doc for 2005 working on integration of 
plasmonic filters and MEMS actuators.  Since 2006, he has been a 
research associate at Stanford University working with the Center for 
Interfacial Engineering in MEMS.  In September 2009, he joined Halcyon 
Molecular part time to aid in their nanofabrication efforts.  Before 
November 2008, you could fit everything he knew about DNA sequencing on 
this page.



From kimsangb at stanford.edu  Mon Mar 15 07:15:36 2010
From: kimsangb at stanford.edu (SangBum Kim)
Date: Mon, 15 Mar 2010 07:15:36 -0700 (PDT)
Subject: PhD Oral Examination - SangBum Kim, Tuesday, March 16, 2010:
 10:00AM
In-Reply-To: <574909022.230471268662426930.JavaMail.root@zm01.stanford.edu>
Message-ID: <1757165014.230521268662536748.JavaMail.root@zm01.stanford.edu>













Special University PhD Oral Examination 



Scalability and R eliability S tudy of P hase- C hange M emory 



SangBum Kim 

Advisor: Professor H.-S. Philip Wong 



Department of Electrical Engineering, Stanford University 



Tuesday, March 16 , 20 10 , 10 :00 ? 11 :00 A M 

Paul Allen Building Auditorium ( CISX-101 ) 

(Refreshments served at 9 :45 A M) 



Abstract 

Phase-change memory (PCM) is one of the most mature emerging memory technologies. Superior s calability and reliability are important features that phase - change memory (PCM) technology should demonstrate to expand its usage in various memory applications. In the first part of the talk, scalability study of PCM will be presented. The first principle for PCM scaling rule is studied using analytical analysis. As a PCM cell scales down, the interfacial effect becomes more prominent in material properties and device characteristics due to larger surface area to volume ratio. Various structures have been fabricated to measure these interfacial effect s and study its impact on the operation of PCM. In search for a high current-density selection-device with low processing temperature which is needed for integration of PCM in a 3 -dimensional 4F 2 cross - point array , a Ge nanowire diode has been successfully integrated with a PCM memory cell. 



In the second part of the talk, reliability related study is presented. Interaction of thermal program-disturb mechanism and temperature dependence of PCM characteristics poses unique challenges for reliability of PCM devices. To study temperature dependence of PCM characteristics , the micro-thermal stage (MTS) with a fast on-chip heater has been integrated with a PCM cell. The MTS enables experimental study on temperature dependence of crystallization time, drift speed , and threshold switching in microsecond time scale . Thermal disturbance and its impact on PCM operation are measured with the MTS and the relevant model is developed. Based on measurement and modeling results, a new scheme is proposed to improve stability of PCM with a short time annealing pulse.
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From jprovine at stanford.edu  Tue Mar 16 14:27:31 2010
From: jprovine at stanford.edu (J Provine)
Date: Tue, 16 Mar 2010 14:27:31 -0700
Subject: reminder of NEMS seminar today 4pm in allen 101x
Message-ID: <8472aa211003161427t6e9d20d9ucd4c7cb62e20d334@mail.gmail.com>

hi everyone,
shameless self-promotion for the below talk.  i hope you can make:

A Start-up?s Efforts in DNA Sequencing via Electron Microscopy



J Provine, PhD

Stanford University / Halcyon Molecular



Abstract

There has been significant progress in the past decade to improve the speed
and accuracy of genomic sequencing.  This technological effort is reaching
critical mass as many commercial and academic efforts have continued to
increase the pace of innovation.  The goal for all those concerned is how to
get a complete read of every single base in a genome for low cost (ie <
$1000) and at high speed (ie less than 1 hour).  In this talk, I will
introduce some of the major challenges and players in this effort, discuss
our work at Halcyon Molecular and in particular the role of nanostructures
and micromachining, and finally give a few short thoughts and lessons
learned as a young academic trying to help a start-up.



Biography

J Provine received BA (in Physics), BS (Electrical Engineering), and Masters
(also Electrical Engineering) degrees from Rice University in 1998 and 1999.
He then received his PhD in Electrical Engineering from Cornell University
in 2005 for work on all optical wavelength routers.  During his PhD he was
able to work at the Berkeley Sensor and Actuator Center where he also was a
post-doc for 2005 working on integration of plasmonic filters and MEMS
actuators.  Since 2006, he has been a research associate at Stanford
University working with the Center for Interfacial Engineering in MEMS.  In
September 2009, he joined Halcyon Molecular part time to aid in their
nanofabrication efforts.  Before November 2008, you could fit everything he
knew about DNA sequencing on this page.
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From pruitt at stanford.edu  Wed Mar 17 11:39:55 2010
From: pruitt at stanford.edu (Beth Pruitt)
Date: Wed, 17 Mar 2010 11:39:55 -0700
Subject: Commercializing Technology through the Power of IP Licensing
Message-ID: <p06230974c7c6d2272084@[10.32.43.226]>

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>Linda
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From mdeal at stanford.edu  Fri Mar 19 07:36:14 2010
From: mdeal at stanford.edu (Michael Deal)
Date: Fri, 19 Mar 2010 07:36:14 -0700
Subject: FW: [CPN] NanoDays - Volunteers needed
Message-ID: <4BA38BDE.90007@stanford.edu>

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From mbaran at stanford.edu  Fri Mar 19 09:45:36 2010
From: mbaran at stanford.edu (Maureen Baran)
Date: Fri, 19 Mar 2010 09:45:36 -0700
Subject: Found Gloves on the Bench Outside the Cleanroom
Message-ID: <003a01cac783$99959240$ccc0b6c0$@edu>

Dear Labmembers,

 

A concerned Staff member found some "Saranac" gloves on the bench outside
the cleanroom.  If these gloves are yours, please come and claim them from
me.

 

I sit in cubicle # 41 on the first floor.

 

Maureen

 

Maureen Baran

Stanford Nanofabrication Facility

Lab Services Administrator

mbaran at stanford.edu

650-725-3664

 

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From choraliz8 at codhost.com  Fri Mar 19 11:29:56 2010
From: choraliz8 at codhost.com (Freda Osborne)
Date: Sat, 20 Mar 2010 02:29:56 +0800
Subject: Your friends will surely want those Swiss watches. These watches look like they cost thousands of dollars but you can get them for just a few hundreds.
Message-ID: <000d01cac792$2cf00300$6400a8c0@choraliz8>

Feel yourself a real business man with exclusive accessories. We combine the lowest prices and the highest quality for you.
&nbsp;
Waiting for you to enter
http://bestonebank.ru
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From jprovine at stanford.edu  Sun Mar 21 18:27:04 2010
From: jprovine at stanford.edu (J Provine)
Date: Sun, 21 Mar 2010 18:27:04 -0700
Subject: Ganesh Sundaram of Cambridge Nanotech speaking about atomic layer 
	deposition in SNF Wednesday March 24, 2010
Message-ID: <8472aa211003211827u2c92ed50he2b79e9a1c5a6152@mail.gmail.com>

hello snf labmembers,
Ganesh Sundaram the VP of Technology for Cambridge Nanotech will be visiting
Stanford on March 24, 2010.  as many of you know SNF and Cambridge Nanotech
have partnered on a getting a new plasma optional, dual chamber ALD system
(a Fiji F202) installed at SNF.  this system will be delivered to SNF in
early April 2010 and Ganesh has agreed to speak with labmember community at
11am-noon in allen 101x (formerly cis 101x) about the system and
capabilities that will very soon be available to our users.  In addition,
Ganesh will be available for questions concerning the system.  I hope many
of you can make this talk as it will be highly informative and will allow
you to get a jump start on utilizing a wonderful new addition in terms of
capability and capacity for our fab and its users.

if there are any questions i can answer in advance, please let me know.
j
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From koo1028 at stanford.edu  Sun Mar 21 22:19:01 2010
From: koo1028 at stanford.edu (Kyunghoae Koo)
Date: Sun, 21 Mar 2010 22:19:01 -0700
Subject: Furnace at 180 C
Message-ID: <003e01cac97f$2ee48c00$8cada400$@edu>

Dear Labmembers, 

 

Does anybody know if there is any furnace I can use, compatible with gold
and constant temperature at 180 C in an inert gas ambient? Fga2 seems to be
unstable at low temperature below 300C. I may not adjust the temperature of
singe oven. Is there any?

 

Thank you

 

Kyunghoae

 

 

===========================================================

Kyung-Hoae Koo

PhD candidate 

Stanford University 

EE department

 

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From mtang at stanford.edu  Mon Mar 22 06:07:50 2010
From: mtang at stanford.edu (Mary Tang)
Date: Mon, 22 Mar 2010 06:07:50 -0700
Subject: Process Clinic today:  Monday, 3/22, 2 pm
Message-ID: <4BA76BA6.3020905@stanford.edu>

Greetings labmembers --


Just a reminder that there is a Process Clinic today (Monday) from 2-4 
pm in the cubicle area outside of Maureen's office.  Staff and senior 
labmembers will be on hand to answer questions and brainstorm ideas to 
address process issues.  Bring your ideas, process questions, your 
process runsheets, SpecMat request, device layouts, and whatever else.


Your SNF staff


 <http://snf.stanford.edu>

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From shott at stanford.edu  Mon Mar 22 11:39:06 2010
From: shott at stanford.edu (John Shott)
Date: Mon, 22 Mar 2010 11:39:06 -0700
Subject: Mini flashlights at etch and deposition tools ....
Message-ID: <4BA7B94A.8080904@stanford.edu>

SNF Lab Members:

Thanks to recommendations from Jim Kruger, we've now distributed a 
number of small LED flashlights at a variety of etch and deposition 
tools where they will, hopefully, be useful for illuminating wafers 
through view ports.

Hopefully this will reduce the number of times when you cannot find a 
working flashlight when you need one or have to appropriate one from 
another tool.  Also, the clear case will make it easier to notice that a 
flashlight is still on so that we will, hopefully, go through fewer 
batteries.

Happy processing,

John



From jypeng at stanford.edu  Mon Mar 22 22:16:01 2010
From: jypeng at stanford.edu (Jammie Peng)
Date: Mon, 22 Mar 2010 22:16:01 -0700
Subject: Alumni Careers Seminar on 4/1 - Aditi Chandra presents her 
	perspective of life at a startup
Message-ID: <b3b0f6121003222216y6c59ea9av37669a43d924ff25@mail.gmail.com>

Stanford Materials Research Society
presents
Alumni Careers Seminar Series

Thursday, April 1, 2010
In McCullough Bldg. Rm. 115
Starts at 5:00pm

*Are there academics outside of academia?
*
*An MSE alumni's perspective of life at a startup*
 [image: Aditi.jpg]
Aditi Chandra, Ph.D.
Section Manager of Print Integration
Kovio Inc. (a printed electronics startup)
 *RSVP below by 3/30 for complimentary dinner and a chance to win door
prizes!*
Aditi Chandra currently works at Kovio, Inc. a printed electronics company.
She is responsible for the technology development and process integration of
silicon-based printed TFTs, specifically with the integration of printed
dopants and gate.  Her past work has also included printed contacts.  She
received her Ph.D in Materials Science and Engineering at Stanford in 2006
for work in metal induced silicon crystallization and nanoparticle memory
devices under the supervision of Prof. Bruce Clemens. She holds a bachelors
degree in Physics from Brown University.
*

**

**

 If you have trouble viewing or submitting this form, you can fill it out
online:
http://spreadsheets.google.com/viewform?formkey=dHcyYnY1N255dTk3ZFJRMndHMDVNWVE6MA

*
*
*
 Name *

 Email *

 Degree Program *

   - BS
   - MS
   - PhD
   - Post-Doc
   - Other:


 Year in Program *

   - 1st year
   - 2nd year
   - 3rd year
   - 4th year
   - 5th year or more


 National MRS Member *

   - Yes
   - No


 Stanford MRS Mailing List *

   - I am part of the mailing list.
   - Please add me to the mailing list.
   - I do not want to join the mailing list.


 Question for the speaker or topic of discussion

   Powered by Google Docs <http://docs.google.com> Report
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*Next Seminar:  Thursday, April 22, 2010*
*Hope Ishii - Lawrence Livermore National Laboratory*
*
*
*Find out more about Stanford MRS at mrs.stanford.edu*

*Jammie Peng*
Alumni Relations Director and E-Commerce Officer
*Stanford Materials Research Society*
jypeng at stanford.edu
mrs.stanford.edu
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From jprovine at stanford.edu  Tue Mar 23 11:33:59 2010
From: jprovine at stanford.edu (J Provine)
Date: Tue, 23 Mar 2010 11:33:59 -0700
Subject: Ganesh Sundaram of Cambridge Nanotech speaking about atomic layer 
	deposition in SNF Wednesday March 24, 2010
In-Reply-To: <8472aa211003211827u2c92ed50he2b79e9a1c5a6152@mail.gmail.com>
References: <8472aa211003211827u2c92ed50he2b79e9a1c5a6152@mail.gmail.com>
Message-ID: <8472aa211003231133q386cd588w9a5669481efc5897@mail.gmail.com>

dear snf labmembers,
a reminder that Ganesh Sundaram the VP of Technology for Cambridge Nanotech
will be visiting Stanford on March 24, 2010.  as many of you know SNF and
Cambridge Nanotech have partnered on a getting a new plasma optional, dual
chamber ALD system (a Fiji F202) installed at SNF.  this system will be
delivered to SNF in early April 2010 and Ganesh has agreed to speak with
labmember community at 11am-noon in allen 101x (formerly cis 101x) about the
system and capabilities that will very soon be available to our users.  In
addition, Ganesh will be available for questions concerning the system.  I
hope many of you can make this talk as it will be highly informative and
will allow you to get a jump start on utilizing a wonderful new addition in
terms of capability and capacity for our fab and its users.

if there are any questions i can answer in advance, please let me know.
j
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From shresbm at gmail.com  Tue Mar 23 18:50:23 2010
From: shresbm at gmail.com (Shrestha Basu Mallick)
Date: Tue, 23 Mar 2010 18:50:23 -0700
Subject: please be careful with chemicals
Message-ID: <353abe271003231850l3a39931bp31c6f8c605f16ffe@mail.gmail.com>

when placing them in passthrough.
Someone had put the 6:1 BOE where the hydrogen peroxide should have been.
Its a risky mistake especially because both have white caps

-- 
Shrestha
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From jacesan at yahoo.com  Tue Mar 23 19:43:24 2010
From: jacesan at yahoo.com (Roy Martin)
Date: Tue, 23 Mar 2010 19:43:24 -0700 (PDT)
Subject: please be careful with chemicals
In-Reply-To: <353abe271003231850l3a39931bp31c6f8c605f16ffe@mail.gmail.com>
Message-ID: <895276.91970.qm@web52601.mail.re2.yahoo.com>

This cannot be stressed enough. I encountered trace amounts, but enough to get an HF burn while working @ SJSU's IC lab. Be careful with that stuff.

Roy

--- On Tue, 3/23/10, Shrestha Basu Mallick <shresbm at gmail.com> wrote:

From: Shrestha Basu Mallick <shresbm at gmail.com>
Subject: please be careful with chemicals
To: labmembers at snf.stanford.edu
Date: Tuesday, March 23, 2010, 6:50 PM

when placing them in passthrough.
Someone had put the 6:1 BOE where the hydrogen peroxide should have been. Its a risky mistake especially because both have white caps

-- 
Shrestha




      
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From mtang at stanford.edu  Thu Mar 25 17:01:06 2010
From: mtang at stanford.edu (Mary Tang)
Date: Thu, 25 Mar 2010 17:01:06 -0700
Subject: Dedicated Wafer Cassette use in SNF
Message-ID: <4BABF942.8040105@stanford.edu>

Dear Labmembers:


It has been brought to our attention that some people need to be 
reminded of the policies on dedicated cassettes:

1.  No litho cassettes may be taken into the white area of the lab.  
This includes the metal boats as well as the teflon cassettes with brown 
buttons.

2.  No Furnace preclean or etch cassettes from clean or semiclean 
stations may be taken into the Litho area of the lab.   This includes 
metal cassettes.

3.  To move wafers between the white and litho areas of the lab, use 
your own transfer cassettes.

4.  If you remove a dedicated cassette from a station (for example, from 
wbdiff to a furnace for loading) return it as soon as possible.

These policies are covered in wet bench training at all these stations.  
If you need a refresher, refer to the training materials in the website 
(procedures on the wiki, video at 
http://spf.stanford.edu/training/wbdiff.wmv.)  If everyone is diligent 
about proper cassette use, the cleanliness in the lab can be better 
maintained and there should be sufficient cassettes for everyone's use.  
If you see someone improperly using dedicated cassettes, you have every 
right to correct that person.  You may also report to staff (please 
provide specific details.)


Thanks for your attention --


Your SNF Staff

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu

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From mtang at stanford.edu  Thu Mar 25 17:33:54 2010
From: mtang at stanford.edu (Mary Tang)
Date: Thu, 25 Mar 2010 17:33:54 -0700
Subject: SNF Personal Chemicals in Flammables Storage
Message-ID: <4BAC00F2.5020306@stanford.edu>

Greetings labmembers:


Because of space and organizational concerns, storage class L personal 
chemicals are being moved from the Flammables cabinets in epi2 area out 
to the service area where there is a nice, new flammables cabinet.   The 
plan is to keep all personal-use chemicals in this new cabinet.  The two 
Flammables cabinets in the epi2 area will be dedicated to SNF-supplied 
chemicals.  This means we will be able to stock more high-use chemicals 
-- and hopefully avoid running out of Remover PG over a busy weekend.

If you have personal-use chemicals in the Flammables cabinets, please 
take a few minutes to make sure they are dated.  If they are no longer 
in use, please dispose of them.  If new yellow labels are needed, 
contact Mahnaz or other staff to get new ones.  Outdated and unlabeled 
chemicals are subject to removal from the lab. 

Any questions, please contact the....


Litho team

3/25/10



From rfasch at stanford.edu  Sun Mar 28 04:15:52 2010
From: rfasch at stanford.edu (Rainer Fasching)
Date: Sun, 28 Mar 2010 04:15:52 -0700
Subject: FW: ME260 - Fuel cell science and technology 
Message-ID: <000601cace68$07d91bb0$178b5310$@edu>

FYI

 

From: Rainer Fasching [mailto:rfasch at stanford.edu] 
Sent: Saturday, March 27, 2010 2:23 PM
To: Mary Tang
Subject: FW: ME260 - Fuel cell science and technology 

 

 

Dear Mary:

 

I'm teaching ME260 course this spring quarter. The announcement was placed
delayed on the bulletin and I want to make sure that students  are aware of
this course opportunity. I would appreciate it very much, if you could
forward this email to SNF students/colleagues.

 

Thanks,

Rainer Fasching

 

ME260

Fuel Cell Science and Technology

Spring 2010

 

Tuesday, Thursday 4:15pm-5:30pm

Lane History Corner (Bldg 200), Room 305

 

Audience: Targeted at advanced undergraduate or beginning level graduate
students in the engineering or physical sciences. We anticipate diverse
student backgrounds and furthermore recognize that the electrochemical
concepts will be new to most students. Therefore, the material will be
presented assuming no prior background in electrochemistry. Much of the
material covered will be theoretical and fundamental in nature.

ClassPicture

Description: Fuel cells provide one of the most efficient means for
converting the chemical energy stored in a fuel to electrical energy.  Fuel
cells offer improved energy efficiency and reduced pollution compared to
heat engines.  While composed of no (or very few) moving parts, a complete
fuel cell system amounts to a small chemical plant for the production of
power.  This course introduces students to the fundamental aspects of fuel
cell systems, with emphasis placed on proton exchange membrane (PEM) and
solid oxide fuel cells (SOFC).  Students will learn the basic principles of
electrochemical energy conversion while being exposed to relevant topics in
materials science, thermodynamics, and fluid mechanics.

 

 

Outline: 

Fuel Cell Principles

What is a Fuel Cell?

Fuel Cell Thermodynamics

Fuel Cell Kinetics

Fuel Cell Charge Transport

Diffusion and Mass Transport

Fuel cell Modeling

Fuel cell Characterization            

Fuel Cell Technology

                                Fuel cell Types

                                Fuel cell Stacking

                                Fuel cell Systems

                                Fuel cell Applications

 

Objectives: By the end of the course, students will have gained the skills
and knowledge to demonstrate the following objectives:

.         Fuel Cell Characteristics. Contrast the advantages and
disadvantages of fuel cells to other energy conversion technologies (e.g.
heat engines). Discuss the advantages and disadvantages between the various
fuel cell types (SOFC, MCFC, PAFC, AFC, PEMFC).

.         Fuel Cell Thermodynamics. Perform thermodynamic calculations to
quantitatively predict ideal fuel cell voltages as a function of gas
concentrations, pressure, and temperature. Calculate thermodynamic
efficiencies. Perform heat and mass balances on fuel cell systems. Describe
the basic mechanisms of fuel cell reactions, electron transfer, and ionic
transport at the molecular scale.

.         Fuel Cell Kinetics. Derive equations for activation, IR, and
concentration losses in fuel cell systems. Assemble a complete (simple)
analytical model for a fuel cell system and use it to predict fuel cell
performance over a range of operating conditions (e.g. at various
temperature, pressures, feed rates, etc.) Identify the most significant
kinetic constraints that limit current fuel cell performance and suggest
research directions to improve performance.

.         Fuel Cell Research. Identify the major materials issues remaining
in fuel cell design. Describe the most important characterization techniques
used to test fuel cell performance and identify bottlenecks.  

.         Fuel Cell Systems. Describe the major strategies for fuel cell
stacking. Compare planar vs. vertical fuel cell interconnection. Discuss the
major fuel cell system applications (portable, transportation, stationary
power) and be able to argue which fuel cell types are most suited for each
application. Discuss and describe the ancillary equipment necessary for a
complete fuel cell system (Compressors, humidification, reformers, heat
management, power conditioning). Perform a basic economic analysis to
predict the cost reductions necessary such that fuel cell systems can be
economically competitive with current energy conversion technologies.

 

 

 

Rainer Fasching, PhD

Cons. Associate Professor

Department of Mechanical Engineering

Stanford University

 

Mail: 440 Escondido Mall, Bldg. 530, Rm. 220, Stanford, CA 94305-3030

Email: rfasch at stanford.edu

Phone: 415-505-3385

Fax: 650-723-5034

 

 

 

 

 

 

 

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From koo1028 at stanford.edu  Mon Mar 29 10:27:12 2010
From: koo1028 at stanford.edu (Kyunghoae Koo)
Date: Mon, 29 Mar 2010 10:27:12 -0700
Subject: Cr etchant: etching rate?
Message-ID: <00a001cacf65$11abaab0$35030010$@edu>

 

Dear Labmembers, 

 

What is the etching rate of Cr etchant in snf? I need to etch 2nm buffer Cr
layer. Lateral etching is not a big issue. How much time will be enough for
that?

Thanks 

 

Kyunghoae

 

 

===========================================================

Kyung-Hoae Koo

PhD candidate 

Stanford University 

EE department

 

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From dalyx at stanford.edu  Mon Mar 29 11:15:21 2010
From: dalyx at stanford.edu (Dany-Sebastien Ly-Gagnon)
Date: Mon, 29 Mar 2010 11:15:21 -0700
Subject: Cr etchant: etching rate?
In-Reply-To: <00a001cacf65$11abaab0$35030010$@edu>
References: <00a001cacf65$11abaab0$35030010$@edu>
Message-ID: <v2y7f014b6b1003291115w182c9251qb921b2163f9a4e12@mail.gmail.com>

For the Cr etchant that we have in lab (Cr-14), the etch rate should be
~93nm/min from literature. Note that our Cr etchant is expired (since April
2009), so literature etch rates may not be reliable.

>From experience, the etch seems to start only after ~30sec in solution, and
the etch rate is quite fast. In about 1 min, I could etch 10nm Cr. It
doesn't seem like the etch rate is linear in time and varies greatly
(perhaps because it is expired), so it may undercut resist patterns
significantly.

Best,

Dany


On Mon, Mar 29, 2010 at 10:27 AM, Kyunghoae Koo <koo1028 at stanford.edu>wrote:

>
>
> Dear Labmembers,
>
>
>
> What is the etching rate of Cr etchant in snf? I need to etch 2nm buffer Cr
> layer. Lateral etching is not a big issue. How much time will be enough for
> that?
>
> Thanks
>
>
>
> Kyunghoae
>
>
>
>
>
> ===========================================================
>
> Kyung-Hoae Koo
>
> PhD candidate
>
> Stanford University
>
> EE department
>
>
>
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From shott at stanford.edu  Mon Mar 29 12:37:26 2010
From: shott at stanford.edu (John Shott)
Date: Mon, 29 Mar 2010 12:37:26 -0700
Subject: Getting ready for the next Coral release ....
Message-ID: <4BB10176.4080300@stanford.edu>

SNF Lab Members:

Within the next couple of days, we will be releasing a new version of 
Coral that will require use of Java Version 6 instead of Java Version 
5.  Why?  Java 5 has reached its End of Service Life and is less 
supportable than the current version (Java Version 6).  More 
importantly, new Coral capabilities will likely use features that are 
available only in newer versions of Java.  For example, people have 
suggested that we be able to open xReporter from within Coral and have 
also suggested that links to online documentation be available from 
within Coral.  Both of those features will be available in the new 
release, but require a feature that is only available in Java 6 ... the 
ability to open the default browser from within a Java application.

How can you prepare?  If you already have Java 6 on your machine, you 
are ready to go and do not have to do anything.  If you have Java 5, 
however, you will want to download and install the Java 6 runtime 
environment.  How can you tell?  If you are on a Windows machine, you 
can open the "Run ..." command line window from the Start Menu and type 
in the command:

javaws -viewer

This will open the Java Web Start cache viewer which will open two 
windows: one named Java Cache Viewer and the other named Java Control 
Panel.  When those open, close the Java Cache Viewer and then click the 
Java tab on the Java Control Panel.  On that panel, there should be a 
button named "View" that will show you a list of one or more versions of 
Java currently installed on your machine.  You may have several, but you 
are looking for one that is listed as Platform = 1.6 (which is Java 6).  
If you only have Platform = 1.5 entries, then you only have Java 5 and 
will need to download and install a Java 6 runtime environment.

If you need to do that go to:

http://java.sun.com/javase/downloads/index.jsp

On that page there are a number of red buttons that say "Download" ... 
but there will be only one button that says "Download JRE"
If you click that link, you will be able to download and install the 
Java Runtime Enviroment onto your machine.  That version will run the 
existing version of Remote Coral but will also be what you need when we 
release the new version of Java later this week.

Note: if you are on a Linux, Solaris, or Mac OS X platform, you can 
easily tell what version of Java you are running by opening a command 
line window and issuing the command: 'java -version'.

Let me know if you have any questions,

John



From jypeng at stanford.edu  Mon Mar 29 16:59:00 2010
From: jypeng at stanford.edu (Jammie Peng)
Date: Mon, 29 Mar 2010 16:59:00 -0700
Subject: RSVP NOW: Are there academics outside of academia? An MSE alumni's 
	perspective of life at a startup
Message-ID: <b3b0f6121003291659ycee536ch470ddf621ef1fff7@mail.gmail.com>

Stanford Materials Research Society
presents
Alumni Careers Seminar Series

Thursday, April 1, 2010
In McCullough Bldg. Rm. 115
Starts at 5:00pm

*Are there academics outside of academia?
*
*An MSE alumni's perspective of life at a startup*
 [image: Aditi.jpg]
Aditi Chandra, Ph.D.

Section Manager of Print Integration
Kovio Inc. (a printed electronics startup)
 *RSVP below by 3/30 for complimentary dinner and a chance to win door
prizes!*
Aditi Chandra currently works at Kovio, Inc. a printed electronics company.
She is responsible for the technology development and process integration of
silicon-based printed TFTs, specifically with the integration of printed
dopants and gate.  Her past work has also included printed contacts.  She
received her Ph.D in Materials Science and Engineering at Stanford in 2006
for work in metal induced silicon crystallization and nanoparticle memory
devices under the supervision of Prof. Bruce Clemens. She holds a bachelors
degree in Physics from Brown University.
*

**

**

 If you have trouble viewing or submitting this form, you can fill it out
online:
http://spreadsheets.google.com/viewform?formkey=dHcyYnY1N255dTk3ZFJRMndHMDVNWVE6MA

*
*
*
 Name *

 Email *

 Degree Program *

   - BS
   - MS
   - PhD
   - Post-Doc
   - Other:


 Year in Program *

   - 1st year
   - 2nd year
   - 3rd year
   - 4th year
   - 5th year or more


 National MRS Member *

   - Yes
   - No


 Stanford MRS Mailing List *

   - I am part of the mailing list.
   - Please add me to the mailing list.
   - I do not want to join the mailing list.


 Question for the speaker or topic of discussion

   Powered by Google Docs <http://docs.google.com> Report
Abuse<http://spreadsheets.google.com/reportabuse?formkey=dHcyYnY1N255dTk3ZFJRMndHMDVNWVE6MA&source=http%253A%252F%252Fspreadsheets.google.com%252Fviewform%253Fformkey%253DdHcyYnY1N255dTk3ZFJRMndHMDVNWVE6MA>-
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Terms<http://www.google.com/google-d-s/terms.html>


*Next Seminar:  Thursday, April 22, 2010*
*Hope Ishii - Lawrence Livermore National Laboratory*
*
*
*Find out more about Stanford MRS at mrs.stanford.edu*

*Jammie Peng*
Alumni Relations Director and E-Commerce Officer
*Stanford Materials Research Society*
 jypeng at stanford.edu
mrs.stanford.edu
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From tryon16 at stanford.edu  Tue Mar 30 03:11:13 2010
From: tryon16 at stanford.edu (Larkhoon Leem)
Date: Tue, 30 Mar 2010 03:11:13 -0700
Subject: e-Workshop: All-Spin Logic
In-Reply-To: <b2a6a2fa1003300309k535cf59eg95fcd2413b066c5f@mail.gmail.com>
References: <b2a6a2fa1003300309k535cf59eg95fcd2413b066c5f@mail.gmail.com>
Message-ID: <b2a6a2fa1003300311h17eba864kc36b3d4fb1d0afa@mail.gmail.com>

You are invited to participate:

All-Spin Logic

to be presented by Supriyo Datta, Behtash Behin-Aein and Kaushik Roy from the
Purdue University

on Tuesday, March 30th at 1pm. Stanford site for this tele-seminar
will be set up at Allen (CISX) 316X.


Abstract: The possible use of spin rather than charge as a state
variable in devices for processing and storing information has been
widely discussed, because it could allow low-power operation and might
also have applications in quantum computing. However, spin-based
experiments and proposals for logic applications typically use spin
only as an internal variable, the terminal quantities for each
individual logic gate still being charge-based. This requires repeated
spin-to-charge conversion, using extra hardware that offsets any
possible advantage.

We propose a spintronic device that uses spin at every stage of its
operation: information manipulation, transport, storage, input and
output are all accomplished with magnets and spin-coherent channels.
Contrary to the typical spin/magnet based logic schemes, the all-spin
scheme neither relies on ordinary magnetic fields (generated by
current carrying wires) nor does it rely on electrical read-out of
magnetic states. Binary data are represented by the bi-stable states
of nanomagnets (i.e. magnetic polarization) which can be non-volatile.
Application of a voltage signal to a magnetic contact (input data bit)
creates a spin-current in a channel which can be conveniently guided
and routed to another magnetic contact (output data bit) where it
determines its final state based on spin-torque phenomenon.

The all-spin device could potentially find use for low-power digital
logic since it should satisfy the five essential requirements for
logic applications namely nonlinearity, gain, concatenability,
feedback prevention and a complete set of Boolean operations.
Satisfaction of these essential characteristics paves the way for the
design of large scale digital circuits. Cascading and clocking of
logic gates will be discussed along with the
device/circuit/architecture co-optimization of all-spin logic (ASL).

While the focus of the talk will be on digital logic, it is
interesting to note that the all-spin scheme could provide a basis for
unconventional approaches. For example the spin accumulation in a
channel underneath a magnetic contact could provide a 'weighted
average' of different inputs that makes it switch ("fire") when it
exceeds a threshold like neural networks. Alternatively the magnetic
contacts on top of the channel could possibly serve as Input-Output
interface for spin-based quantum computing.



Biographies of Presenters:

Supriyo Datta received his B.Tech. from the IIT, Kharagpur in 1975,
his Ph.D from the University of Illinois, Urbana-Champaign in 1979 and
joined Purdue University in 1981. The approach pioneered by his group
for the description of quantum transport far from equilibrium has been
widely adopted in the field of nanoelectronics and he shared the IEEE
Cledo Brunetti award in 2002 with his colleague Mark Lundstrom. His
work has also influenced course and curriculum development in
nanoelectronics for which he received the IEEE Leon Kirchmayer award
for Graduate Teaching in 2008. URL:
http://cobweb.ecn.purdue.edu/~datta/

Behtash Behin-Aein received his B.Sc. in electrical engineering from
Purdue University, West Lafayette, IN in 2004. He is currently a
research assistant in Supriyo Datta's research group working towards
his Ph.D at Purdue University. His research interests include spin
devices, spin dynamics in confined magnetic structures, spin transport
and spin-torque phenomenon.

Kaushik Roy received his B.Tech. degree in electronics and electrical
communications engineering from IIT, Kharagpur, India, and Ph.D in
electrical and computer engineering from the University of Illinois at
Urbana- Champaign in 1990. His research interests include VLSI
design/CAD for nano-scale Silicon and non-Silicon technologies,
low-power electronics for portable computing and wireless
communications, VLSI testing and verification, and reconfigurable
computing. Dr. Roy has received the National Science Foundation Career
Development Award in 1995, IBM faculty partnership award, ATT/Lucent
Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors
Award and Purdue College of Engineering Research Excellence Award.
URL: https://engineering.purdue.edu/NRL


From mtang at stanford.edu  Tue Mar 30 10:42:22 2010
From: mtang at stanford.edu (Mary Tang)
Date: Tue, 30 Mar 2010 10:42:22 -0700
Subject: Cr etchant: etching rate?
In-Reply-To: <v2y7f014b6b1003291115w182c9251qb921b2163f9a4e12@mail.gmail.com>
References: <00a001cacf65$11abaab0$35030010$@edu> <v2y7f014b6b1003291115w182c9251qb921b2163f9a4e12@mail.gmail.com>
Message-ID: <4BB237FE.2060705@stanford.edu>

Hi Dany, Kyunghoae, and others --

Thanks for letting us know about the expired Cr-14 etchant -- it should 
not have been in there and has now been replaced with current stock.  
The shelf-life is pretty short (3 months) so we need to keep an eye on it.

As for VLSI etchant etch rates, the Berkeley Microlab lab manual has an 
excellent reference that is linked on the wiki:
http://microlab.berkeley.edu/labmanual/chap1/JMEMSEtchRates2(2003).pdf

Please remember that the etch rates depend on film quality and that can 
vary depending on the machine and conditions of deposition.  So the etch 
rates in this document should not be taken at full face value, but as a 
good starting point -- you should always verify etch rates against the 
actual film you are using in a critical etch.  And so, yes, there is a 
delay in Cr etching because Cr is highly reactive and forms a native 
oxide on the surface which etches more slowly than bulk Cr.


Uli & Mary



Dany-Sebastien Ly-Gagnon wrote:
> For the Cr etchant that we have in lab (Cr-14), the etch rate should 
> be ~93nm/min from literature. Note that our Cr etchant is expired 
> (since April 2009), so literature etch rates may not be reliable.
>
> From experience, the etch seems to start only after ~30sec in 
> solution, and the etch rate is quite fast. In about 1 min, I could 
> etch 10nm Cr. It doesn't seem like the etch rate is linear in time and 
> varies greatly (perhaps because it is expired), so it may undercut 
> resist patterns significantly.
>
> Best,
>
> Dany
>
>
> On Mon, Mar 29, 2010 at 10:27 AM, Kyunghoae Koo <koo1028 at stanford.edu 
> <mailto:koo1028 at stanford.edu>> wrote:
>
>      
>
>     Dear Labmembers,
>
>      
>
>     What is the etching rate of Cr etchant in snf? I need to etch 2nm
>     buffer Cr layer. Lateral etching is not a big issue. How much time
>     will be enough for that?
>
>     Thanks
>
>      
>
>     Kyunghoae
>
>      
>
>      
>
>     ===========================================================
>
>     Kyung-Hoae Koo
>
>     PhD candidate
>
>     Stanford University
>
>     EE department
>
>      
>
>

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From ahazeghi at stanford.edu  Wed Mar 31 16:27:26 2010
From: ahazeghi at stanford.edu (Arash Hazeghi)
Date: Wed, 31 Mar 2010 16:27:26 -0700
Subject: Au etch rate
Message-ID: <005701cad129$b930fc20$2b92f460$@edu>

Hi,

Does anyone know the approximate etch rate for thick gold film using the
standard Au etch solution?

 

Thanks,

Arash

 

 

 

----------------------------------------------------------------------------
------

Arash Hazeghi

 

PhD Candidate

Stanford Center for Integrated Systems

CIS-X 300, 420 Via Palou Mall, 

Stanford, CA 94305

 

phone: +1-650-725-0418

web: http://www.stanford.edu/~ahazeghi

 

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