PhD Oral Examination - Li-Wen Chang, Wednesday, March 17th, 2010, 1:00pm

Li-Wen Chang lwchang at
Wed Mar 10 23:20:10 PST 2010

Device / Circuit Fabrication Using Diblock Copolymer Lithography

PhD Oral Examination
Speaker: Li-Wen Chang, Department of Materials Science and
Engineering, Stanford University
PhD Advisor: Prof. H.-S. Philip Wong

Time: 1pm (refreshments served at 12:45pm)
Date: Wednesday, March 17, 2010
Location: Allen 101X Auditorium

Silicon technology scaling has been continued for decades in order to
make smaller and faster devices. The scaling roadmap is essentially
enabled by the evolution of lithography technology. As conventional
lithography is reaching its resolution limit, there is still no
apparent solution for printing feature sizes beyond the 22 nm node. In
view of the escalating cost for improving the lithography tool,
industry is now using double patterning technique to enhance the
feature density without the need to change the infrastructure. As one
of the candidates for the Next Generation Lithography, block copolymer
lithography,  has showcased its capability of delivering
self-assembled array of nanoscale features ranging from 30nm to 10nm,
through a self-assembly process.

Although ITRS projects block copolymer lithography to be used on 16 nm
technology node, no block copolymer lithography integration with
conventional CMOS process has been demonstrated. In this work, we
fabricated the top-gated FETs / inverters with 20 nm contact holes
patterned using block copolymer lithography. It is employed as a
double patterning technique with the second layer photoresist replaced
by block copolymers. The synergy of the conventional top-down
lithography with bottom-up self-assembly not only relaxes the pattern
dimension of the first layer generated by conventional lithography,
but also delivers final feature size that is solely determined by the
block copolymer systems. Alignment of the self-assembled contact holes
to the MOSFET source and drain is achieved with a unique guiding
layer. The self-assembly process is integrated with an existing CMOS
process flow using conventional tools on a full wafer level. The
design rule derivation for future device / circuit design integrating
bock copolymer lithography is also addressed.

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