Reminder: Arash Hazeghi's PhD Orals

Arash Hazeghi ahazeghi at
Fri Nov 5 06:38:38 PDT 2010



Speaker: Arash Hazeghi

Advisor:   Prof. H.-S. Philip Wong

Date:   Friday, Nov. 5th

Time:   3:00PM (Refreshments served at 2:45PM)

Location: CIS-X Auditorium






For more than four decades, Moore's law has been the driving force of the
semiconductor industry. Thanks to the continuous scaling of Silicon CMOS,
rapid development of faster, smaller and cheaper electronics has been
realized extending the boundaries of science and technology. However, as
scaling continues into the new decade and beyond 20nm, short-channel
effects, parasitics, power dissipation, lithography limitations and process
variation limit the performance of Silicon CMOS. In order to overcome these
challenges new types of semiconductor material and technology are needed.


With a diameter of no more than a few nanometers, Carbon Nanotubes (CNT)
have unique electronic and structural properties that makes them ideal
candidates for high performance digital logic applications. Recent
innovations in high-density horizontally-aligned CNT synthesis and transfer
process have enabled us to fabricate large-scale logic circuits with robust
functionality, solely based on CNT Field Effect Transistors (CNFETs).


In this work we first investigate one of the major performance-limiting
factors of the aligned CNT-based devices, the electrical contact resistance
between CNT and metal contact, and propose a solution to reduce this
resistance. We also provide a physics-based model for simulation, analysis
and design of CNFET devices operating in ballistic as well as low-field
semi-classical transport regimes. Finally, since measurement of carrier
density is an integral part of understanding these devices, a new Integrated
Capacitance Bridge (ICB) device is also provided for high-resolution
wide-temperature range measurements of quantum capacitance in




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