EE PhD Oral Examination - Roozbeh Parsa, Friday, October 29, 2010; 8:30 am

Roozbeh Parsa rparsa at
Wed Oct 27 22:00:44 PDT 2010

Stanford University Oral Defense - Department of Electrical Engineering 

Speaker: Roozbeh Parsa 
Advisor: Prof. Roger T. Howe 
Date: Friday, October 29th 
Time: 8:30am (refreshments at 8:15am) 
Location: Paul Allen Building, Cypress Auditorium (formerly CISX-101) 



CMOS scaling has been very successful in generating small, fast, low cost electronics. However, in 
advanced CMOS nodes, the total power consumption is dominated by the static power dissipation, 
which is caused greatly by gate leakage, short channel effects, and finite subthreshold slope. Further scaling of CMOS only exacerbates these problems. 

Nanoelectromechanical (NEM) relays are promising devices for assisting CMOS systems by reducing the static power dissipation due to their zero leakage current, infinite subthreshold slope, and scalable actuation voltage. Electrostatically-actuated NEM relays are devices where the operation is based on the deformation of a flexible beam under the influence of electrostatic force in order to create a conducting path between two electrodes. 

This work studies the fabrication process development of sidewall-coated laterally-actuated NEM relays. The developed process enables decoupling of the mechanical and electrical properties of the relay, allowing independent optimization of each property and paving the path for creating a back-end-of-line (BEOL) compatible process. Furthermore, a major failure mechanism of NEM relays is beam-to-gate shorting after actuation. To ameliorate this problem, new designs with improved mechanical properties were simulated and tested. These designs utilize a stiff electrode and a compliant beam to eliminate undesired beam deformation near the gate electrode. These results in addition to variation studies, stress outcomes, and basic logic functionality of the NEM relays will be presented. 

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