From mtang at stanford.edu Wed Sep 1 08:40:22 2010 From: mtang at stanford.edu (Mary Tang) Date: Wed, 01 Sep 2010 08:40:22 -0700 Subject: [Fwd: Update! Via Palou Road Construction Start Monday,August 30th] Message-ID: <4C7E73E6.4040809@stanford.edu> All, The north side of Via Pueblo will be widened towards the Paul Allen building, the south side of the road will remain open to traffic with flaggers on each end. This section will be closed to pedestrians and bikes during construction with detours to Via Palou and through the SEQ. Construction will begin next week. Working hours Mon - Fri. 6am - 2:30pm, with occasional activity on the weekends. ADA access to the Paul Allen building will be on the north side, at the Serra Mall (Allen Annex entrance). Emergency exits will be maintained. Lastly, sensitive lab equipment may be impacted by the vibrations during the demolition phase. Please contact David Kirk, project representative dgkirk at stanford.edu or 650-384-5758 with questions or concerns. Thanks for your attention! -- Kenny Green Facilities Services Manager Electrical Engineering 650.724.3310 Office 650.804.2032 Cell -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From shott at stanford.edu Thu Sep 2 13:01:45 2010 From: shott at stanford.edu (John Shott) Date: Thu, 02 Sep 2010 13:01:45 -0700 Subject: Reiteration of SNF equipment enable and capping policies .... Message-ID: <4C8002A9.7070102@stanford.edu> SNF Lab Members: Over the course of the past few days, it has come to my attention that a number of lab members are confused as to the SNF policy related to enabling of equipment and application of the cap. As yesterday was the start of a new fiscal year, it is a good time to review these policies so that there is no uncertainty. According to the SNF Policy Manual (https://snf.stanford.edu/SNF/safety/safety-orientation/ManualPartI.pdf) the policy on enabling equipment and caps states: /Once you have been qualified to use a piece of equipment, *you must enable the equipment in order to use it*. Most equipment in the lab is interlocked to Coral so that it will not function unless it is enabled by a qualified user. You must not enable equipment for an unqualified person to use; doing so is considered a violation of the Stanford Fundamental Standard. You should either disable a tool when you are finished with it; or if someone else wants to use the tool immediately after you, with your permission, he/she may enable over you./ /The "Cap" is the maximum equipment use charge that can be accrued by a single lab member account in a single calendar month (starting form the 1st of each month.) The purpose of the cap is to allow researchers to work without having to keep a close eye on the clock. ... *Multiple lab members working on the same project are each subject to his/her own cap. One lab member working on multiple projects is subject to a cap for each project. In short, the "Cap Rule" is: one cap per person, per project, per calendar month.*/ This has been the policy in SNF at least since the days when Dean Plummer was the Director of this facility and is the policy today. Another way to state this policy is that if you are operating a piece of equipment, it must be enabled in your name. If you are operating equipment and it is not enabled (whether it is interlocked or not) you are in violation of our policy. If you are operating equipment and it is enabled by someone else, you are in violation of our policy ... and the person who has the equipment enabled may be in violation of our policy for allowing you to use equipment that is enabled by them. While not all lab members are students, it is useful to ALL lab members to know that Stanford students are guided by a policy known as the Fundamental Standard (http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/fundamental.htm). SNF staff certainly believe that failure to enable equipment under the proper account by the proper user is a violation of the Fundamental Standard. Effective immediately, If you are found using equipment that is not enabled or is enabled by someone else or if you have allowed someone else to use equipment that is enabled by you, we will impose the following sanctions: 1. First violation: one week expulsion from the lab and 10 hours of community service. Appeals will be handled by the SNF Student Advisory Committee. 2. Second violation: one month expulsion from the lab and 20 hours of community service. Appeals will be handled by the SNF Student Advisory Committee and the SNF Faculty Director. 3. Third violation: three month expulsion from the lab and 40 hours of community service. Appeals will be handled by the SNF Faculty Advisory Committee. These penalties ARE new, but will be imposed immediately. There is no grace period and being unaware of these sanctions will not be considered as an excuse given the long standing nature of our policies related to enabling of equipment and the use of capped equipment charges. Note: we've found a number of cases where Member A has lots of entries into the lab (based on door access logs), lots of equipment reservations, but virtually no equipment use in a month. Member B often has enabled equipment at the times reserved by Member A ... but has no corresponding entry into the lab at those times. Member A and Member B can expect to be invited to have a personal meeting with me to be certain that they understand this policy clearly. This is an important issue because it creates serious safety and liability concerns especially if lab members are using equipment for which they are not qualified. Moreover, from a fiscal perspective, it is unfair to the lab members that ARE abiding by rules and policies to ask them, in effect, to subsidize those that are not properly enabling equipment to avoid or reduce their lab fees. Thank you for your cooperation in this important matter. If you have any questions, do not hesitate to contact me. John -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Fri Sep 3 09:29:06 2010 From: mtang at stanford.edu (Mary Tang) Date: Fri, 03 Sep 2010 09:29:06 -0700 Subject: Reminder: Venture Clinic Today, 4 pm Message-ID: <4C812252.2000309@stanford.edu> Dear Labmembers: There will also be a Venture Clinic with Shahin Farschi of Lux Capital, Friday, Sept. 3, at 4 pm in Allen 201 (note room change). Learn about the current conditions in the venture world or discuss your startup ideas with an experienced venturist. Shahin may also be contacted directly: Shahin Farshchi, Ph.D. Senior Associate Lux Capital Management, LLC C: 925.323.2784 http://www.luxcapital.com From mtang at stanford.edu Fri Sep 3 09:35:44 2010 From: mtang at stanford.edu (Mary Tang) Date: Fri, 03 Sep 2010 09:35:44 -0700 Subject: Announcement: 2010 Lithography Workshop Message-ID: <4C8123E0.4060008@stanford.edu> As per Prof. Pease: The 2010 Lithography Workshop will be held in Hawaii from Nov. 7-11. Special rates for student presenters are available. See the attached for more information. If interested, contact program chairs Michael Fritze(mfritze at isi.edu)and VivekSingh (vivek.singh at intel.com). The workshop website is: www.lithoworkshop.org. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Sept Student Announcement-1.pdf Type: application/pdf Size: 27244 bytes Desc: not available URL: From svo at stanford.edu Fri Sep 3 15:05:28 2010 From: svo at stanford.edu (Sonny Vo) Date: Fri, 3 Sep 2010 15:05:28 -0700 Subject: Question for pmma users Message-ID: <000001cb4bb4$1e9949f0$5bcbddd0$@edu> Hello labmembers, Perhaps some of you have direct experience using pmma in anisole as a resist using UV lithography and can give me some useful numbers. From what literature I can find online, ebeam exposure or even uv exposure will make it positive, however, upon extensive exposure, crosslinking will occur to convert the pmma into negative tone (exposed features will not dissolve away in developer). I am new to pmma so I am not sure how long the UV exposure is in UV, seconds or tens of minutes even to get the crosslinking for negative tone. I am not concern at all about critical dimension or over exposure. I just want to either develop away the exposed part (positive tone) or keep the exposed part (negative tone) . I will trial and error it but getting some insight from you first would be much appreciated. Thank you Regards, Sonny --------------- "What makes the desert beautiful," said the Little Prince ,"is that somewhere it hides a well ." _.--. _ ;,- `' ( ,,, ( E#=====#############=: ] :_"' ,._( ``` `--' rock on Sonny Vo Ph.d candidate Department of Applied Physics, Stanford University (626) 216-4597 Harris Research Group: http://snow.stanford.edu/index.html -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Fri Sep 3 16:49:01 2010 From: mtang at stanford.edu (Mary Tang) Date: Fri, 03 Sep 2010 16:49:01 -0700 Subject: Fall Course Announcement - EE412: Adv. Nanofab. Lab. Message-ID: <4C81896D.4000003@stanford.edu> Dear Labmembers: We'd like to bring to your attention this course offering for this Fall term, EE412: Advanced Nanofabrication Laboratory. This is a team-project-based course with the aim to develop, characterize and document processes that will be of value to the SNF labmember community. The instructors are Profs. Howe, Solgaard, and Pruitt. Students will receive not only course credit, but lab time and supplies in support of their projects -- and of course the satisfaction of contributing to the lab community knowledge base. For more information, check out the Stanford Bulletin and the proposed course syllabus (https://snf.stanford.edu/SNF/processes/ee412/about-ee412). We are looking for students, mentors, and projects -- and hoping to be able to match everyone up by the first week of classes. Mentors (listed by Coral ID) and project groups thus collected so far: 1. ALD - Characterize and bring up the new ALD systems. Mentor: jprovine 2. STSETCH2 - Characterization/optimization of etch recipes. Mentors: mcvittie, mtang 3. RTA's - Bring up and characterize new RTA's. Mentor: emyers 4. EV Spraycoater - Characterize/optimize spraycoater recipes. Mentors: jparker, mahnaz 5. New liftoff resist - Qualify/characterize new single-layer, negative resists for liftoff metalization. Mentor: mahnaz Please note that each project group can have more than one project or project team. If you would like to enroll, serve as a mentor, or propose a Community Service project, please get in touch with one of us. And please spread the word. Thanks for your attention -- The EE412 Project Mentors From mtang at stanford.edu Fri Sep 10 11:44:14 2010 From: mtang at stanford.edu (Mary Tang) Date: Fri, 10 Sep 2010 11:44:14 -0700 Subject: New Link: Functional Area Status for Etch and Furnaces Message-ID: <4C8A7C7E.5040505@stanford.edu> Dear Labmembers - We'd like to bring to your attention two new links on the SNF home page. On the lower right side, under "Quick Links", you will find links to summaries of tool status in the Etch and the Furnace/Diffusion areas. These morning updates will be posted on a daily basis (Monday-Friday). We hope that these will be useful in providing a broader picture of the priority issues in each area. Let us know what you think. Team Etch/Team Furnaces From jaehlee at stanford.edu Sat Sep 11 12:03:44 2010 From: jaehlee at stanford.edu (Jae Hyung Lee) Date: Sat, 11 Sep 2010 12:03:44 -0700 Subject: [Lost last night] Clean Basket for pieces Message-ID: Dear labmembers, I was using three clean basket of my own and leave those in the fab last night in the clean bag. If anyone accidently took it please let me know. I reallly need it back since I am mostly working with pieces. Thanks, Jae -- Jae Hyung Lee PhD Candidate, Department of Electrical Engineering, Stanford University Cell: (650) 796-7456 From shott at stanford.edu Mon Sep 13 09:32:49 2010 From: shott at stanford.edu (John Shott) Date: Mon, 13 Sep 2010 09:32:49 -0700 Subject: Jack hammering on Via Pueblo .... Message-ID: <4C8E5231.6040809@stanford.edu> SNF Lab Members: As many of you have learned, there is significant jack hammering activity on Via Pueblo this morning. We were supposed to receive advance warning of when this would occur and did not. We are working with Stanford Project Management and McGuire & Hestor to try to get better warning information in the future. This activity may disrupt operations of the Raith, SEMs and high-resolution optical lithography. We apologize for this inconvenience and will hope to get more advance warning of activities of this type in the future. John From toecutter4ranger at gmail.com Mon Sep 13 13:02:27 2010 From: toecutter4ranger at gmail.com (ToeCutter) Date: Mon, 13 Sep 2010 13:02:27 -0700 Subject: Jack hammering on Via Pueblo .... In-Reply-To: <2524_1284395638_4C8E5276_2524_279_1_4C8E5231.6040809@stanford.edu> References: <2524_1284395638_4C8E5276_2524_279_1_4C8E5231.6040809@stanford.edu> Message-ID: <1162587A-BE79-4A25-AC78-42314A9548E5@gmail.com> While the vibration may be visible on the SEM imaging section of the Raith during normal SEM operations, and all of our other SEM's images as well, it should not be evident during any Ebeam Lithography writes due to the very short dwell times when the system unblanks and is actually performing an exposure operation. If anyone observes any artifact that could be attributed to these vibrations, please send me an SEM image and report and claim a free lunch from me! Thank you, James Conway On Sep 13, 2010, at 9:32 AM, John Shott wrote: > SNF Lab Members: > > As many of you have learned, there is significant jack hammering > activity on Via Pueblo this morning. We were supposed to receive > advance warning of when this would occur and did not. We are > working with Stanford Project Management and McGuire & Hestor to try > to get better warning information in the future. > > This activity may disrupt operations of the Raith, SEMs and high- > resolution optical lithography. > > We apologize for this inconvenience and will hope to get more > advance warning of activities of this type in the future. > > John > > > > From rshyam at stanford.edu Mon Sep 13 17:02:36 2010 From: rshyam at stanford.edu (Shyam Raghunathan) Date: Mon, 13 Sep 2010 17:02:36 -0700 Subject: EE PhD Oral Examination - Shyam Raghunathan - Friday, Sept 17, 10.15 am, CIS-X Auditorium Message-ID: EE Ph.D. Oral Examination Scaled Planar Floating-Gate NAND Flash Memory Technology: Problems and Novel Solutions Shyam Raghunathan Advisor: Prof. Krishna Saraswat Co-Advisors: Prof. Yoshio Nishi, Prof. Tejas Krishnamohan Chair: Prof. Butrus Khuri-Yakub Date: Sept 17th, Friday, 10.30 am (Refreshments at 10.15 am) Venue: Allen CIS-X Auditorium Flash memory is the most widely used non-volatile information-storage technology today. NAND Flash memories are ubiquitous in their use as portable storage media in cellphones, cameras, music players, and other portable electronic devices. In addition, NAND Flash memory has recently seen rapid adoption as Solid-state drives (SSD) in place of Hard-disk drives (HDD) in modern personal computers and data servers. In addition to greater speed, SSDs also provide much lower power consumption compared to HDDs. The NAND Flash memory device, consisting of a floating-gate transistor cell, is the most aggressively scaled electronic device, as evidenced by ever-increasing memory capacities. In this talk, we will examine some problems in the continued scaling of these structures and discuss novel solutions to overcome them. (1) Firstly, we investigate scaling of the conventional poly-silicon floating-gate, aimed at reducing cell-to-cell interference. We demonstrate experimentally a new reliability concern for the first time, arising due to programming current becoming increasingly ballistic through ultra-thin poly-silicon floating-gates. We also experimentally demonstrate doping-related issues in the poly-silicon floating-gate. (2) We then demonstrate a novel metal-based floating-gate cell for the first time, designed to overcome the problems discussed above. We explore factors that influence the choice of metal and we demonstrate excellent functionality in ultra-thin metal floating-gate cells scaled down to 3 nm TiN floating-gate thickness, thus greatly reducing cell-to-cell interference. (3) Finally, in order to facilitate continued scaling of the control dielectric, we explore replacement of the conventional Oxide-Nitride dielectric with high-k dielectric materials. We demonstrate integration of both poly-silicon and metal floating-gate cells with Al2O3 high-k control dielectric, thereby enabling the planar floating-gate cell. From ycjun at stanford.edu Wed Sep 15 09:36:09 2010 From: ycjun at stanford.edu (Young Chul Jun) Date: Wed, 15 Sep 2010 09:36:09 -0700 (PDT) Subject: University PhD Oral Defense In-Reply-To: <12759_1284401143_4C8E67F6_12759_5141_1_p06230907c8b416d53d1a@[171.64.84.39]> Message-ID: <495656092.91001.1284568569818.JavaMail.root@zm03.stanford.edu> RE: University PhD Oral Defense of Young Chul Jun / Remind Department of Applied Physics University PhD Dissertation Defense Plasmonic Control of Light Emission: Tailoring Light Emission Properties with Metal Nanostructures Young Chul Jun Applied Physics PhD Candidate Reseach Advisor: Professor Mark Brongersma September 20 (Monday), 2010 @4:15 p.m. Location: McCullough Building , Room 115 ABSTRACT Enhanced light-matter interactions in light-confining structures (such as optical cavities) have been extensively investigated for both fundamental studies and practical applications. Plasmonic nanostructures, which can confine and manipulate light down to ~1 nm scale, are becoming increasingly important. Many areas of optical physics and devices can benefit from such extreme light concentration and manipulation. For example, fluorescent molecule or quantum dot (QD) emission can be strongly modified and controlled via surface plasmon polariton (SPP) coupling. In this dissertation talk, we present our theoretical and experimental studies on QD emission in metal nanogap structures that can provide extreme field concentration, enhancing light-matter interactions significantly. We start with a theoretical analysis of dipole emission in metal-dielectric-metal (MDM) waveguide structures. We look at both infinite (i.e. planar) and finite thickness MDM structures. We find that both structures exhibit strong spontaneous emission enhancements due to the tight confinement of modes between two metallic plates and that light emission is dominated by gap SPP coupling. For planar structures we present analytical solutions for the enhanced dipole decay rate, while for finite thickness MDM structures (i.e. nanoslits) we present results from numerical simulations. Next, we present our experiments on the SPP coupling of CdSe/ZnS QD emission in metal nanoslits. First, we observed clear lifetime and polarization state changes of QD emission with slit width due to gap SPP excitation. Second, with optimized side grooves (i.e. combined slit-groove and hole-groove structures), we collimated QD emission vertically into a very narrow angle, achieving an unprecedented level of directionality control, and visualized it with confocal scanning microscopy. Third, by using two metal plates as electrodes, we dynamically modulated QD emission intensity and wavelength with external voltage. Finally, we extend our dipole emission calculation to several slot waveguide structures. We consider light emission in metal slots, metal-oxide-Si slots, and Si slot waveguides. We find that large spontaneous emission enhancement can be obtained over a broad range of wavelengths and that light emission is strongly funneled into slot waveguide modes. These represent broadband waveguide QED (quantum electro-dynamics) systems, which have unique merits for on-chip light sources and quantum information processings. These theoretical and experimental studies show that the SPP coupling of light emission is a very promising way to control light emission properties and may find broad application in spectroscopy, sensing, optoelectronics, and integrated optics. -------------- next part -------------- An HTML attachment was scrubbed... URL: From hector at AsylumResearch.com Wed Sep 15 12:18:29 2010 From: hector at AsylumResearch.com (Hector Cavazos) Date: Wed, 15 Sep 2010 19:18:29 +0000 Subject: boron doping tube Message-ID: <5A653CAD436BD74F8BAD5CA6872A34752CEFCA@Ex2010.AsylumResearch.com> I am trying to make a boron-doped etch stop in my n-type silicon and want to use the boron pre-dep tube at SNF. I need at least a 1um thick p++ silicon layer with at least a 5e18 concentration there. I can't go higher than 900C due to my device processing constrictions. Can anyone offer any recommendations for time and temp to do this? Would I need a dope and drive process and if so, how long of a drive? Thanks for any help!!! -Hector -------------- next part -------------- An HTML attachment was scrubbed... URL: From shott at stanford.edu Wed Sep 15 13:05:39 2010 From: shott at stanford.edu (John Shott) Date: Wed, 15 Sep 2010 13:05:39 -0700 Subject: Construction vibration about to begin .... Message-ID: <4C912713.8090606@stanford.edu> SNF Lab Members: We have just received notice that they will be tearing up more concrete on Via Pueblo starting shortly and scheduled to last for a period of about 2 hours. Ebeam, SEM, high-resolution lithography and AFM operations may be affected. While we would like to be able to notify you earlier in the process we were at least notified before the vibrations began this time. We will hope to do better as this project progresses. Note: Jim McVittie is working with our Wilcoxon 731A high-sensitivity accelerometer to see if we can quantify the magnitude of the vibration this time around in hopes of providing better information as to exactly how disruptive these construction activities are. Thanks, John From rshyam at stanford.edu Thu Sep 16 08:16:28 2010 From: rshyam at stanford.edu (Shyam Raghunathan) Date: Thu, 16 Sep 2010 08:16:28 -0700 Subject: Reminder: EE PhD Oral Examination - Shyam Raghunathan - Tomorrow (Friday), 10.15 am, CIS-X Auditorium Message-ID: EE Ph.D. Oral Examination Scaled Planar Floating-Gate NAND Flash Memory Technology: Problems and Novel Solutions Shyam Raghunathan Advisor: Prof. Krishna Saraswat Co-Advisors: Prof. Yoshio Nishi, Prof. Tejas Krishnamohan Chair: Prof. Butrus Khuri-Yakub Date: Sept 17th, Friday, 10.30 am (Refreshments at 10.15 am) Venue: Allen CIS-X Auditorium Flash memory is the most widely used non-volatile information-storage technology today. NAND Flash memories are ubiquitous in their use as portable storage media in cellphones, cameras, music players, and other portable electronic devices. In addition, NAND Flash memory has recently seen rapid adoption as Solid-state drives (SSD) in place of Hard-disk drives (HDD) in modern personal computers and data servers. In addition to greater speed, SSDs also provide much lower power consumption compared to HDDs. ? ? ? ?The NAND Flash memory device, consisting of a floating-gate transistor cell, is the most aggressively scaled electronic device, as evidenced by ever-increasing memory capacities. In this talk, we will examine some problems in the continued scaling of these structures and discuss novel solutions to overcome them. ? ? ? ?(1) Firstly, we investigate scaling of the conventional poly-silicon floating-gate, aimed at reducing cell-to-cell interference. ?We demonstrate experimentally a new reliability concern for the first time, arising due to programming current becoming increasingly ballistic through ultra-thin poly-silicon floating-gates. We also experimentally demonstrate doping-related issues in the poly-silicon floating-gate. ? ? ? ?(2) We then demonstrate a novel metal-based floating-gate cell for the first time, designed to overcome the problems discussed above. We explore factors that influence the choice of metal and we demonstrate excellent functionality in ultra-thin metal floating-gate cells scaled down to 3 nm TiN floating-gate thickness, thus greatly reducing cell-to-cell interference. ? ? ? ?(3) Finally, in order to facilitate continued scaling of the control dielectric, we explore replacement of the conventional Oxide-Nitride dielectric with high-k dielectric materials. We demonstrate integration of both poly-silicon and metal floating-gate cells with Al2O3 high-k control dielectric, thereby enabling the planar floating-gate cell. From shott at stanford.edu Fri Sep 17 07:54:05 2010 From: shott at stanford.edu (John Shott) Date: Fri, 17 Sep 2010 07:54:05 -0700 Subject: SNF Lab Member meeting: Wednesday, 9/22 - 10 a.m. Message-ID: <4C93810D.400@stanford.edu> SNF Lab Members and Faculty: We would like to invite you to a meeting to provide an update on a number of matters related to the Stanford Nanofabrication Facility. This meeting will be held in Allen 101X next Wednesday, September 22 from 10 a.m. to 11:30 a.m. Issues to be covered include: SNF Facility Upgrade under NSF ARI-R2 and Stanford BGM funding SNF Equipment Additions and Installation Update SNF User AdCom Comments - Nahid Harjee SNF Staff Reorganization SNF Safety Issues and recent toxic gas alarms SNC Update - Prof. Kam Moler Naturally, we will be happen to answer questions about these or other issues that you may have. Thanks, John and Roger From rshyam at stanford.edu Fri Sep 17 09:28:08 2010 From: rshyam at stanford.edu (Shyam Raghunathan) Date: Fri, 17 Sep 2010 09:28:08 -0700 Subject: Reminder: TODAY : EE PhD Oral Examination - Shyam Raghunathan - 10.15 am, CIS-X Auditorium In-Reply-To: References: Message-ID: EE Ph.D. Oral Examination Scaled Planar Floating-Gate NAND Flash Memory Technology: Problems and Novel Solutions Shyam Raghunathan Advisor: Prof. Krishna Saraswat Co-Advisors: Prof. Yoshio Nishi, Prof. Tejas Krishnamohan Chair: Prof. Butrus Khuri-Yakub Date: Sept 17th, Friday, 10.30 am (Refreshments at 10.15 am) Venue: Allen CIS-X Auditorium Flash memory is the most widely used non-volatile information-storage technology today. NAND Flash memories are ubiquitous in their use as portable storage media in cellphones, cameras, music players, and other portable electronic devices. In addition, NAND Flash memory has recently seen rapid adoption as Solid-state drives (SSD) in place of Hard-disk drives (HDD) in modern personal computers and data servers. In addition to greater speed, SSDs also provide much lower power consumption compared to HDDs. The NAND Flash memory device, consisting of a floating-gate transistor cell, is the most aggressively scaled electronic device, as evidenced by ever-increasing memory capacities. In this talk, we will examine some problems in the continued scaling of these structures and discuss novel solutions to overcome them. (1) Firstly, we investigate scaling of the conventional poly-silicon floating-gate, aimed at reducing cell-to-cell interference. We demonstrate experimentally a new reliability concern for the first time, arising due to programming current becoming increasingly ballistic through ultra-thin poly-silicon floating-gates. We also experimentally demonstrate doping-related issues in the poly-silicon floating-gate. (2) We then demonstrate a novel metal-based floating-gate cell for the first time, designed to overcome the problems discussed above. We explore factors that influence the choice of metal and we demonstrate excellent functionality in ultra-thin metal floating-gate cells scaled down to 3 nm TiN floating-gate thickness, thus greatly reducing cell-to-cell interference. (3) Finally, in order to facilitate continued scaling of the control dielectric, we explore replacement of the conventional Oxide-Nitride dielectric with high-k dielectric materials. We demonstrate integration of both poly-silicon and metal floating-gate cells with Al2O3 high-k control dielectric, thereby enabling the planar floating-gate cell. -------------- next part -------------- An HTML attachment was scrubbed... URL: From ahazeghi at stanford.edu Fri Sep 17 20:14:09 2010 From: ahazeghi at stanford.edu (Arash Hazeghi) Date: Fri, 17 Sep 2010 20:14:09 -0700 (PDT) Subject: Missing ASML reticle In-Reply-To: <1520473151.163723.1284779465709.JavaMail.root@zm03.stanford.edu> Message-ID: <615458149.163743.1284779649362.JavaMail.root@zm03.stanford.edu> Dear lab members, My ASML reticle (standard compu graphics red box) is missing, since I have not taken it outside the lab someone must have garbbed it by accident, I appriciate if you can check to see if you have it, my Coral ID (Ahazeghi) is written on the box and the job neame is CNFET_JOB. I cannot do anything without my mask. Thanks, Arash -------------- next part -------------- An HTML attachment was scrubbed... URL: From shott at stanford.edu Mon Sep 20 06:47:40 2010 From: shott at stanford.edu (John Shott) Date: Mon, 20 Sep 2010 06:47:40 -0700 Subject: Jack hammer schedule this morning ... Message-ID: <4C9765FC.4000805@stanford.edu> SNF Lab Members: McGwire-Hester will be doing some more demolition (AKA jack hammering) this morning from about 7:30 to 10 a.m. along Via Pueblo. This may affect vibration-sensitive activities in the lab. The site supervisor believes that this should complete most of the activity that creates significant vibration until they start compaction later in the construction process. Thanks, John From mtang at stanford.edu Mon Sep 20 08:51:03 2010 From: mtang at stanford.edu (Mary Tang) Date: Mon, 20 Sep 2010 08:51:03 -0700 Subject: EE412 Adv Nanofab Lab: First Class Wed, 4 pm, Allen 101 Message-ID: <4C9782E7.6070300@stanford.edu> Dear Labmembers -- Just a reminder that EE412 is coming this term: Advanced Nanofabrication Laboratory. This is a team-project-based course with the aim to develop, characterize and document processes that will be of value to the SNFlabmember community. The instructors are Profs. Howe, Solgaard, and Pruitt. Students will receive not only course credit, but lab time and supplies in support of their projects -- and of course the satisfaction of contributing to the lab community knowledge base. There's still time to think about participating. We are looking for students, mentors, and projects -- and hoping to be able to match everyone up by the first week of classes. Mentors (listed by Coral ID) and project groups thus collected so far: 1. ALD - Characterize and bring up the new ALD systems. Mentor: jprovine 2. STSETCH2 - Characterization/optimization of etch recipes. Mentors: mcvittie, mtang 3. RTA's - Bring up and characterize new RTA's. Mentor: emyers 4. EV Spraycoater - Characterize/optimize spraycoater recipes. Mentors: jparker, mahnaz 5. New liftoff resist - Qualify/characterize new single-layer, negative resists for liftoff metalization. Mentor: mahnaz Please note that each project group can have more than one project or project team. If you would like to enroll, serve as a mentor, or propose a Community Service project, please get in touch with one of us. And please spread the word. Thanks for your attention -- The EE412 Project Mentors -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility CIS Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mtang at stanford.edu Mon Sep 20 10:27:49 2010 From: mtang at stanford.edu (Mary Tang) Date: Mon, 20 Sep 2010 10:27:49 -0700 Subject: Process Clinic, Today, 2-3 pm Message-ID: <4C979995.8090105@stanford.edu> Dear Labmembers -- There will be a Process Clinic today, Monday, Sept. 20, from 2-3 pm in the cubicle area outside Maureen's office. Bring device sketches, process questions/runsheets, and mask layouts. Staff and experienced labmembers will be on hand to brainstorm solutions. Your SNF staff From edmyers at stanford.edu Mon Sep 20 13:42:56 2010 From: edmyers at stanford.edu (Ed Myers) Date: Mon, 20 Sep 2010 13:42:56 -0700 Subject: AW610 RTP system release Message-ID: <6.2.5.6.2.20100920133553.0291e440@stanford.edu> All, I have completed the high temperature oxide growth qualification for both of our new aw610 systems. I've attached a spread sheet showing the resulting oxide thickness for 5 consecutive wafers along with the data from the last AG4100 qualification run. As you can see all three systems are within 10angstroms. I am releasing the second system, aw610-r (the gold contaminated system) for develop recipe development. I want to start with recipes which are controlled by the pyrometer, or recipes with steady state temperatures greater than 600C. Once we get these recipes installed and running, I will convert the system to thermocouple control for recipes less than 600C. My to finish the pyrometer work this week and do the TC work next week. Please contact me and schedule a time for your recipe development, testing, annealing and training. Regards, Ed -------------- next part -------------- A non-text attachment was scrubbed... Name: 610 start-up thickess comparison.xls Type: application/octet-stream Size: 23552 bytes Desc: not available URL: From rissman at stanford.edu Tue Sep 21 13:35:04 2010 From: rissman at stanford.edu (Paul Rissman) Date: Tue, 21 Sep 2010 13:35:04 -0700 Subject: Fwd: Raman Microscopy talk Message-ID: <20100921203531.9235B178BF9@smtp.stanford.edu> >TALK IS NOW IN ALLEN 101 (Linville Room) >Hi all, > >We will have Andrew King, a representative of Renishaw Plc - >Spectroscopy Products Division, UK, which is specialized for Raman >microscopy. He will give a talk about their technology and >equipment at 1:30pm on September 21 in CIS101. If you are >interested in this new capability, please attend the presentation. > >Yoshio Nishi <<...>> > > > From shott at stanford.edu Wed Sep 22 03:19:53 2010 From: shott at stanford.edu (John Shott) Date: Wed, 22 Sep 2010 03:19:53 -0700 Subject: Toxic gas alarm shortly after midnight Monday night .... Message-ID: <4C99D849.1000306@stanford.edu> SNF Lab Members: As a number of you are aware shortly after midnight on Monday night (technically at about 00:13 Tuesday morning) there was a blue toxic gas alarm that rang and evacuated the lab. This was triggered by the detector that monitors POCl3 and BBr3 in the Tylan bank that contains tylan5 and tylan6 .... although, I believe that the problem had nothing to do with the tubes in that bank. At about 00:30 I received an automated call from the toxic gas monitoring system and at about 00:40 received a call from Stanford work control. I arrived at the lab at about 1 a.m. After studying the alarm history and looking at detected levels .... which had returned to zero about 10 minutes after the initial alarm ... I entered the lab with all of our hand-held monitoring instruments. At that point, I was unable to detect any levels of any toxic gases. I did, however, find that the vacuum pump for tylannitride had ruptured the pump casing and blew pump oil outside the cabinet. It is likely that this hot pump oil ... that contains residuals of dichlorosilane and hydrogen chloride ... was the source of the chemical that triggered the POCl3/BBr3 sensor in the adjacent Tylan bank. Interestingly, there was no record of tylannitride running anything other than the PUMP10 program at this time. It is highly unusual for a pump to have ruptured in this way when it was under vacuum with nothing but a bit of nitrogen flowing. While tylannitride is down until further notice pending pump replacement and thorough testing of all elements in the system, everything else in the lab should be ready for normal service. I have done my best to mop up and dispose of the pump oil outside of the tylannitride cabinet and have blanked off the exhaust from that pump that leads to the burn box so that there will be no unwanted leak of room air into the burnbox system. If anyone smelled anything unusual during this incident or has any relevant information, please contact me. At this point, aside from tylannitride, the lab is operational and available for use. Thank you for your continued support, John From shott at stanford.edu Wed Sep 22 08:20:04 2010 From: shott at stanford.edu (John Shott) Date: Wed, 22 Sep 2010 08:20:04 -0700 Subject: Jack hammering from about 8:30 to 9:30 this morning ... Message-ID: <4C9A1EA4.9010906@stanford.edu> SNF Lab Members: McGuire-Hester just informed me that they have a bit more demolition work along Via Pueblo this morning that will last from about 8:30 to 9:30 this morning. I'm hopeful that that will get us past the demolition phase ... Thanks, John From gsosa at stanford.edu Thu Sep 23 10:39:04 2010 From: gsosa at stanford.edu (Gary J Sosa) Date: Thu, 23 Sep 2010 10:39:04 -0700 (PDT) Subject: Litho Nanospec In-Reply-To: <268126035.389983.1285263113874.JavaMail.root@zm08.stanford.edu> Message-ID: <449724256.390838.1285263544554.JavaMail.root@zm08.stanford.edu> Hi Labmembers... Just to inform you that the "Litho Nanospec" that used to be directly across from Karl Suss Aligner #2 has moved. It is now located in the "Old Jerabic Mask Making Room", to the left of the Tencor P2. This may be a temporary or permanent location for this tool, but until further notice, this is its new home. For any new users in the lab, please ask any Litho Staff Member if you need help finding the Jerabic Room. Thank you for your patience and understanding... ..Gary From mahnaz at stanford.edu Thu Sep 23 15:43:41 2010 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Thu, 23 Sep 2010 15:43:41 -0700 Subject: New exhaust hoof and Nanospec Message-ID: <4C9BD81D.6030103@stanford.edu> Hello all, We have new exhaust hood for the four hot plates across the Karlsuss. The table and the hood was designed by Jim Haydon. We already moved the old tables out and the hot plates are hooked up and Gary is calibrating them as i am writing this email. We had to move the nanospec to the " LITHO METROLOGY room" or AFM room. So please take a look and let us know how you like it? Please tank Jim, Gary and Mario when you see them. it looks beautiful. mahnaz From tholme at stanford.edu Thu Sep 23 16:05:10 2010 From: tholme at stanford.edu (Tim Holme) Date: Thu, 23 Sep 2010 16:05:10 -0700 Subject: mercury probe Message-ID: Does anyone have access to a mercury probemeasurement system to measure the capacitance/resistance of thin films? I'd like to run a few simple test on films we've deposited, no more than 10 measurements would be needed. I'd much appreciate if one of you would be willing to share your tool and 30 minutes of your time to help out. Thanks very much, Tim -------------- next part -------------- An HTML attachment was scrubbed... URL: From insun at stanford.edu Fri Sep 24 12:17:38 2010 From: insun at stanford.edu (Insun Park) Date: Fri, 24 Sep 2010 12:17:38 -0700 Subject: Does anyone know about 3D process simulators? Message-ID: Hello, I am trying to figure out how much stress is developed during Si thermal oxidation on a Si nanostructure. Does anyone know about 3D process simulators that can simulate thermal oxidation stress on Si? Thanks for any help! Insun -------------- next part -------------- An HTML attachment was scrubbed... URL: From mahnaz at stanford.edu Fri Sep 24 14:03:42 2010 From: mahnaz at stanford.edu (Mahnaz Mansourpour) Date: Fri, 24 Sep 2010 14:03:42 -0700 Subject: Shut down yes oven Message-ID: <4C9D122E.3090305@stanford.edu> Hello all, We need to swap few tables around in the Litho area and we have decided to do it early Monday morning ( 9/27). One the table to be changed is the YES oven so we need to turn it off and of course turn it back on when the table swapped. The YES oven will be shut from 8 am to 9:30 am. you will like the new look, I promise you. mahnaz From dasgupta at stanford.edu Tue Sep 28 13:09:37 2010 From: dasgupta at stanford.edu (Neil Dasgupta) Date: Tue, 28 Sep 2010 13:09:37 -0700 (PDT) Subject: removing PR after argon dry etching Message-ID: <1289100878.447210.1285704577764.JavaMail.root@zm03.stanford.edu> Hi labmembers, I am running into a wall with my new process. We are using 1.6 um of 3612 resist as an etch mask for dry etching in the MRC etcher. Our dry etch recipe is argon sputtering/etching for 10 minutes at 100 W. This causes hardening/texturing of the resist, which looks like craters in the SEM after the dry etch. The problem is that I have not been able to remove this PR after this hardening occurs. I have tried 10 minutes O2 plasma in drytek 1, followed by acetone sonication for 10 minutes, followed by another O2 descum, but the resist still remains. The samples have Al metal on them, so that I can not use piranha. They are also gold contaminated. I imagine this is a problem people have encountered before, so any advice, especially specific recipes would be greatly appreciated. Thanks, Neil Dasgupta