Reminder : EE PhD Oral Examination - Jie Zhang, Today, 2:00 PM
zhangjie at stanford.edu
Mon Jun 20 09:48:23 PDT 2011
Title : Variation-Aware Design of Carbon Nanotube VLSI Circuits
Speaker : Jie (Jerry) Zhang
Advisor : Prof. Subhasish Mitra
Date : June 20, 2011
Time : 2:00 pm (refreshments at 1:45 pm)
Location : CIS-X Auditorium
Carbon Nanotube Field Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient future electronic systems. Variations specific to carbon nanotubes (CNTs) pose major obstacles to energy-efficient and robust CNFET digital VLSI. CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. CNT processing techniques alone are inadequate to overcome these challenges.
We present an integrated approach, combining CNFET modeling, processing and circuit design, to create VLSI circuits tolerant to CNT variations. Probabilistic models, calibrated using experimental data, are used to analyze the effects of two major sources of CNT variations: metallic CNTs (CNTs with no / very small bandgaps) and CNT density variations (due to the non-uniformity in CNT positioning).
Using these models, we create a probabilistic framework to derive simple yet useful CNFET processing and circuit design guidelines to overcome CNT variations. The effectiveness of this approach is demonstrated using two examples:
1. CNT variations result in functional failures of CNFET circuits. The failure probability may be reduced through CNFET sizing but at substantial energy costs. A new layout design technique, which engineers correlation among various CNFETs, reduces CNFET circuit failure probability at significantly lower costs.
2. We quantify the impact of CNT variations on delay variations of CNFET circuits. We explore the space of CNFET sizing, together with various possibilities to improve CNFET processing, to minimize circuit delay variations at low energy costs.
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