Oral Exam Announcement: Byoungil Lee

Byoungil Lee bilee at stanford.edu
Tue Sep 13 17:14:17 PDT 2011

Stanford University PhD Oral Defense - Department of Electrical Engineering

Speaker: Byoungil Lee
Date: September 16, 2011 (Friday)
Time: 1:00 PM (Refreshments served at 12:45 PM)
Location: Paul Allen Auditorium (CISX-AUD)
Advisor: H.-S Philip Wong

Title:  Fabrication and Characterization of Nanoscale Resistance Change Memory


As the current charge-based memory technologies such as DRAM and Flash Memory are facing their fundamental scaling limits, new types of memory technologies such as spin-torque-transfer RAM (STTRAM), phase-change memory (PCM), and metal-oxide resistance change memory (RRAM) have been actively explored. Among these candidates, RRAM devices utilize the resistance change property of the metal-oxide films, and have shown promising results such as fast switching speed, low programming current, and good CMOS compatibility. Despite the potential advantages, they suffer from the critical issues that must be addressed for the high-density memory application, which includes existence of forming-process, large variation in switching characteristics, and cell selection issue in the cross-point structure. 

In this talk, I will first demonstrate the process and characterization methodology for RRAM devices to verify the characteristics and potential issues in the nanoscale regime down to 50X50 nm2 size. Unipolar switching memory cells using NiO thin films were fabricated by ebeam lithography process. The device characteristics and the scaling trends will be discussed. 

Next, I will present two novel RRAM structures developed by the process and characterization methods established in the previous section. In the first structure, both top and bottom electrodes are processed prior to the metal-oxide deposition, and therefore, contamination-less programming region is achieved in the memory cell. Moreover, the novel structure features more confined conduction path compared to the conventional structure, which results in narrower low-resistance distribution. The process flow and characteristics of the nanoscale NiO memory cells using this structure will be presented. 

In the second structure, an oxide-to-oxide interface is incorporated inside the memory cell in order to utilize the initial leakage and eliminate the high-voltage forming process. Due to this initial leakage, the as-fabricated AlOx memory cells exhibit low-resistance sates, while the conventional AlOx devices show high-resistance initial states.  The new memory cell does not require the high-voltage forming process since the as-fabricated cells can be switched to high-resistance states with a regular RESET voltage. 

Finally, application of the forming-less AlOx cells to the complementary resistive switch (CRS) scheme will be discussed using the measured cell characteristics. The CRS scheme was proposed in 2010 as a potential solution to the high-density cross-point memory arrays. The novel memory cells with forming-less property demonstrate promising results that enables the CRS operation using bipolar switching RRAM cells. 

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