From shott at stanford.edu Sat Dec 1 13:59:53 2012 From: shott at stanford.edu (John Shott) Date: Sat, 1 Dec 2012 13:59:53 -0800 Subject: =?utf-8?Q?Steam_back_on_=E2=80=A6?= Message-ID: SNF lab members and Allen Building occupants: As of about 1:30 today steam service to the building has been restored and Jose Solorzano has done a thorough check of all affected systems and found them to be functioning properly. In particular, temperature and humidity control in the clean room has been restored to normal levels. Other utilities such as domestic hot water should also be ready for use. Thanks to the steam shop and to Jose for getting this repair done and systems brought back on line sooner than expected. To my knowledge all SNF operations can resume as normal. Have a good weekend, John Sent from my iPhone From mikebell at stanford.edu Sun Dec 2 18:07:18 2012 From: mikebell at stanford.edu (Michael Bell) Date: Sun, 2 Dec 2012 18:07:18 -0800 Subject: Badger Questions and Concerns for industrial users Message-ID: <003f01cdd0fa$eca7be30$c5f73a90$@stanford.edu> Pradeep, As a current user of Badger I?m sure you?ve been relieved to see that much of the look and feel of the application is identical to that of Coral and that there are a number of enhancements that benefit members and staff alike. In addition to the presentations a couple of months ago, more information on the conversion specifics will be available shortly. Rest assured that every effort is being made to make the transition as painless as possible. It is true that Badger, like so many software resources at Stanford and elsewhere, restricts offsite access. Stanford does supply a VPN client that enables offsite use of the application in most cases. I understand that your employer has a particularly restrictive policy concerning this. I can certainly appreciate their concerns for the security of mission critical resources and would only add that, firewalls, data encryption and increasingly complex authentication strategies are a sometimes annoying, but inevitable consequence of the need for data and application security in the face of sophisticated threats. I have used the Stanford VPN successfully for years and have found it to be robust and reliable. I?m hopeful that most members, like myself, will find that offsite access from home, work or the local caf? will not be an issue. The good news on multiple accounts is that Badger can support functionality identical to that of Coral. We will have more information on this and other issues in the very near future. Again, we are committed to making the conversion to Badger as seamless as possible and expect most members to find that the conversion will make the scheduling and use of equipment in Stanford?s shared labs more convenient. Regards, Michael Bell -------------- next part -------------- An HTML attachment was scrubbed... URL: From Saraswat at cis.stanford.edu Mon Dec 3 04:26:40 2012 From: Saraswat at cis.stanford.edu (Krishna Saraswat) Date: Mon, 3 Dec 2012 04:26:40 -0800 Subject: Seminar on "Light-Emitting Diodes for Illumination Applications" Message-ID: Light-Emitting Diodes for Illumination Applications Mike Krames (CTO, Soraa) 4:15pm, Dec 3 (Monday) Location: Paul Allen Building (CIS)-101X Abstract - Light-Emitting Diode (LED) technology advancements accelerated with the introduction of GaN-based blue- and white-emitting LEDs in the 1990s and have ushered in an era of new lighting products with unprecedented luminous efficacy and the potential for substantial savings in worldwide electricity consumption. However, the very high prices associated with these new products are limiting the adoption rate and threaten to substantially reduce and/or delay the positive impact that is promised by solid state lighting. A primary reason for the high costs are the performance limitations and complicated semiconductor processing operations inherent to the utilization of foreign substrates as the materials platforms for most of today's GaN-based LEDs. In contrast, recent advancements in GaN substrate technology have provided an opportunity for products platforms based on the native substrate. This technology platform, GaN-on-GaN(tm), opens the path to new operating regimes and simplified LED architectures which enable unprecedented performance and revolutionary designs for solid-state lighting products. First generation products based on GaN-on-GaN(tm) will be described. Speaker Bio - Mike Krames received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, IL, in 1995, under the supervision of Prof. Nick Holonyak, Jr. After graduation, he joined Hewlett-Packard Optoelectronics Division as a research engineer developing high-power visible-spectrum LEDs. He subsequently formed and ran the Advanced Laboratories for Lumileds Lighting Co., and later Philips Lumileds, in San Jose, CA. There his research focused on advanced III-nitride epitaxy, LED device technology, and luminescent materials for photon down-conversion. Mike was involved in spearheading several technology advancements at Lumileds, including flip-chip technology (the basis for Luxeon(tm)), thin-film technology, photonic crystal LEDs, ceramic phosphors, and advancing understanding behind the "droop" mechanism in InGaN-GaN LEDs. In 2009, Mike joined the management team of Soraa as Chief Technology Officer. Mike is a senior member of IEEE and has published more than 75 papers and been granted more than 80 U.S. patents in the field of solid-state lighting and displays. From jihwanan at stanford.edu Tue Dec 4 10:45:48 2012 From: jihwanan at stanford.edu (JIHWAN AN) Date: Tue, 4 Dec 2012 10:45:48 -0800 Subject: Furnace on campus? Message-ID: Hi all, I'm Jihwan in Prinz group. I am looking for a furnace which can go up to ~1500C on campus. Anybody know where I can find it? Thanks, Jihwan -- Jihwan An Ph.D. Candidate Nanoscale Prototyping Laboratory (NPL) Department of Mechanical Engineering Stanford University, CA cell : 650-862-0414 e-mail: jihwanan at stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From jprovine at stanford.edu Tue Dec 4 10:56:09 2012 From: jprovine at stanford.edu (J Provine) Date: Tue, 4 Dec 2012 10:56:09 -0800 Subject: Furnace on campus? In-Reply-To: References: Message-ID: how big of a sample do you have, what cleanliness is it, and what gases/pressure do you need the ambient to be? j On Tue, Dec 4, 2012 at 10:45 AM, JIHWAN AN wrote: > Hi all, > > I'm Jihwan in Prinz group. I am looking for a furnace which can go up to > ~1500C on campus. Anybody know where I can find it? > > Thanks, > Jihwan > > > -- > Jihwan An > Ph.D. Candidate > Nanoscale Prototyping Laboratory (NPL) > Department of Mechanical Engineering > Stanford University, CA > > cell : 650-862-0414 > e-mail: jihwanan at stanford.edu > -------------- next part -------------- An HTML attachment was scrubbed... URL: From mdeal at stanford.edu Tue Dec 4 11:01:11 2012 From: mdeal at stanford.edu (Michael Deal) Date: Tue, 04 Dec 2012 11:01:11 -0800 Subject: Mentors and Projects needed for SNF/NNIN Research Experience for Undergraduates (REU) program Message-ID: <50BE4877.8080808@stanford.edu> An HTML attachment was scrubbed... URL: From jihwanan at stanford.edu Tue Dec 4 11:30:29 2012 From: jihwanan at stanford.edu (JIHWAN AN) Date: Tue, 4 Dec 2012 11:30:29 -0800 Subject: Furnace on campus? In-Reply-To: References: Message-ID: My sample is ZrO2 ceramic. Need an annealing in ambient air, gold-contaminated, no outgassing. Thanks Jihwan On Tue, Dec 4, 2012 at 10:45 AM, JIHWAN AN wrote: > Hi all, > > I'm Jihwan in Prinz group. I am looking for a furnace which can go up to > ~1500C on campus. Anybody know where I can find it? > > Thanks, > Jihwan > > > -- > Jihwan An > Ph.D. Candidate > Nanoscale Prototyping Laboratory (NPL) > Department of Mechanical Engineering > Stanford University, CA > > cell : 650-862-0414 > e-mail: jihwanan at stanford.edu > -- Jihwan An Ph.D. Candidate Nanoscale Prototyping Laboratory (NPL) Department of Mechanical Engineering Stanford University, CA cell : 650-862-0414 e-mail: jihwanan at stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From snf-conversion at badgerlms.com Tue Dec 4 11:33:56 2012 From: snf-conversion at badgerlms.com (snf-conversion at badgerlms.com) Date: Tue, 4 Dec 2012 11:33:56 -0800 Subject: Important Badger Conversion Instructions Message-ID: <004301cdd256$4e193e30$ea4bba90$@badgerlms.com> SNF Lab Members: As most of you know SNF is in the process of converting from the Coral application to Badger Lab Management Software. Members will use Coral until the start of the holiday break and use Badger after the break. Reservations for after the break can be made in Badger with the usual reservation horizons. Many members already have Badger accounts and know that the look and feel of Badger is similar to Coral. New Badger users will have no trouble performing all of their normal functions. Our hope is to make this transition as simple as possible. It is; however, critical that all members read the information at the website below and move quickly to follow the instructions. https://www.stanford.edu/group/snf/Badger/SNF-Conversion.html Important Dates - 12-14 Final day to complete your application and verify your data in Coral and Badger. 12-21 Lab Closes - Coral use ends. 1-8 Lab Reopens - Badger is used over the break for reservations starting on the 8th. Regards, The SNF Conversion Team -------------- next part -------------- An HTML attachment was scrubbed... URL: From dasgupta at stanford.edu Tue Dec 4 13:34:22 2012 From: dasgupta at stanford.edu (Neil Dasgupta) Date: Tue, 4 Dec 2012 13:34:22 -0800 (PST) Subject: GaAs etching in PQuest In-Reply-To: <1681907268.8904378.1354656674873.JavaMail.root@stanford.edu> Message-ID: <1512285789.8906663.1354656862032.JavaMail.root@stanford.edu> Hi labmembers, I am preparing a new process which involves etching features into GaAs. I haven't worked much with GaAs in the past, and was hoping to benefit from the existing expertise. I was planning to use P Quest, and was wondering if anybody has experience etching GaAs in this machine recently, and might be able to share recipes/etch rates (including selectivity for mask materials). I would like to etch on the order of 1 micron deep features. Also, if you recommend any surface cleaning/pre-treatments before the etch, it would be greatly appreciated. Thank you, Neil Dasgupta Prinz Group From kangning at stanford.edu Tue Dec 4 15:03:44 2012 From: kangning at stanford.edu (kangning) Date: Tue, 4 Dec 2012 15:03:44 -0800 Subject: Which one shall I choose between Sirion and DB235 Dual-Beam? Message-ID: <201212041503397480875@stanford.edu> Hi everyone, I was wondering if anyone in this list is familiar with the SEMs in the SNL. I want to take some images of the fine structures on bacterial surface, which may need a resolution of at least 10 nm. I am planning to get trained on the SEMs in the SNL. It appears that before qualified to the training for FEI Magellan 400 XHR one has to be trained on either FEI Sirion SEM or the FEI DB235 Dual-Beam FIB/SEM. Could anyone make a suggestion that which one of the two is the better for my experiment with fixed bacteria? I hope to work on that one first and then consider whether to move on to Magellan. Thanks a lot! Best, Kangning Kangning Ren, Ph.D. Zarelab, Department of Chemistry Stanford University Tel: +1-650-723-8280 Email: kangning at stanford.edu Lab website: http://www.stanford.edu/group/Zarelab/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From svo at stanford.edu Tue Dec 4 15:28:38 2012 From: svo at stanford.edu (Sonny Vo) Date: Tue, 4 Dec 2012 15:28:38 -0800 Subject: GaAs etching in PQuest In-Reply-To: <1512285789.8906663.1354656862032.JavaMail.root@stanford.edu> References: <1681907268.8904378.1354656674873.JavaMail.root@stanford.edu> <1512285789.8906663.1354656862032.JavaMail.root@stanford.edu> Message-ID: hi Neil! how's it be?! This guy sonny vo had a lot of amazing GaAs etches there. Just enable pquest, find a 'svo gaas etch' or anything with svo, load sample, hit run and you can say something like, 'i want my samples to turn into gold.' and after 45 minutes, you get your wish. Make sure to make eye contact with the machine when you say this. This is important. Active Pquest users know how emotional this machine can get. "Yusi Chen" , a fellow Harris Group has been visiting the pawn shop regularly with his samples so connect with him. $onny On Tue, Dec 4, 2012 at 1:34 PM, Neil Dasgupta wrote: > Hi labmembers, > > I am preparing a new process which involves etching features into GaAs. I > haven't worked much with GaAs in the past, and was hoping to benefit from > the existing expertise. I was planning to use P Quest, and was wondering > if anybody has experience etching GaAs in this machine recently, and might > be able to share recipes/etch rates (including selectivity for mask > materials). I would like to etch on the order of 1 micron deep features. > Also, if you recommend any surface cleaning/pre-treatments before the > etch, it would be greatly appreciated. > > Thank you, > Neil Dasgupta > Prinz Group > -- Regards, Sonny ----*** Department of Applied physics, Stanford University research group: http://snow.stanford.edu/index.html* 626-216-4597 -------------- next part -------------- An HTML attachment was scrubbed... URL: From cfchiang at stanford.edu Thu Dec 6 00:06:30 2012 From: cfchiang at stanford.edu (Chia-Fang Chiang) Date: Thu, 6 Dec 2012 00:06:30 -0800 (PST) Subject: PhD Defense Announcement: Chia-Fang Chiang In-Reply-To: <1590060598.11151611.1354780654494.JavaMail.root@stanford.edu> Message-ID: <1940164915.11155763.1354781190410.JavaMail.root@stanford.edu> Stanford University Ph.D. Oral Examination ? Dept. of Mechanical Engineering Title: Micromachined Temperature Compensated Pressure Sensor Implemented Using a Multi-Sensor Integration Platform Speaker: Chia-Fang Chiang Advisor: Professor Thomas W. Kenny Date: Friday, December 14, 2012 Time: 10:00 am (refreshments at 9:45 am) Location: Hartley conference center (Mitchell Earth Sciences) - Room 130 Abstract : Micromachined pressure sensors are widely used in our everyday lives: in automobiles they are implemented to monitor tire pressure and detect side crashes; in medical devices they are used to track blood pressure in the brain; and in navigation they are utilized to determine altitude and assist global positioning system (GPS) receivers. While the requirements for a pressure sensor vary depending upon the specific application, a common requirement is accurate sensing over a wide operating temperature range (-40 ? 125 ?C). I will begin by introducing our capacitive pressure sensor design and demonstrating how it outperforms a piezoresistive pressure sensor with respect to temperature insensitivity. To further reduce temperature dependence, a high resolution resonant thermometer has been cofabricated with the capacitive pressure sensor, enabling the tracking of temperature fluctuations on the die and correction of the associated pressure error. In the second half of the talk, I will discuss our development of a resonant pressure sensor. This is motivated by the emerging demand of altimeters which require high resolution (10Pa/meter). As the design is coupled to the die strain, the accuracy of the resonant pressure sensors is strongly influenced by errors induced by both temperature and package stress. We address this limitation with a multiple sensor solution where temperature and strain sensors are cofabricated to reduce the pressure sensor?s temperature and package stress dependence, thus improving accuracy. Throughout the talk, I will discuss the process flows enabling the fabrication of such structures. Key developments include time insensitive vapor etching of silicon dioxide with hydrofluoric acid to release structures as well as the fabrication of structures that can be driven and sensed in both in-plane (x,y) and out-of-plane (z) directions on either bulk silicon or SOI wafer substrates. -------------- next part -------------- An HTML attachment was scrubbed... URL: From hongyuc at stanford.edu Thu Dec 6 10:43:18 2012 From: hongyuc at stanford.edu (Henry Hong-Yu Chen) Date: Thu, 6 Dec 2012 10:43:18 -0800 Subject: Preview of IEDM Presentations at Stanford: 9am-12pm on Dec. 7th, Fri @Packard 202 Message-ID: *Preview of IEDM Presentations at Stanford* * Date: December 7th, 2012 (Friday) Time: 9am-12pm Place: Packard 202 Host: Prof. H.-S. Philip Wong* *1. 9:00 am* 10.4 A Neuromorphic Visual System Using RRAM Synaptic Devices with Sub-pJ Energy and Tolerance to Variability: Experimental Characterization and Large-Scale Modeling, *S. Yu*, B. Gao, Z. Fang***, H. Yu**, J. Kang*, H.-S. P. Wong, Stanford University, *Peking University, **South University of Science and Technology, ***A*STAR We report metal oxide resistive switching memory (RRAM) as synaptic devices for a neuromorphic visual system. At the device level, we experimentally characterized the gradual resistance modulation of RRAM by hundreds of identical pulses and a low energy consumption (<1 pJ per spike). At the system level, we simulated the performance of image orientation selectivity on a neuromorphic visual system which consists of CMOS neuron circuits and a 16 kb RRAM array. It was found that the system can tolerate the variability which is commonly present in RRAM devices. *2. 9:30 am** * 20.5 Electrode/Oxide Interface Engineering by Inserting Single-Layer Graphene: Application for HfOx?Based Resistive Random Access Memory, *H.-Y. Chen*, H. Tian*, B. Gao, S. Yu, J. Liang, J. Kang***, Y. Zhang**, T.-L. Ren*, H.-S. P. Wong, Stanford University, *Tsinghua University, **Lawrence Berkeley National Laboratory, ***Peking University In this paper, electrode/oxide interface with inserted single-layer graphene (SLG) is studied using Ramen spectroscopy and electrical measurement. Raman mapping and single point measurements show noticeable changes in both D-band and G-band signal of SLG during the electrical cycling. This might suggest a new methodology to investigate the migration of oxygen ions in metal oxide resistive random access memory (RRAM). Applying this interface engineering technique to HfOx-based RRAM, the SLG increases low resistance state (LRS) resistance (> 1M?) due to its intrinsically high out-of-plane resistance. This enables the reduction of RESET current by 22X and programming power consumption by 47X. This work indicates that interface engineering design plays an important role in addition to exploring different metal oxides or metal electrode materials for RRAM. *3. 10:00 am* 14.6 State-of-the-art Graphene Transistors on Hexagonal Boron Nitride, High-k, and Polymeric Films for GHz Flexible Analog Nanoelectronics, *J. Lee *, K. Parrish, F. Chowdhury, T.-J. Ha, Y. Hao, L. Tao, A. Dodabalapur, R. Ruoff, D. Akinwande, University of Texas, Austin We report state-of-the-art graphene transistors for flexible nanoelectronics with record current density, intrinsic gain, extrinsic frequency metrics, and the highest doubler conversion gain and power. In addition, current saturation, and robust electrical stability down to a record 0.7mm bending radius, and immersion in liquids were demonstrated for the first time. *4. 10:30 am* 24.7 Exceeding Nernst Limit (59mV/pH): CMOS-Based pH Sensor for Autonomous Applications, *K. Parizi*, A. Yeh, A. Poon, H.S.P. Wong, Stanford University A highly sensitive and accurate field-effect sensor was obtained in a standard differential pair CMOS structure without Ag/AgCl reference electrode. The device is composed of two sensors each with a floating gate (FG) field effect transistor (FET), a control gate (CG) and an extended sensing gate (SG). By extending the sensing gate and engineering the capacitance value of the CG, we achieved a remarkable sensitivity of 130mV/pH for our pH sensor exceeding the fundamental Nernst limit, 59mV/pH. In addition, we removed the bulky Ag/AgCl reference electrode by a novel technique employing differential measurement to cancel the effect of the common abnormal potential change occurs in the solution. *5. 11:00 am* 26.1 Understanding Metal Oxide RRAM Current Overshoot and Reliability Using Kinetic Monte Carlo Simulation,* S. Yu*, X. Guan, H.-S.P. Wong, Stanford University A Kinetic Monte Carlo simulator is developed for metal oxide resistive random access memory (RRAM) to study a full set of RRAM characteristics such as set/forming current overshoot, endurance, and retention. The simulations suggest that 1) eliminating the forming process and decreasing the parasitic capacitance is required for minimizing the overshoot effect and reducing the reset power consumption; 2) the degradation of endurance is mainly due to oxygen escaping from the electrode during cycling; 3) the oxygen migration barrier can be extracted from the retention baking test over a suitable temperature range. *6. 11:30* 20.7 HfOx Based Vertical Resistive Random Access Memory for Cost-Effective 3D Cross-Point Architecture without Cell Selector,* H.-Y. Chen*, S. Yu, B. Gao, P. Huang*, J. Kang*, H.-S.P. Wong, Stanford University, *Peking University Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current (<50?A), switching speed (~50ns), switching endurance (>108 cycles), half-selected disturbance immunity (>109 cycles), retention (>105s @125oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture, and the simulation shows that ~1Mb array without cell selector is achievable. -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Thu Dec 6 13:36:00 2012 From: mtang at stanford.edu (Mary Tang) Date: Thu, 06 Dec 2012 13:36:00 -0800 Subject: Countdown to Shutdown: TWO weeks! Message-ID: <50C10FC0.6060602@stanford.edu> Dear Labmembers -- REMINDER: Lab shuts down at 7 am THURSDAY, Dec. 20. Lab reopens Tuesday, Jan. 8, at 7 am. REMOVE EVERYTHING: from WIP shelves and common storage by shutdown. LAB BINS & LOCKERS: All personal items MUST be removed from lab bins and lockers by shutdown, unless you renew subscriptions (new policy, below). Contact mbaran at snf.stanford.edu or mahnaz at snf.stanford.edu to get your bin or locker tagged. Bins or lockers without tags will be emptied at shutdown. Be aware that SNF is not responsible for valuables left during shutdown. NEW BIN & LOCKER POLICY: Bin/locker fees will be charged when assigned, for rental through Dec. 2013. So, in January, it will be 12 months of fees (e.g., $120 for a medium sized bin, plus overhead.) In March, 9 months. The goal is to simplify billing and ensure inactive bins/lockers don't accumulate by encouraging annual cleanup. Any questions,contact Aubrey Martinez (aubreym at snf) Thanks for your attention -- Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From clchang6 at stanford.edu Thu Dec 6 15:06:24 2012 From: clchang6 at stanford.edu (Chienliu Chang) Date: Thu, 6 Dec 2012 15:06:24 -0800 Subject: Company for placing solder balls Message-ID: Dear Lab members, Good afternoon. I am looking for a company for placing solder balls like the picture as attached. If you have any information about this kind of company, please let me know. Thank you very much. Best regards, Chienliu ------------------------------------------------- Chienliu Chang, Ph.D. Room 104 Ginzton Laboratory Center for Nanoscale Science & Engineering Stanford University 348 Via Pueblo, Stanford, CA 94305-4088 Phone: 650-725-2265 Email: clchang6 at stanford.edu clchang6 at ntu.edu.tw ------------------------------------------------- -------------- next part -------------- A non-text attachment was scrubbed... Name: Solder balls in Elvis Lin's paper.JPG Type: image/jpeg Size: 105744 bytes Desc: not available URL: From jimkruger at yahoo.com Fri Dec 7 12:02:26 2012 From: jimkruger at yahoo.com (jim kruger) Date: Fri, 7 Dec 2012 12:02:26 -0800 (PST) Subject: Good results with HD_SiO2 Message-ID: <1354910546.87819.YahooMailNeo@web161001.mail.bf1.yahoo.com> Good results for HD_SiO2. I find that the uniformity and reproducibility of rate and index are all better than 1% I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to better than 1% The key to predicting thickness is adding the 6 seconds of the ?Light? step to the total deposition time. I included data from thickness' 56 nm to 677 nm and from factory and site acceptance as well as depositions logged by ?wslee? and my own 3 depositions. The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the 6 seconds of strike. If interested, I can e-mail my spreadsheet. Please log your results and send me your data for ?HD_SiO2?. Send dry etch, and especially wet etch rates as well. Any one interested in a recipe for lower rate for control of thinner films? ? I predict (10.3 + 6) seconds for a 450 Ang. film. jimkruger -------------- next part -------------- An HTML attachment was scrubbed... URL: From pradeep.nataraj at gmail.com Fri Dec 7 15:59:29 2012 From: pradeep.nataraj at gmail.com (Pradeep Nataraj) Date: Fri, 7 Dec 2012 15:59:29 -0800 Subject: Good results with HD_SiO2 In-Reply-To: <1354910546.87819.YahooMailNeo@web161001.mail.bf1.yahoo.com> References: <1354910546.87819.YahooMailNeo@web161001.mail.bf1.yahoo.com> Message-ID: Thanks for that Jim. Also Big thanks to Jim Mcvitte for all the effort installing and bringing up the tool. Attached is the SIMS from Applied Materials, indicating that no metal or other contamination in the chamber. I am pretty surprised given that it is a low temp tool and contaminated tool. Also attached is also the AFM roughness Images for the tool on SiNx and SiOx for 1000A. Enjoy Pradeep On Fri, Dec 7, 2012 at 12:02 PM, jim kruger wrote: > Good results for HD_SiO2. > I find that the uniformity and reproducibility of rate and index are all > better than 1% > > I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to > better than 1% > > The key to predicting thickness is adding the 6 seconds of the ?Light? > step to the total deposition time. > > I included data from thickness' 56 nm to 677 nm and from factory and > site acceptance as well as depositions logged by ?wslee? and my own 3 > depositions. > > The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the > 6 seconds of strike. > > If interested, I can e-mail my spreadsheet. > > Please log your results and send me your data for ?HD_SiO2?. Send dry > etch, and especially wet etch rates as well. > > Any one interested in a recipe for lower rate for control of thinner > films? I predict (10.3 + 6) seconds for a 450 Ang. film. > > jimkruger > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: SIMS results on P samples.jpg Type: image/jpeg Size: 171501 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: icp_sio_90.jpg Type: image/jpeg Size: 123246 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: icp_sinx_90.jpg Type: image/jpeg Size: 127252 bytes Desc: not available URL: From sebastian.j.osterfeld at magarray.com Fri Dec 7 19:10:16 2012 From: sebastian.j.osterfeld at magarray.com (Sebastian J. Osterfeld) Date: Fri, 7 Dec 2012 19:10:16 -0800 (PST) Subject: Good results with HD_SiO2 In-Reply-To: <1354910546.87819.YahooMailNeo@web161001.mail.bf1.yahoo.com> Message-ID: <1302017646.13150597.1354936216215.JavaMail.root@stanford.edu> Hi Jim, What is the wafer temperature during the SiO2 deposition? Thanks! Sebastian ----- Original Message ----- > From: "jim kruger" > To: HD-pcvd at SNF.stanford.edu, labmembers at snf.stanford.edu > Cc: "Douglas Tham" > Sent: Friday, December 7, 2012 12:02:26 PM > Subject: Good results with HD_SiO2 > Good results for HD_SiO2. > I find that the uniformity and reproducibility of rate and index are > all better than 1% > I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to > better than 1% > The key to predicting thickness is adding the 6 seconds of the > ?Light? step to the total deposition time. > I included data from thickness' 56 nm to 677 nm and from factory and > site acceptance as well as depositions logged by ?wslee? and my own > 3 depositions. > The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for > the 6 seconds of strike. > If interested, I can e-mail my spreadsheet. > Please log your results and send me your data for ?HD_SiO2?. Send dry > etch, and especially wet etch rates as well. > Any one interested in a recipe for lower rate for control of thinner > films? I predict (10.3 + 6) seconds for a 450 Ang. film. > jimkruger -------------- next part -------------- An HTML attachment was scrubbed... URL: From jimkruger at yahoo.com Fri Dec 7 19:20:13 2012 From: jimkruger at yahoo.com (jim kruger) Date: Fri, 7 Dec 2012 19:20:13 -0800 (PST) Subject: Good results with HD_SiO2 In-Reply-To: <1302017646.13150597.1354936216215.JavaMail.root@stanford.edu> References: <1354910546.87819.YahooMailNeo@web161001.mail.bf1.yahoo.com> <1302017646.13150597.1354936216215.JavaMail.root@stanford.edu> Message-ID: <1354936813.88713.YahooMailNeo@web161005.mail.bf1.yahoo.com> The nominal chuck temperature is 90C, wafer believed less than 100C. The wafer is RF Biased to give some ion bombardment during deposition. jim ________________________________ From: Sebastian J. Osterfeld To: jim kruger Cc: Douglas Tham ; HD-pcvd at SNF.stanford.edu; labmembers at snf.stanford.edu Sent: Friday, December 7, 2012 7:10 PM Subject: Re: Good results with HD_SiO2 Hi Jim, What is the wafer temperature during the SiO2 deposition? Thanks! Sebastian ________________________________ From: "jim kruger" >To: HD-pcvd at SNF.stanford.edu, labmembers at snf.stanford.edu >Cc: "Douglas Tham" >Sent: Friday, December 7, 2012 12:02:26 PM >Subject: Good results with HD_SiO2 > > >Good results for HD_SiO2. >I find that the uniformity and reproducibility of rate and index are all better than 1% > > >I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to better than 1% > > >The key to predicting thickness is adding the 6 seconds of the ?Light? step to the total deposition time. > > >I included data from thickness' 56 nm to 677 nm and from factory and site acceptance as well as depositions logged by ?wslee? and my own 3 depositions. > > >The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the 6 seconds of strike. > > >If interested, I can e-mail my spreadsheet. > > >Please log your results and send me your data for ?HD_SiO2?. Send dry etch, and especially wet etch rates as well. > > >Any one interested in a recipe for lower rate for control of thinner films? ? I predict (10.3 + 6) seconds for a 450 Ang. film. > > >jimkruger -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Mon Dec 10 09:53:43 2012 From: mtang at stanford.edu (Mary Tang) Date: Mon, 10 Dec 2012 09:53:43 -0800 Subject: Labmembers' Meeting, 10 am Thursday, 12/13 Message-ID: <50C621A7.4040508@stanford.edu> Greetings labmembers -- There will be a Labmembers' meeting held this Thursday, Dec. 13, at 10 am in the AllenX Auditorium. The agenda includes (though subject to change): 1. Opening remarks: Overview, intro to new staff/org structure -- John Bumgarner 2. Financials and Badger Rollout: John B, Aubrey Martinez 3. New Tool Installation Update: Ed Myers 4. Clean Room Ops: Brett Huff 5. Renovation/Renovation II and Labmember Survey Summary: Mary Tang 6. Closing remarks: John B Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From mbaran at stanford.edu Mon Dec 10 11:58:22 2012 From: mbaran at stanford.edu (Maureen Baran) Date: Mon, 10 Dec 2012 11:58:22 -0800 (PST) Subject: Holiday Party - Tuesday, December 18th from 1:00 to 3:00 Message-ID: <003a01cdd710$b2bcf930$1836eb90$@stanford.edu> MARK YOUR CALENDAR!!! Dear All, We are planning a wonderful Holiday party, Tuesday, December 18th from 1:00 to 3:00. Please plan accordingly and give yourself some well-deserved time to enjoy a cup of cheer and more with your fellow Allen Building Dwellers / SNF Lab Members to reminisce about 2012 or your holiday plans. Maureen -------------- next part -------------- An HTML attachment was scrubbed... URL: From mcvittie at stanford.edu Mon Dec 10 15:40:33 2012 From: mcvittie at stanford.edu (Jim McVittie) Date: Mon, 10 Dec 2012 15:40:33 -0800 (PST) Subject: Good results with HD_SiO2 In-Reply-To: <1354936813.88713.YahooMailNeo@web161005.mail.bf1.yahoo.com> Message-ID: <1842901353.15016914.1355182833586.JavaMail.root@stanford.edu> Jim, Today, I measured the peak wafer temperature for a 3 min HDP nitride run using the temperature label method, which we commonly use in the etch systems. The peak temperature is > 107C but < 121C. Remember that the chuck temperature is set to 90C. The heating is from ions coming from the ICP plasma which is running at 1000w. I expect the oxide process to reach a similar peak temperature. I will measure the oxide case later in the wk. Jim ----- Original Message ----- From: "jim kruger" To: "Sebastian J. Osterfeld" Cc: "Douglas Tham" , HD-pcvd at SNF.stanford.edu, labmembers at snf.stanford.edu Sent: Friday, December 7, 2012 7:20:13 PM Subject: Re: Good results with HD_SiO2 The nominal chuck temperature is 90C, wafer believed less than 100C. The wafer is RF Biased to give some ion bombardment during deposition. jim From: Sebastian J. Osterfeld To: jim kruger Cc: Douglas Tham ; HD-pcvd at SNF.stanford.edu; labmembers at snf.stanford.edu Sent: Friday, December 7, 2012 7:10 PM Subject: Re: Good results with HD_SiO2 Hi Jim, What is the wafer temperature during the SiO2 deposition? Thanks! Sebastian From: "jim kruger" To: HD-pcvd at SNF.stanford.edu, labmembers at snf.stanford.edu Cc: "Douglas Tham" Sent: Friday, December 7, 2012 12:02:26 PM Subject: Good results with HD_SiO2 Good results for HD_SiO2. I find that the uniformity and reproducibility of rate and index are all better than 1% I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to better than 1% The key to predicting thickness is adding the 6 seconds of the ?Light? step to the total deposition time. I included data from thickness' 56 nm to 677 nm and from factory and site acceptance as well as depositions logged by ?wslee? and my own 3 depositions. The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the 6 seconds of strike. If interested, I can e-mail my spreadsheet. Please log your results and send me your data for ?HD_SiO2?. Send dry etch, and especially wet etch rates as well. Any one interested in a recipe for lower rate for control of thinner films? I predict (10.3 + 6) seconds for a 450 Ang. film. jimkruger From karthikb at stanford.edu Tue Dec 11 02:00:51 2012 From: karthikb at stanford.edu (Karthik Balakrishnan) Date: Tue, 11 Dec 2012 02:00:51 -0800 Subject: Vendor suggestion for fired ceramic PCB Message-ID: Dear Lab members, I am looking for a vendor that has the ability to make a two layer PCB on fired ceramic. The few I've talked to today use a ceramic-PTFE laminate but that won't work for my application. Does anyone have any recommendations? Thanks, Karthik --------------------------- Karthik Balakrishnan karthikb at stanford.edu PhD Candidate, Stanford University Department of Aeronautics and Astronautics Hansen Experimental Physics Labs 452 Lomita Mall Room 223 Stanford, California 94305 From mtang at stanford.edu Tue Dec 11 06:09:14 2012 From: mtang at stanford.edu (Mary Tang) Date: Tue, 11 Dec 2012 06:09:14 -0800 Subject: Shutdown Countdown is 8 Days: Remember YOUR LAB BIN! Message-ID: <50C73E8A.1040503@stanford.edu> Dear labmembers -- Shutdown in EIGHT days (7 am Thurs, 12/20.) Your LAB BIN WILL BE REMOVED unless you inform staff! (See http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:5421:201212:ldjpkjnagmdabiecmjca) Your SNF Staff From mbaran at stanford.edu Tue Dec 11 11:26:30 2012 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 11 Dec 2012 11:26:30 -0800 (PST) Subject: SNF Badger Conversion Instructions and December Timeline and More Message-ID: <007301cdd7d5$6220b910$26622b30$@stanford.edu> 2nd Notice - Please make every effort to get your application done. Dear SNF Lab Members: As most of you know SNF is in the process of converting from the Coral application to Badger Lab Management Software. Members will use Coral until the start of the holiday break and use Badger after the break. Reservations for after the break can be made in Badger with the usual reservation horizons. Many members already have Badger accounts and know that the look and feel of Badger is similar to Coral. New Badger users will have no trouble performing all of their normal functions. Our hope is to make this transition as simple as possible. It is; however, critical that all members read the information at the website below and move quickly to follow the instructions. https://www.stanford.edu/group/snf/Badger/SNF-Conversion.html Important Dates - 12-14 Final day to complete your application and verify your data in Coral and Badger. 12-21 Lab Closes - Coral use ends. 1-8 Lab Reopens - Badger is used over the break for reservations starting on the 8th. Regards, The SNF Conversion Team -------------- next part -------------- An HTML attachment was scrubbed... URL: From ofaolain at stanford.edu Wed Dec 12 11:26:57 2012 From: ofaolain at stanford.edu (Liam O'Faolain) Date: Wed, 12 Dec 2012 11:26:57 -0800 Subject: Silicon cleaving Message-ID: <50C8DA81.2070707@stanford.edu> Dear Labmembers, I have recently learned about this system- https://latticegear.com/store/cleaving-hardware/latticeax-with-eagle-eye-camera/. This appears to be a very precise means of cleaving silicon and potentially very useful to many of us. You may find a video of it in operaton here: http://www.youtube.com/watch?v=L0RXW8fVn4Q&feature=plcp A sales representative from LatticeGear is planning to give me a demonstration of the system in the middle of January. If you are interested in attending, please let me know. Yours, Liam -- Dr. William Whelan-Curtin (Liam O'Faolain) Ginzton Laboratory, Nano Building 348 Via Pueblo Mall, Stanford CA 94305, USA. http://www.nanophotonics.eu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Wed Dec 12 11:43:04 2012 From: mtang at stanford.edu (Mary Tang) Date: Wed, 12 Dec 2012 11:43:04 -0800 Subject: Labmembers' Mtg - New Date: 12/17/12 Message-ID: <50C8DE48.2090508@stanford.edu> Dear Labmembers -- The Labmembers' meeting has been postponed to Monday, Dec. 17. It will be at 10 am in the AllenX Auditorium. The agenda will be as follows: Intro/Overview: John Bumgarner Clean Room Ops: Brett Huff Epi update: Maurice New Etcher Installation Update: Ed Myers Renovation 2: Mary Tang Labmember Survey Summary: Mary Tang Badger Rollout: Michael Bell Financials: Aubrey Martinez Closing: John B ** Slide 2 -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From pease at cis.stanford.edu Wed Dec 12 11:55:09 2012 From: pease at cis.stanford.edu (Roger Fabian Pease) Date: Wed, 12 Dec 2012 11:55:09 -0800 Subject: Silicon cleaving In-Reply-To: <50C8DA81.2070707@stanford.edu> References: <50C8DA81.2070707@stanford.edu> Message-ID: <2B62158C-26A0-4DD4-B6F3-F693DA9222C0@cis.stanford.edu> Emma Chisit? fp On Dec 12, 2012, at 11:26 AM, Liam O'Faolain wrote: > Dear Labmembers, > > I have recently learned about this system- https://latticegear.com/store/cleaving-hardware/latticeax-with-eagle-eye-camera/. This appears to be a very precise means of cleaving silicon and potentially very useful to many of us. You may find a video of it in operaton here: http://www.youtube.com/watch?v=L0RXW8fVn4Q&feature=plcp > > A sales representative from LatticeGear is planning to give me a demonstration of the system in the middle of January. If you are interested in attending, please let me know. > > Yours, > Liam > -- > Dr. William Whelan-Curtin (Liam O'Faolain) > Ginzton Laboratory, Nano Building > 348 Via Pueblo Mall, Stanford CA 94305, USA. > http://www.nanophotonics.eu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Thu Dec 13 10:16:08 2012 From: mtang at stanford.edu (Mary Tang) Date: Thu, 13 Dec 2012 10:16:08 -0800 Subject: Shutdown Countdown: One week! Message-ID: <50CA1B68.3090301@stanford.edu> //Dear Labmembers: Shutdown in ONE WEEK (7 am Thurs, 12/20.) - Your LAB BIN WILL BE REMOVED unless you inform staff! (See http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:5421:201212:ldjpkjnagmdabiecmjca) - Tomorrow is the deadline for setting up new Badger accounts to ensure uninterrupted SNF access. (See http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:5432:201212:pcmggcgaalobimlandbm) Thanks for your attention -- Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From pradeep.nataraj at gmail.com Thu Dec 13 12:10:15 2012 From: pradeep.nataraj at gmail.com (Pradeep Nataraj) Date: Thu, 13 Dec 2012 12:10:15 -0800 Subject: Badger VPN Issues Message-ID: Michaell, I have tired more than many times to get the VPN going, but no luck! My account works fine, when I am in Stanford network. I have talked many users they have the same issues. I am not going to local coffee house to reserve my tool time. This needs to be fixed, before lab starts using badger next year. Thank you for your attention. Pradeep On Sun, Dec 2, 2012 at 6:07 PM, Michael Bell wrote: > Pradeep,**** > > As a current user of Badger I?m sure you?ve been relieved to see that much > of the look and feel of the application is identical to that of Coral and > that there are a number of enhancements that benefit members and staff > alike. In addition to the presentations a couple of months ago, more > information on the conversion specifics will be available shortly. Rest > assured that every effort is being made to make the transition as painless > as possible. **** > > It is true that Badger, like so many software resources at Stanford and > elsewhere, restricts offsite access. Stanford does supply a VPN client that > enables offsite use of the application in most cases. I understand that > your employer has a particularly restrictive policy concerning this. I can > certainly appreciate their concerns for the security of mission critical > resources and would only add that, firewalls, data encryption and > increasingly complex authentication strategies are a sometimes annoying, > but inevitable consequence of the need for data and application security in > the face of sophisticated threats. I have used the Stanford VPN > successfully for years and have found it to be robust and reliable. I?m > hopeful that most members, like myself, will find that offsite access from > home, work or the local caf? will not be an issue. **** > > The good news on multiple accounts is that Badger can support > functionality identical to that of Coral. We will have more information on > this and other issues in the very near future. Again, we are committed to > making the conversion to Badger as seamless as possible and expect most > members to find that the conversion will make the scheduling and use of > equipment in Stanford?s shared labs more convenient.**** > > Regards,**** > > Michael Bell**** > > ** ** > -------------- next part -------------- An HTML attachment was scrubbed... URL: From cfchiang at stanford.edu Thu Dec 13 13:21:14 2012 From: cfchiang at stanford.edu (Chia-Fang Chiang) Date: Thu, 13 Dec 2012 13:21:14 -0800 (PST) Subject: [Reminder] PhD Defense Announcement: Chia-Fang Chiang Tomorrow 10am, Hartley conference center In-Reply-To: <1940164915.11155763.1354781190410.JavaMail.root@stanford.edu> Message-ID: <227283869.18023597.1355433674040.JavaMail.root@stanford.edu> Stanford University Ph.D. Oral Examination ? Dept. of Mechanical Engineering Title: Micromachined Temperature Compensated Pressure Sensor Implemented Using a Multi-Sensor Integration Platform Chia-Fang Chiang Advisor: Professor Thomas W. Kenny Date: Friday, December 14, 2012 Time: 10:00 am (refreshments at 9:45 am) Location: Hartley conference center (Mitchell Earth Sciences) - Room 130 Abstract : Micromachined pressure sensors are widely used in our everyday lives: in automobiles they are implemented to monitor tire pressure and detect side crashes; in medical devices they are used to track blood pressure in the brain; and in navigation they are utilized to determine altitude and assist global positioning system (GPS) receivers. While the requirements for a pressure sensor vary depending upon the specific application, a common requirement is accurate sensing over a wide operating temperature range (-40 ? 125 ?C). I will begin by introducing our capacitive pressure sensor design and demonstrating how it outperforms a piezoresistive pressure sensor with respect to temperature insensitivity. To further reduce temperature dependence, a high resolution resonant thermometer has been cofabricated with the capacitive pressure sensor, enabling the tracking of temperature fluctuations on the die and correction of the associated pressure error. In the second half of the talk, I will discuss our development of a resonant pressure sensor. This is motivated by the emerging demand of altimeters which require high resolution (10Pa/meter). As the design is coupled to the die strain, the accuracy of the resonant pressure sensors is strongly influenced by errors induced by both temperature and package stress. We address this limitation with a multiple sensor solution where temperature and strain sensors are cofabricated to reduce the pressure sensor?s temperature and package stress dependence, thus improving accuracy. Throughout the talk, I will discuss the process flows enabling the fabrication of such structures. Key developments include time insensitive vapor etching of silicon dioxide with hydrofluoric acid to release structures as well as the fabrication of structures that can be driven and sensed in both in-plane (x,y) and out-of-plane (z) directions on either bulk silicon or SOI wafer substrates. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Hartley.jpg Type: image/jpeg Size: 291531 bytes Desc: not available URL: From mtang at stanford.edu Mon Dec 17 08:40:31 2012 From: mtang at stanford.edu (Mary Tang) Date: Mon, 17 Dec 2012 08:40:31 -0800 Subject: Reminder: Labmembers' Mtg Today, 10 am in the Auditorium Message-ID: <50CF4AFF.9000709@stanford.edu> Dear Labmembers -- The Labmembers' meeting is today, Monday, Dec. 17. It will be at 10 am in the AllenX Auditorium. The agenda will be as follows: Intro/Overview: John Bumgarner Clean Room Ops: Brett Huff Epi update: Maurice New Etcher Installation Update: Ed Myers Renovation 2: Mary Tang Labmember Survey Summary: Mary Tang Badger Rollout: Michael Bell Financials: Aubrey Martinez Closing: John B -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From ben.jian at arrayedfiberoptics.com Mon Dec 17 12:14:06 2012 From: ben.jian at arrayedfiberoptics.com (Ben Jian) Date: Mon, 17 Dec 2012 12:14:06 -0800 Subject: silicon wet etching question Message-ID: <50CF7D0E.2060706@arrayedfiberoptics.com> Dear Labmembers, I have a question for you on silicon wet etching. I would like to create an array of slightly tilted ramp surfaces in silicon. The tilted surfaces are 50 um by 50 um with a bottom surface that is tilted by 3 degree from wafer surface, so that one side has a depth of 2.5 um and the other side has a depth of zero. The small surface should be optically smooth for optical purposes. I wonder if this can be done simply by patterning and wet etching silicon using KOH etch with a silicon wafer that is cut 3 degree off (111) orientation. It appears to be an easy task to do, since the starting surface is so close to the final surface (only etch down 2.5 um on one side of the ramp). But I have been warned that it may not be easy to do. Has anyone done this before? Do you think this approach would work? Would the final surface be optical quality, or the ramped surface might have a lot of steps? Thanks. Merry Christmas! Ben From mtang at stanford.edu Mon Dec 17 14:36:39 2012 From: mtang at stanford.edu (Mary Tang) Date: Mon, 17 Dec 2012 14:36:39 -0800 Subject: SNF LAB BINS WILL BE EMPTIED!!! Message-ID: <50CF9E77.3090402@stanford.edu> Dear labmembers -- SNF lab bins WILL BE EMPTIED starting on shutdown, Thursday at 7 am. If you want to keep your bins and items in your bins over the shutdown, you will need to contact Maureen Baran (mbaran at snf) or Aubrey (aubreym at stanford.edu) about renewing your subscription for the year. Any bins which do not have active subscriptions WILL BE EMPTIED by staff. Your SNF staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu From jimkruger at yahoo.com Tue Dec 18 09:04:11 2012 From: jimkruger at yahoo.com (jim kruger) Date: Tue, 18 Dec 2012 09:04:11 -0800 (PST) Subject: Continuing good HD oxide, even across a chamber clean Message-ID: <1355850251.89055.YahooMailNeo@web161002.mail.bf1.yahoo.com> Recipe "HDP-SiO2" We ran 6 wafers targeting 5000 A, 2 before a chamber plasma clean, 4 after.? Measurements this run were 55 pt Woollam. The dep rate and uniformity continue to be ~1%.? The current dep rate estimate is 27.66 A/sec, consistent with previous values of 27.72 and 27.58.? Remember to include the 6 sec of "strike" in the rate calculations The 1st wafer after the clean was 0.68% thicker than the averages (= 2 sigma of wafer avgs, nearly a significant difference). Those few interested in this spreadsheet, please ask. Douglas Tham participated in the depositions and measurements. Thanks to Jim McVittie, Nancy and Elmer, and to SNF for a marvelous new tool. Also to Ed Myers for the Woollam, making these measurements possible. jim -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbaran at stanford.edu Tue Dec 18 09:07:17 2012 From: mbaran at stanford.edu (Maureen Baran) Date: Tue, 18 Dec 2012 09:07:17 -0800 (PST) Subject: Today's the Day - Winter (Holiday) Party from 1:00 to 3:00P on the 1st floor of the Allen Building Message-ID: <008501cddd42$2a215520$7e63ff60$@stanford.edu> Dear All, Today is our Winter (Holiday) party from 1:00P to 3:00P. Please make time in your busy schedule to come down and have a drink (soda or water - you decide) with your co-workers / co lab members. The fun begins on the first floor of the Allen building next to the Litho (yellow) area of the lab at 1:00P. Thank you, Maureen From: Maureen Baran [mailto:mbaran at stanford.edu] Sent: Monday, December 10, 2012 11:58 AM To: cis-building at cis.stanford.edu; labmembers at snf.stanford.edu Subject: Holiday Party - Tuesday, December 18th from 1:00 to 3:00 Importance: High MARK YOUR CALENDAR!!! Dear All, We are planning a wonderful Holiday party, Tuesday, December 18th from 1:00 to 3:00. Please plan accordingly and give yourself some well-deserved time to enjoy a cup of cheer and more with your fellow Allen Building Dwellers / SNF Lab Members to reminisce about 2012 or your holiday plans. Maureen -------------- next part -------------- An HTML attachment was scrubbed... URL: From jrshakya at stanford.edu Tue Dec 18 10:37:31 2012 From: jrshakya at stanford.edu (Jyotindra Shakya) Date: Tue, 18 Dec 2012 10:37:31 -0800 (PST) Subject: Sloped Via Etch Message-ID: <806645943.3096521.1355855851614.JavaMail.root@stanford.edu> Hi All, Before we go on vacation, I just wanted to ask if anyone had measured Step Profile for O2, CHF3 Oxide Etch on mrc? I need to have sloped Via Etch for contaminated process. Because next step is evaporative dep for lift off. Any other suggestions would also be helpful. -Jyotindra From wangss at stanford.edu Wed Dec 19 15:28:09 2012 From: wangss at stanford.edu (Shasha Wang) Date: Wed, 19 Dec 2012 15:28:09 -0800 (PST) Subject: MEMS engineer opening in Northern Europe In-Reply-To: <1241201470.4109433.1355959590137.JavaMail.root@stanford.edu> Message-ID: <152486017.4110032.1355959689074.JavaMail.root@stanford.edu> Dear Labmembers, Fairchild Semiconductor has two positions opening up for a MEMS foundry Engineer and MEMS Process Technician (or Jr. Engineer), to work in a fab in Northern Europe. The positions would require spending ~75% time in Northern Europe. Please let me know if you are interested. Shasha -------------- next part -------------- A non-text attachment was scrubbed... Name: Job_Requistions_Rev1_for_External.pptx Type: application/vnd.openxmlformats-officedocument.presentationml.presentation Size: 292690 bytes Desc: not available URL: From mtang at stanford.edu Thu Dec 20 07:55:26 2012 From: mtang at stanford.edu (Mary Tang) Date: Thu, 20 Dec 2012 07:55:26 -0800 Subject: SNF: Shut Down for Winter Closure Message-ID: <50D334EE.8020900@stanford.edu> Dear Labmembers -- SNF is officially closed for business. Doors reopen on Tuesday, Jan. 8 at 7 am. Happy holidays and see you next year! Your SNF Staff -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Room 136, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu