From kamins at stanford.edu  Tue Jan  3 12:10:30 2012
From: kamins at stanford.edu (Ted Kamins)
Date: Tue, 3 Jan 2012 12:10:30 -0800 (PST)
Subject: CVD seminars during Winter Quarter
In-Reply-To: <1178978135.903633.1323747840425.JavaMail.root@zm07.stanford.edu>
Message-ID: <933077721.178407.1325621430841.JavaMail.root@zm07.stanford.edu>


During the Winter Quarter on Tuesdays at 1:30 pm (except for February 21), I plan to give a series of informal talks on CVD - including epi.  The talks will be based on fairly old material, but might provide some useful background for those using or interested in CVD.

The first talk will be on Tuesday, January 10, starting at 1:30 pm, in Allen - 338X.

A (perhaps somewhat overly ambitious) outline based on a previous short course is attached.

Ted
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From edmyers at stanford.edu  Thu Jan 12 13:26:28 2012
From: edmyers at stanford.edu (Ed Myers)
Date: Thu, 12 Jan 2012 13:26:28 -0800
Subject: Fwd: J.A. Woollam WVASE32 Short Course
In-Reply-To: <4F0F457A.4070103@jawoollam.com>
References: <4F0F457A.4070103@jawoollam.com>
Message-ID: <4F0F5004.20101@stanford.edu>

Please contact Veronica Cockerill at JA Woollam if you are interested in 
attending.

-------- Original Message --------
Subject: 	J.A. Woollam WVASE32 Short Course
Date: 	Thu, 12 Jan 2012 14:41:30 -0600
From: 	Veronica Cockerill <vcockerill at jawoollam.com>
To: 	WoollamMailList at jawoollam.com



Dear J.A. Woollam Customers,

We would like to invite those of you who use our WVASE32 software to the 
next WVASE32 Data Analysis Fundamentals Short Course. It will be held 
*March 6-9, 2012* at the University of North Carolina Charlotte. I have 
attached a course description and registration form. If you would like 
to attend, please fill out the registration form completely and fax or 
email to me by*February 24, 2012.* Once I receive your registration 
form, I will send a confirmation email.

This course will focus on data analysis methods for spectroscopic 
ellipsometry, using WVASE32 software, with a significant amount of 
"hands-on" computer time. For this reason, participants should be 
familiar with WVASE32 software.

*NOTE:* Many of you use our other data analysis software, CompleteEASE. 
A course dedicated to WVASE32 will not be of benefit to you if you use 
CompleteEASE. They are two completely different programs. The next 
CompleteEASE short course has not been scheduled yet. Once it is, I will 
notify you of that course. Thank you for your patience.

If you have any questions, please let me know.

Best regards,
Veronica
-- 

*******************************
Veronica Cockerill
Marketing Coordinator
J. A. Woollam Co., Inc.
645 M Street, Suite 102
Lincoln, NE 68508
_vcockerill at jawoollam.com
_Phone: (402)477-7501 x101
Fax: (402)477-8214
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From artitw at stanford.edu  Thu Jan 12 14:12:13 2012
From: artitw at stanford.edu (Artit Wangperawong)
Date: Thu, 12 Jan 2012 14:12:13 -0800
Subject: NNIN computing facility
In-Reply-To: <2059256212.67328.1326399997339.JavaMail.root@zm04.stanford.edu>
References: <1317171775.67193.1326399810345.JavaMail.root@zm04.stanford.edu>
	<2059256212.67328.1326399997339.JavaMail.root@zm04.stanford.edu>
Message-ID: <CAOYkFzbfAKZ4JxKP=wPqgzv36E3aKR_Re0uGtt7S6xeRrDkTeA@mail.gmail.com>

All

This is a great resource. please contact Zhiyong for more info.

Art

---------- Forwarded message ----------
From: Zhiyong Zhang
Date: Thursday, January 12, 2012
Subject: NNIN computing facility
To: Artit Wangperawong <artitw at stanford.edu>


Artit,

Stanford is one of the sites of NNIN with computing capabilities. NNIN
provides facilities for academic and industrial users. We here at Stanford
have a cluster with 512 cores and a large range of software packages,
including various ab inito packages such as QMC and various DFT packages.
Here is some simple description of the facility at Stanford,
http://www.stanford.edu/group/nnin-computing/ and at other sites which have
the computing facilities, http://www.nnin.org/nnin_compsim.html. You can
also install your own software for your simulations and use the cluster for
development purposes.

If you need to access the cluster for your simulations I will be happy to
set it up for you. Also if you know of anybody who could benefit from using
the cluster, please feel free to pass the word to them also.

Best,

Zhiyong
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From xixie54 at stanford.edu  Sat Jan 14 18:19:18 2012
From: xixie54 at stanford.edu (Xi Xie)
Date: Sat, 14 Jan 2012 18:19:18 -0800 (PST)
Subject: transparent conductive substrate
Message-ID: <1395370170.483711.1326593958426.JavaMail.root@zm06.stanford.edu>

Hi All,
I need a transparent conductive substrate/film/cable/tape, something like Si wafer or Copper tape but need to be transparent and have good conductivity. Anyone have any idea anything like that and I can readily buy?
Also I try to deposite Au on glass slide but the conductivity is low. Any one have better idea of how to do that? Thanks!

Best,
Xi


From cmcg at stanford.edu  Sun Jan 15 17:17:44 2012
From: cmcg at stanford.edu (Chris McGuinness)
Date: Sun, 15 Jan 2012 17:17:44 -0800 (PST)
Subject: LEdit Macro Examples?
In-Reply-To: <1631404302.408227.1326676624823.JavaMail.root@zm10.stanford.edu>
Message-ID: <2022973595.408239.1326676664057.JavaMail.root@zm10.stanford.edu>

Hi all,
I'm trying to use a macro to create a layout in LEdit. I was wondering if anyone had any example macros they could share with me.
Thanks,
Chris


From gunjim at stanford.edu  Mon Jan 16 12:42:31 2012
From: gunjim at stanford.edu (Marika Gunji)
Date: Mon, 16 Jan 2012 12:42:31 -0800
Subject: MSE PhD Dissertation Defense: Marika Gunji (Mon January 30th, 2PM)
Message-ID: <CABpiHTeWmEmS+q1QxY9jfvsNQrdSX2PO_-h5BVTSTxuRBHObFw@mail.gmail.com>

*Nanostructured SiGe and Ge for Future Electronic Devices*



Marika Gunji

Department of Materials Science and Engineering

Advisor: Prof. Paul C. McIntyre

Monday January 30th 2012, 2PM (Refreshments at 1:45PM)

Location: CIS-X 101 Allen Auditorium

(http://cis.stanford.edu/directions/)



As the packing density of silicon (Si) integrated circuits (IC) increases,
scaling requirements are becoming severe. Two approaches are considered to
be effective to continue dimensional scaling. One is to alter the device
layer so that it is a semiconductor other than silicon. Silicon-germanium
(SiGe) and germanium (Ge) are suitable candidates because of their greater
carrier mobilities than Si and their process compatibility with Si
substrates. Another approach is to change the device or circuit structures
so that there is less power consumption and better performance for higher
device packing densities in ICs. Nanoscale structures such as ultra-thin
semiconductor-on-insulators or nanowires can be incorporated in future
transistors.

The presentation will focus initially on synthesis of highly compressively
strained SiGe-on-insulator (SGOI) substrate fabrication. The strain
relaxation mechanisms in highly compressively-strained (0.67% ~ 2.33%
biaxial strain), thin SGOI structures with Ge atomic fraction ranging from
0.18 to 0.81 will be described. SGOI layers (8.7 nm ~ 75 nm thickness) were
fabricated by selective oxidization of Si from compressively strained SiGe
films epitaxially grown on single crystalline Si-on-insulator (SOI) layers.
After high temperature oxidation annealing, ~ 30% of the observed strain
relaxation can be attributed to formation of intrinsic SFs and the
remaining strain relaxation to stress-driven buckling of the SiGe layers.

The presentation will also discuss the path to obtain higher-k dielectrics
on Ge metal-oxide-semiconductor (MOS) devices. To obtain high gate
capacitance density dielectrics on high-mobility Ge channels, one solution
is to interpose a large energy band gap (Eg) insulator with moderate k as
an interface layer between a higher-k dielectric and the channel, since
higher-k dielectrics tend to have small Eg. Al2O3 layers (k ~ 8) can have
stable interfaces with Ge and a large band gap. On the other hand, TiO2 can
achieve a much higher k value (~ 60) when in the rutile crystalline phase,
but its conduction band offset with Ge is less than 1 eV.
TiO2/Al2O3bilayers deposited on Ge(100) by ALD can achieve low
interface trap density
with small leakage current after post-metal forming gas anneal. From
measurements performed on MOS capacitors, the maximum capacitance at a
given frequency increases after the 450 ?C forming gas anneal, indicating
that the dielectric constant of TiO2 increased to ~50 after annealing.
Consistent with these results, TEM datae indicate that the ALD-grown
TiO2phase had predominantly transformed to the rutile phase after
annealing.

In order to measure the channel transfer characteristics for this TiO2 (7.5
nm)/Al2O3 (2.5 nm)/Ge(100) stack, pMOSFETs with long channels (Lg = 2 ? 30
um) were fabricated. The devices show a subthreshold swing of 115 mV/dec
and an on-state current of 60 mA/mm. Measured peak hole mobility reaches
370 cm2/Vs, which suggests the feasibility and potential of TiO2/Al2O3/Ge
gate stacks for high performance MOSFETs.


-- 
---------------------------------
Marika Gunji

PhD Candidate
McIntyre Group
Department of Materials Science and Engineering
Stanford University
E-mail: gunjim at stanford.edu
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From krivoire at stanford.edu  Tue Jan 17 16:44:51 2012
From: krivoire at stanford.edu (Kelley Rivoire)
Date: Tue, 17 Jan 2012 16:44:51 -0800
Subject: EE PhD Oral Examination -- Kelley Rivoire, Fri. Jan 20, 2 pm, Nano 232
Message-ID: <CAL5O44czEuZ3o-EVBsa1tNr9onyFOjXrhZWRK5SHc=5V0ST=qQ@mail.gmail.com>

Stanford University PhD Oral Defense - Department of Electrical Engineering

Title: Nonlinear frequency conversion in III-V semiconductor photonic crystals
Speaker: Kelley Rivoire
Advisor: Jelena Vuckovic

Date: Friday, Jan. 20, 2012
Time: 2 pm (refreshments served at 1:45 pm)
Location: Nano Building, room 232

Abstract:

Nonlinear optical processes provide a physical mechanism for
converting the frequency of light. This allows the generation of
tunable light sources at wavelengths inaccessible with lasers, leading
to a diverse set of applications in fields such as spectroscopy,
sensing, and metrology. To make these processes efficient has
conventionally required relatively exotic materials that are
incompatible with state of the art nanofabrication, resulting in
large-area devices that operate at high optical powers and cannot be
integrated with on-chip optical and electronic circuits.

In this talk, I will show how optical nanocavities, by localizing
light into sub-cubic optical wavelength volumes with long photon
storage times, can greatly enhance the efficiency of nonlinear
frequency conversion processes in III-V semiconductors, while
simultaneously shrinking the device footprint, reducing the operating
power, and providing a scalable on-chip platform. This approach also
enables on-chip quantum frequency conversion interfaces, which are
crucial for the construction of quantum networks. I will first
describe how photonic crystal nanocavities in gallium phosphide can
generate second harmonic radiation with only nanowatts of coupled
optical powers, and efficiency many orders of magnitude greater than
in previous nanoscale devices. We extend this approach to demonstrate
sum-frequency generation in GaP photonic crystal cavities with
multiple cavity modes, as well as broadband upconversion employing
photonic crystal waveguides. I will then discuss how we can integrate
nanocavity-enhanced second harmonic generation with a single quantum
dot to create a single photon source triggered at 300 MHz by a
telecommunication wavelength laser coupled with an external
electro-optic modulator, a simpler and faster configuration than
standard approaches. Finally, I will present the design and
characterization of multi-resonant photonic crystal nanocavities with
large frequency separation that can further reduce the powers of all
of the aforementioned processes.


From jwc at snf.stanford.edu  Tue Jan 17 17:11:24 2012
From: jwc at snf.stanford.edu (James W. Conway)
Date: Tue, 17 Jan 2012 17:11:24 -0800
Subject: Invitation to Raith / Stanford Advanced Lithography Workshop - February
 15, 2012
In-Reply-To: <md5:axiqdY/UgYPPY27I9Y8D6Q==>
References: <md5:axiqdY/UgYPPY27I9Y8D6Q==>
Message-ID: <4F161C3C.8010006@snf.stanford.edu>

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From wslee at stanford.edu  Tue Jan 17 17:19:58 2012
From: wslee at stanford.edu (Scott Lee)
Date: Tue, 17 Jan 2012 17:19:58 -0800
Subject: kapton tape
Message-ID: <CAC8qUHDvZmHX=ArHE8S0F4jntA6yeHpmM775JY6FkcDLPekFUw@mail.gmail.com>

Hi all,

I'm trying to prepare some samples for Tom Carver's lab and need some
kapton tape (probably ~20cm). Does anyone have some I could use? It would
be greatly appreciated.

Thanks,
Scott
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From sergei at scipp.ucsc.edu  Tue Jan 17 19:49:15 2012
From: sergei at scipp.ucsc.edu (Sergei)
Date: Tue, 17 Jan 2012 19:49:15 -0800
Subject: transparent conductive substrate
In-Reply-To: <1395370170.483711.1326593958426.JavaMail.root@zm06.stanford.edu>
References: <1395370170.483711.1326593958426.JavaMail.root@zm06.stanford.edu>
Message-ID: <4F16413B.1040800@scipp.ucsc.edu>

Hi Xi,

We used to buy 4" 1mm thick corner glass wafers coated by ITO for 
several times in the past. The surface resistance was around 20 ohm/sq. 
The vendor was TFD (Thin Film Devices). It's about 5 years passed since 
our last purchase, but they are still in business, apparently:
http://www.tfdinc.com/

Good luck,
Sergei

On 1/14/2012 6:19 PM, Xi Xie wrote:
> Hi All,
> I need a transparent conductive substrate/film/cable/tape, something like Si wafer or Copper tape but need to be transparent and have good conductivity. Anyone have any idea anything like that and I can readily buy?
> Also I try to deposite Au on glass slide but the conductivity is low. Any one have better idea of how to do that? Thanks!
>
> Best,
> Xi



From sgchong at stanford.edu  Wed Jan 18 10:04:30 2012
From: sgchong at stanford.edu (Soogine Chong)
Date: Wed, 18 Jan 2012 10:04:30 -0800 (PST)
Subject: Oral Exam Announcement: Soogine Chong
In-Reply-To: <1906194062.865532.1326909840701.JavaMail.root@zm07.stanford.edu>
Message-ID: <2028951171.865588.1326909870028.JavaMail.root@zm07.stanford.edu>

Stanford University PhD Oral Defense - Department of Electrical Engineering
Title:  Design and Fabrication of Nanoelectromechanical (NEM) Relays Integrated with CMOS
Speaker: Soogine Chong 
Advisor: Professor H.-S. Philip Wong

Date: Friday, January 20, 2012
Time: 10:00 AM (Refreshments served at 9:45 AM)
Location: Paul G. Allen Auditorium (Formerly CISX-101)

Abstract:
  CMOS scaling following Moore?s Law has resulted in a dramatic increase in computing power over the decades.  This was possible by scaling down the CMOS transistors, both in dimensions and voltage.  However, continuous voltage scaling is becoming increasingly difficult because of the increase in subthreshold leakage.  This increase is inevitable with threshold voltage scaling, since the subthreshold slope is theoretically limited to be larger than 60 mV/dec. Nanoelectromechanical (NEM) relays are promising devices to overcome this voltage scaling issue because of their sharp on/off transition characteristics and zero off-state leakage.  However, these devices have long switching times due to their long mechanical delays.  By combining NEM relays with CMOS, it is possible to capitalize on the benefits of each technology.

  In this talk, I propose a novel NEM-CMOS SRAM cell design, followed by an experimental demonstration of the fabrication of NEM relays and their integration with CMOS.  In the proposed NEM-CMOS SRAM cell, NEM relays replace the pull-down NMOS transistors of a conventional six-transistor CMOS SRAM cell.  Simulations show that this hybrid cell has an increased stability and a lower leakage compared to those of a conventional CMOS SRAM cell, without the long mechanical delay of the NEM relay limiting the performance.  Despite these advantages, this circuit has not yet been experimentally demonstrated.  As an initial step toward the demonstration, I first demonstrate the fabrication of NEM relays without CMOS in two different versions: optically patterned scaled-up devices and e-beam patterned scaled-down devices.  With the scaled down devices that have a CMOS-compatible fabrication process, I show an on-chip CMOS inverter successfully driving a NEM relay at the same supply voltage, demonstrating the feasibility of NEM-CMOS integration. 

-- 
Soogine Chong
Stanford University
PhD candidate in Electrical Engineering
e-mail: sgchong at stanford.edu
mobile: +1-650-804-8556



From mtang at stanford.edu  Thu Jan 19 14:49:55 2012
From: mtang at stanford.edu (Mary Tang)
Date: Thu, 19 Jan 2012 14:49:55 -0800
Subject: Venture Clinic, Tues, 1/24 4 pm, Allen 101
Message-ID: <4F189E13.8010507@stanford.edu>

Dear Labmembers -

Interested in starting a company, joining a startup, or just learning more
about starting, funding, and raising money for fledgling technology
companies?  Join VC Clinic where Shahin Farshchi, Principal at Lux Capital
and Gavin McCraley, Of Counsel at law firm Morrison Forrester discuss and
answer questions on mechanics and challenges of creating and growing
technology companies.   Venture Clinic will be held at 4PM Tuesday, January
24th in Allen 101.



-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu



From vijayn at stanford.edu  Sat Jan 21 17:18:46 2012
From: vijayn at stanford.edu (Vijay Kris Narasimhan)
Date: Sat, 21 Jan 2012 17:18:46 -0800 (PST)
Subject: Blue Tape
Message-ID: <1835939252.766421.1327195126654.JavaMail.root@zm02.stanford.edu>

Hi All, 


Does anyone have some blue tape to spare? I can pay you with a modicum of chocolate for your generosity. I would appreciate it if I could have the tape by tomorrow afternoon. 


Cheers, 


Vijay 
(650) 453-8564 
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From phani at stanford.edu  Mon Jan 23 14:09:58 2012
From: phani at stanford.edu (Naga Phani Aetukuri)
Date: Mon, 23 Jan 2012 14:09:58 -0800
Subject: MSE PhD Dissertation Defense: Naga Phani Aetukuri - 6th Feb 3pm CIS-X
 101
In-Reply-To: <4F1DABC6.6030904@stanford.edu>
References: <4F1DABC6.6030904@stanford.edu>
Message-ID: <4F1DDAB6.60809@stanford.edu>

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From mtang at stanford.edu  Tue Jan 24 14:03:54 2012
From: mtang at stanford.edu (Mary Tang)
Date: Tue, 24 Jan 2012 14:03:54 -0800
Subject: Venture Clinic Today, Tuesday, Allen 101, 4 pm
Message-ID: <4F1F2ACA.8050603@stanford.edu>

Dear labmembers --

Thinking about starting up a company while you're waiting for the lab 
renovation to end?  Shahin Farschi (Lux Capital) and Gavin McCraley 
(Morrison Foerster) will be here to host an open discussion and answer 
questions about startups.  The Venture Clinic will start at 4 pm, 
Tuesday, Jan. 24, in Allen 101.

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu



From angiel at stanford.edu  Tue Jan 24 15:06:44 2012
From: angiel at stanford.edu (Angie Lin)
Date: Tue, 24 Jan 2012 15:06:44 -0800
Subject: electrochemical CV measurement
Message-ID: <51FD54E8-B6CC-49F9-BF57-7593B9F69267@stanford.edu>

Hi Labmembers,

Does anyone know where I might be able to do an electrochemical capacitance-voltage profiling measurement?  I'm looking to characterize a III-V film on a heavily doped n-type Si substrate.

Thanks,
Angie

From josep at stanford.edu  Thu Jan 26 13:40:36 2012
From: josep at stanford.edu (Jose Padovani)
Date: Thu, 26 Jan 2012 13:40:36 -0800
Subject: Seminar - Dr. Paul J. Hung, CellASIC Corporation
Message-ID: <69EC4CAD-F06F-433A-84A7-C6BA78EC1543@stanford.edu>

Hi all,

Interesting seminar next Tuesday, January 31, 4-5pm @ Allen 101X Auditorium.

Speaker: Dr. Paul J. Hung, CellASIC Corporation

Topic: Polymer MEMS for Cell-based Microphysiological Platform

Abstract: 
In the post-??genomic era, the next waves of innovation has centered on understanding and utilizing living cells. Physiologic cells are 3D individuals receiving dynamic cues from their perspective microenvironment in order to perform properly; however, current cell-??based studies are dominantly conducted on static 2D format, leaving a large gap between research findings and clinical applications. Polymer Micro-??Electrical-??Mechanical Systems (MEMS) could potentially bridge the gap by providing a more clinically relevant platform to manipulate living cells. Polymer has attractive properties such as biocompatibility, gas permeability, and well-?? understood surface chemistry. MEMS offer the ability to probe into the time and geometric scale similar to those found in the physiologic cellular microenvironments. The established manufacturing infrastructure further reduces the level of resource investment in project development. In this talk, I will first define the roles for each component of Polymer MEMS in creating cell-??based microphysiological platforms. A systematic method to design physiologic-?? relevant cell-??based circuitry will then be presented. Robust manufacturing processes to implement the design on a user-??friendly format will be discussed. A toxicity and metabolism screening platform capable of maintaining metabolic functions of liver cells for over 4 weeks will be used as an example. Finally, potential applications of Polymer MEMS for personalized cell diagnosis and therapy will be mentioned. 

Short Bio:

Paul J Hung co-??founded CellASIC Corporation in 2005 to develop and commercialize advanced cell-??based platforms with Polymer MEMS technology. He received his B.S. degree in Electrical Engineering from National Taiwan University in 1999, and Ph.D. from University of California at Berkeley in Electrical Engineering in 2005. Dr. Hung?s research interests include polymer MEMS, biosensors, and platform engineering with the aims to develop the next generation bio-?? instrumentation, as well as personalized biomedical devices. 


--
Jose Padovani
Graduate Student
Electrical Engineering Department
Stanford University








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From mtang at stanford.edu  Fri Jan 27 18:34:42 2012
From: mtang at stanford.edu (Mary Tang)
Date: Fri, 27 Jan 2012 18:34:42 -0800
Subject: SNF Renovation Update
Message-ID: <4F235EC2.1040709@stanford.edu>

Dear Labmembers --

After 6 weeks of extended shutdown and construction, we are very pleased 
to report that the renovation is going extremely well.  The construction 
crew is knowledgeable, professional, and know our concerns -- they 
worked extra shifts and weekends to help us minimize the shutdown time 
and impact to labmembers' research.  Main construction work is done and 
has passed most of the inspections with the County.

There are, however, still a few inspections outstanding, so until these 
are done, we won't have a definite date as to when the lab will be 
reopened for use. *We will keep everyone posted as we get more 
information*.  Please check out the behind-the-scenes photos of the 
construction, links on the SNF website (see News links.)

Your SNF staff

-- 
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA  94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu

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From gunjim at stanford.edu  Sun Jan 29 15:55:48 2012
From: gunjim at stanford.edu (Marika Gunji)
Date: Sun, 29 Jan 2012 15:55:48 -0800
Subject: [Reminder] MSE PhD Dissertation Defense: Marika Gunji (Tomorrow, 2PM)
Message-ID: <CABpiHTfdUDyVGGw0zmoacSOptFnsyes8h5o7Rai1gmisQ+D=Mg@mail.gmail.com>

>  *Nanostructured SiGe and Ge for Future Electronic Devices*
>
>
>
> Marika Gunji
>
> Department of Materials Science and Engineering
>
> Advisor: Prof. Paul C. McIntyre
>
> Monday January 30th 2012, 2PM (Refreshments at 1:45PM)
>
> Location: CIS-X 101 Allen Auditorium
>
> (http://cis.stanford.edu/directions/)
>
>
>
> As the packing density of silicon (Si) integrated circuits (IC) increases,
> scaling requirements are becoming severe. Two approaches are considered to
> be effective to continue dimensional scaling. One is to alter the device
> layer so that it is a semiconductor other than silicon. Silicon-germanium
> (SiGe) and germanium (Ge) are suitable candidates because of their greater
> carrier mobilities than Si and their process compatibility with Si
> substrates. Another approach is to change the device or circuit structures
> so that there is less power consumption and better performance for higher
> device packing densities in ICs. Nanoscale structures such as ultra-thin
> semiconductor-on-insulators or nanowires can be incorporated in future
> transistors.
>
> The presentation will focus initially on synthesis of highly compressively
> strained SiGe-on-insulator (SGOI) substrate fabrication. The strain
> relaxation mechanisms in highly compressively-strained (0.67% ~ 2.33%
> biaxial strain), thin SGOI structures with Ge atomic fraction ranging from
> 0.18 to 0.81 will be described. SGOI layers (8.7 nm ~ 75 nm thickness) were
> fabricated by selective oxidization of Si from compressively strained SiGe
> films epitaxially grown on single crystalline Si-on-insulator (SOI) layers.
> After high temperature oxidation annealing, ~ 30% of the observed strain
> relaxation can be attributed to formation of intrinsic SFs and the
> remaining strain relaxation to stress-driven buckling of the SiGe layers.
>
> The presentation will also discuss the path to obtain higher-k dielectrics
> on Ge metal-oxide-semiconductor (MOS) devices. To obtain high gate
> capacitance density dielectrics on high-mobility Ge channels, one solution
> is to interpose a large energy band gap (Eg) insulator with moderate k as
> an interface layer between a higher-k dielectric and the channel, since
> higher-k dielectrics tend to have small Eg. Al2O3 layers (k ~ 8) can have
> stable interfaces with Ge and a large band gap. On the other hand, TiO2can achieve a much higher k value (~ 60) when in the rutile crystalline
> phase, but its conduction band offset with Ge is less than 1 eV. TiO2/Al2O
> 3 bilayers deposited on Ge(100) by ALD can achieve low interface trap
> density with small leakage current after post-metal forming gas anneal. From
> measurements performed on MOS capacitors, the maximum capacitance at a
> given frequency increases after the 450 ?C forming gas anneal, indicating
> that the dielectric constant of TiO2 increased to ~50 after annealing.
> Consistent with these results, TEM datae indicate that the ALD-grown TiO2phase had predominantly transformed to the rutile phase after annealing.
>
> In order to measure the channel transfer characteristics for this TiO2(7.5 nm)/Al
> 2O3 (2.5 nm)/Ge(100) stack, pMOSFETs with long channels (Lg = 2 ? 30 um)
> were fabricated. The devices show a subthreshold swing of 115 mV/dec and an
> on-state current of 60 mA/mm. Measured peak hole mobility reaches 370 cm2/Vs,
> which suggests the feasibility and potential of TiO2/Al2O3/Ge gate stacks
> for high performance MOSFETs.
>
>
> --
> ---------------------------------
> Marika Gunji
>
> PhD Candidate
> McIntyre Group
> Department of Materials Science and Engineering
> Stanford University
> E-mail: gunjim at stanford.edu
>



-- 
---------------------------------
Marika Gunji

PhD Candidate
McIntyre Group
Department of Materials Science and Engineering
Stanford University
E-mail: gunjim at stanford.edu
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From josep at stanford.edu  Tue Jan 31 15:43:16 2012
From: josep at stanford.edu (Jose Padovani)
Date: Tue, 31 Jan 2012 15:43:16 -0800
Subject: Seminar Reminder: Dr. Paul J. Hung, CellASIC Corporation 4-5pm Allen 101X
Message-ID: <C9E2B5A1-E7CC-4714-B034-5047F3DABB17@stanford.edu>

Hi all,

Interesting seminar next Tuesday, January 31, 4-5pm @ Allen 101X Auditorium.

Speaker: Dr. Paul J. Hung, CellASIC Corporation

Topic: Polymer MEMS for Cell-based Microphysiological Platform

Abstract: 
In the post-??genomic era, the next waves of innovation has centered on understanding and utilizing living cells. Physiologic cells are 3D individuals receiving dynamic cues from their perspective microenvironment in order to perform properly; however, current cell-??based studies are dominantly conducted on static 2D format, leaving a large gap between research findings and clinical applications. Polymer Micro-??Electrical-??Mechanical Systems (MEMS) could potentially bridge the gap by providing a more clinically relevant platform to manipulate living cells. Polymer has attractive properties such as biocompatibility, gas permeability, and well-?? understood surface chemistry. MEMS offer the ability to probe into the time and geometric scale similar to those found in the physiologic cellular microenvironments. The established manufacturing infrastructure further reduces the level of resource investment in project development. In this talk, I will first define the roles for each component of Polymer MEMS in creating cell-??based microphysiological platforms. A systematic method to design physiologic-?? relevant cell-??based circuitry will then be presented. Robust manufacturing processes to implement the design on a user-??friendly format will be discussed. A toxicity and metabolism screening platform capable of maintaining metabolic functions of liver cells for over 4 weeks will be used as an example. Finally, potential applications of Polymer MEMS for personalized cell diagnosis and therapy will be mentioned. 

Short Bio:

Paul J Hung co-??founded CellASIC Corporation in 2005 to develop and commercialize advanced cell-??based platforms with Polymer MEMS technology. He received his B.S. degree in Electrical Engineering from National Taiwan University in 1999, and Ph.D. from University of California at Berkeley in Electrical Engineering in 2005. Dr. Hung?s research interests include polymer MEMS, biosensors, and platform engineering with the aims to develop the next generation bio-?? instrumentation, as well as personalized biomedical devices. 


--
Jose Padovani
Graduate Student
Electrical Engineering Department
Stanford University



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