Oral Exam Announcement: Soogine Chong

Soogine Chong sgchong at stanford.edu
Wed Jan 18 10:04:30 PST 2012


Stanford University PhD Oral Defense - Department of Electrical Engineering
Title:  Design and Fabrication of Nanoelectromechanical (NEM) Relays Integrated with CMOS
Speaker: Soogine Chong 
Advisor: Professor H.-S. Philip Wong

Date: Friday, January 20, 2012
Time: 10:00 AM (Refreshments served at 9:45 AM)
Location: Paul G. Allen Auditorium (Formerly CISX-101)

Abstract:
  CMOS scaling following Moore’s Law has resulted in a dramatic increase in computing power over the decades.  This was possible by scaling down the CMOS transistors, both in dimensions and voltage.  However, continuous voltage scaling is becoming increasingly difficult because of the increase in subthreshold leakage.  This increase is inevitable with threshold voltage scaling, since the subthreshold slope is theoretically limited to be larger than 60 mV/dec. Nanoelectromechanical (NEM) relays are promising devices to overcome this voltage scaling issue because of their sharp on/off transition characteristics and zero off-state leakage.  However, these devices have long switching times due to their long mechanical delays.  By combining NEM relays with CMOS, it is possible to capitalize on the benefits of each technology.

  In this talk, I propose a novel NEM-CMOS SRAM cell design, followed by an experimental demonstration of the fabrication of NEM relays and their integration with CMOS.  In the proposed NEM-CMOS SRAM cell, NEM relays replace the pull-down NMOS transistors of a conventional six-transistor CMOS SRAM cell.  Simulations show that this hybrid cell has an increased stability and a lower leakage compared to those of a conventional CMOS SRAM cell, without the long mechanical delay of the NEM relay limiting the performance.  Despite these advantages, this circuit has not yet been experimentally demonstrated.  As an initial step toward the demonstration, I first demonstrate the fabrication of NEM relays without CMOS in two different versions: optically patterned scaled-up devices and e-beam patterned scaled-down devices.  With the scaled down devices that have a CMOS-compatible fabrication process, I show an on-chip CMOS inverter successfully driving a NEM relay at the same supply voltage, demonstrating the feasibility of NEM-CMOS integration. 

-- 
Soogine Chong
Stanford University
PhD candidate in Electrical Engineering
e-mail: sgchong at stanford.edu
mobile: +1-650-804-8556




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