[Reminder] MSE PhD Dissertation Defense: Marika Gunji (Tomorrow, 2PM)

Marika Gunji gunjim at stanford.edu
Sun Jan 29 15:55:48 PST 2012

>  *Nanostructured SiGe and Ge for Future Electronic Devices*
> Marika Gunji
> Department of Materials Science and Engineering
> Advisor: Prof. Paul C. McIntyre
> Monday January 30th 2012, 2PM (Refreshments at 1:45PM)
> Location: CIS-X 101 Allen Auditorium
> (http://cis.stanford.edu/directions/)
> As the packing density of silicon (Si) integrated circuits (IC) increases,
> scaling requirements are becoming severe. Two approaches are considered to
> be effective to continue dimensional scaling. One is to alter the device
> layer so that it is a semiconductor other than silicon. Silicon-germanium
> (SiGe) and germanium (Ge) are suitable candidates because of their greater
> carrier mobilities than Si and their process compatibility with Si
> substrates. Another approach is to change the device or circuit structures
> so that there is less power consumption and better performance for higher
> device packing densities in ICs. Nanoscale structures such as ultra-thin
> semiconductor-on-insulators or nanowires can be incorporated in future
> transistors.
> The presentation will focus initially on synthesis of highly compressively
> strained SiGe-on-insulator (SGOI) substrate fabrication. The strain
> relaxation mechanisms in highly compressively-strained (0.67% ~ 2.33%
> biaxial strain), thin SGOI structures with Ge atomic fraction ranging from
> 0.18 to 0.81 will be described. SGOI layers (8.7 nm ~ 75 nm thickness) were
> fabricated by selective oxidization of Si from compressively strained SiGe
> films epitaxially grown on single crystalline Si-on-insulator (SOI) layers.
> After high temperature oxidation annealing, ~ 30% of the observed strain
> relaxation can be attributed to formation of intrinsic SFs and the
> remaining strain relaxation to stress-driven buckling of the SiGe layers.
> The presentation will also discuss the path to obtain higher-k dielectrics
> on Ge metal-oxide-semiconductor (MOS) devices. To obtain high gate
> capacitance density dielectrics on high-mobility Ge channels, one solution
> is to interpose a large energy band gap (Eg) insulator with moderate k as
> an interface layer between a higher-k dielectric and the channel, since
> higher-k dielectrics tend to have small Eg. Al2O3 layers (k ~ 8) can have
> stable interfaces with Ge and a large band gap. On the other hand, TiO2can achieve a much higher k value (~ 60) when in the rutile crystalline
> phase, but its conduction band offset with Ge is less than 1 eV. TiO2/Al2O
> 3 bilayers deposited on Ge(100) by ALD can achieve low interface trap
> density with small leakage current after post-metal forming gas anneal. From
> measurements performed on MOS capacitors, the maximum capacitance at a
> given frequency increases after the 450 °C forming gas anneal, indicating
> that the dielectric constant of TiO2 increased to ~50 after annealing.
> Consistent with these results, TEM datae indicate that the ALD-grown TiO2phase had predominantly transformed to the rutile phase after annealing.
> In order to measure the channel transfer characteristics for this TiO2(7.5 nm)/Al
> 2O3 (2.5 nm)/Ge(100) stack, pMOSFETs with long channels (Lg = 2 – 30 um)
> were fabricated. The devices show a subthreshold swing of 115 mV/dec and an
> on-state current of 60 mA/mm. Measured peak hole mobility reaches 370 cm2/Vs,
> which suggests the feasibility and potential of TiO2/Al2O3/Ge gate stacks
> for high performance MOSFETs.
> --
> ---------------------------------
> Marika Gunji
> PhD Candidate
> McIntyre Group
> Department of Materials Science and Engineering
> Stanford University
> E-mail: gunjim at stanford.edu

Marika Gunji

PhD Candidate
McIntyre Group
Department of Materials Science and Engineering
Stanford University
E-mail: gunjim at stanford.edu
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