Oral Exam Announcement: Jiale Liang

Jiale Liang liangjl at stanford.edu
Sun Jun 3 18:16:24 PDT 2012

Stanford University Ph.D. Oral Examination – Department of Electrical Engineering

Title: Phase Change Memory Towards Sub-10nm - Device Structure and Array Analysis
Speaker: Jiale Liang
Advisor: H. -S. Philip Wong

Date: Wednesday, June 6, 2012
Time: 2:00 pm (Refreshments at 1:45pm)
Location: CIS-X Auditorium

Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. Moreover, for memory array implementation, array size limitations from sneak path leakage and wire scaling are severe. A careful co-design between memory device structure and array configuration beyond sub-10nm regime is hence imperative.

In the first part of my presentation, I will explore the scaling limit of PCM cells by demonstrating a fully functional cross-point memory cell using carbon nanotubes (CNTs) as the memory electrode. The use of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of programming current to 1.4 μA, which is two orders of magnitude smaller than the state-of-the-art, and a record-low programming energy to 210 fJ. Measured electrical characteristics validate the advantage of device scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultra-dense PCM array down to 1.8nm node technology.

In the second part of my presentation, I will extend the discussion from a single PCM device to the resistive cross-point memory array. First, the methodology for worst case analysis and the reduced circuit model for cross-point memory arrays are introduced. Using this model, the size limiting factors of cross-point memory arrays without selection devices are analyzed considering both the array data pattern dependence and memory cell parameter dependence. Next, the impact of bit line and word line wire scaling on the write/read margin, energy dissipation, speed and reliability of resistive cross-point memory array are quantitatively examined for wire sizes down to the sub-10nm node. The impending resistivity increase due to wire dimensional scaling results in significantly degraded write and read windows, substantial interconnect energy, increased wire latency and exacerbating reliability. Lastly, the concept of using local back gate (LBG) CNFET as memory electrode, interconnect, and selection device for cross-point memory arrays is proposed. The improvement in the cross-point array performance promises the possibility of an integrated memory-carbon structure for sizes beyond sub-10nm.

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