Lithography of the Future : A technological and economic challenge
saraswat at cis.stanford.edu
Wed Oct 3 08:37:19 PDT 2012
Title : Lithography of the Future : A technological and economic challenge
Date : Oct 3, Wednesday
Place : CIS-X 101, Paul Allen Building
Semiconductor devices scaling has been at the heart of the remarkable progress of the computer industry over the last 40 years, as described by Moore’s Law, and lithography is the engine that drives Moore’s Law relentlessly forward. By reducing the wavelength of light and by employing ever bigger optics, lithographers have managed to deliver scaling solutions that meet the needs of the industry. However, with practical limitations on these approaches coming into play, future advances may have to rely on innovative new approaches not just to deliver feature size scaling, but to control costs that if unchecked, threaten to undermine the financial underpinnings of scaling.
This talk will describe the current state of the art in patterning and will describe the future lithography directions that are currently being researched and developed in industry, both from a technical and an economic perspective.
Sam Sivakumar is an Intel Fellow and director of Lithography in Intel's Portland Technology Development Group in Oregon. He is responsible for the definition, development and deployment of Intel's next generation lithography processes, resolution enhancement techniques and optical proximity correction.
Sivakumar joined Intel in 1990 after graduating in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign and throughout his career with the company has worked in the lithography area on photoresists, patterning equipment and process development. He has contributed to lithography development, characterization and transfer to high-volume manufacturing of every submicron process technology generation at Intel since 1990 and has co-invented industry-leading interconnect patterning techniques for several Intel technology generations.
He has published 23 papers and holds 35 patents on lithography and semiconductor processing.
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