Lucian Shifren (Suvolta) : Rise of depletion CMOS (today)

Aneesh Nainani nainani at stanford.edu
Wed Oct 10 02:44:51 PDT 2012


*Title : Rise of depletion CMOS
*
* Date : Oct 10, Wednesday
Place : CIS-X 101, Paul Allen Building*
*Time : 4:15pm*

*Abstract*

The semiconductor industry is once again approaching a major turning point.
CMOS physical scaling and Moore’s law are ending. New device architectures,
materials and lithography techniques are needed to reignite Moore’s law. In
this talk we will explore where we stand with scaling and Moore’s law and
also discuss two new device architectures (FinFET and DDC) which are
potential candidates for current and future technology nodes.



*Bio*

*Lucian Shifren, PhD*

*Sr. Director, Device Technology*

Dr. Lucian Shifren is senior director of device technology at SuVolta.
Prior to joining SuVolta in 2010, Lucian spent eight years at Intel as a
staff engineer in the Process and Device Modeling Group, where he
concentrated on device architecture and performance issues across a range
of nodes – from 65nm to 15nm.  Amongst his accomplishments, Lucian wrote
the first quantum mechanical self-consistent Monte Carlo simulator with
full scattering terms and was instrumental in discovering the physics
behind PMOS stress gain in MOSFETs. Lucian earned BS, MS and PhD degrees in
Electrical Engineering from Arizona State University and an MBA from
Portland State University.  As an author, Lucian has published over 25
refereed papers and has more than 20 patents pending or issued.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://snf.stanford.edu/pipermail/labmembers/attachments/20121010/ea4595af/attachment.html>


More information about the labmembers mailing list