NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook

Krishna Saraswat saraswat at cis.stanford.edu
Wed Oct 17 10:20:12 PDT 2012


NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook

 
Time : 4:15pm (10/17/2012)
Location : CIS-X 101 
Speaker : Pranav Kalavade 


Abstract 

This talk will start with device basics of FG memory devices, and cover some basic operation of the NAND flash cell. This will be followed by highlighting the scaling challenges, giving examples of solutions that industry has developed along the way. The talk will conclude with some comments about future directions that are being explored in the industry.

Bio
Pranav is a Principle Engineer in the Non-volatile Solutions Group at Intel. His early work was on NOR flash cell on the 90nm node. Later, he was part of the initial technical team leading the Intel-Micron NAND JDP, and has worked on NAND for multiple nodes starting with the 50nm technology, and currently working on 20nm technology. Pranav has served as a panelist of several conferences. He previously served as the Financial and Technical and is currently General Chairman of the IEEE International Memory Workshop. Pranav received his B. Tech (EE) from IIT Bombay, India, M.S. (EE) from Purdue University, and a Ph.D. from Stanford University. Pranav has several publications in technical journals and conferences, and holds 7 patents with several applications that are currently pending.


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