[labmembers] Reminder: Oral Exam for Scott Lee Tomorrow!

Scott Lee wslee at stanford.edu
Thu Feb 14 15:04:42 PST 2013

Department of Electrical Engineering

University PhD Oral Examination

Nanoelectromechanical Relays

for Low Power Digital Systems

Wm. Scott Lee

Research Advisor: Professor Roger Howe

Friday, February 15, 2013 @ 10AM

(Refreshments @ 9:45AM)

Location: Packard Building, Room 202


Field programmable gate arrays (FPGAs) are flexible digital circuits
capable of implementing arbitrary digital logic. This flexibility comes at
a price: a digital function implemented on an FPGA requires more area and
power while operating at a lower speed compared to the same function built
on an application specific integrated circuit (ASIC).  The overhead
required to implement the programmable routing is directly responsible for
much of the discrepancy. By replacing the FPGA pass transistors and SRAM
programming cells with low leakage nanolectromechanical (NEM) relays, this
overhead can be significantly reduced without a reduction in speed. The NEM
relay consists of a released beam, a fixed gate electrode, and a fixed
drain electrode. When the relay is out of contact, an air gap separates the
beam and drain resulting in zero leakage. When the relay moves into
contact, electrical current passes from the drain to the beam.

In this work, we investigate NEM relays as potential FPGA routing elements.
The NEM relays must meet certain metrics with respect to contact
resistance, cycling, and hysteresis to obtain significant benefits for the
FPGA. NEM relays are fabricated and characterized to determine if they meet
these metrics. Design and fabrication techniques are developed to decrease
the contact resistance and achieve better control of the hysteresis window.
These techniques enable three regions of varying stiffness for the spring,
the actuation electrode, and the contact. Contact materials such as
titanium nitride, hafnium diboride, and ruthenium are also explored as a
means of reaching these metrics.
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