mcvittie at snf.stanford.edu
Tue Jul 30 18:07:32 PDT 2002
My feeling now is that several things may be going on with your wafers.
1. The fact that we are not seeing the deposition on the dummy wafer, even at
seems to indicate that there was some chamber contamination or other problem
when you did your first run.
2.The fact that the room temperature GaAs and InP etch rates are normal
indicates that the chamber in probably back to normal.
3. The fact that the 85C InP etch rate is low may indicate that the
temperature at the wafer is not really at 85C. It is possible the position of
the themal couple or a heat path was changed during the repair.
I suggest that you try a run with an increased the temperature setting (+10C)
and that you do a temperature calibration run using the temperature dots. I
believe I have some temperature dots in my cart in the lab. Tonight, after
you finish your increased temperature run, the system will be opened up to
Vijit Sabnis wrote:
> Since it looks like the pquest does not have any major leak
> issues, I recommend opening the machine up for use. At this
> point we will probably learn more by having people try their
> various etches and monitoring the performance and etch rate
> of their process. I suggest that everyone try to be more
> conscientious about writing down the etch rate and any
> other observations in the log book.
> - vijit
> > PQuest: Ramp down turbo and vented chamber. Turn off backing pump,
> > disassemble and cleaned foreline and roughing valve. Varify
> > both foreline and roughing valve if leaking by, I open the
> > slit valve and turn on purge and backfill valve. Monitor
> > foreline pressure and no rise on pressure encounter. Eric and I
> > varifty leak rate on chamber:
> > L/R with foreline and throttle close is @1.4mt per min.
> > L/R with foreline close throttle open is 0.0mt per min
> > L/R with foreline and throttle close, load lock vented
> > is @1.4mt per min.
> > I don't believe there is any significant leak on the
> > chamber.
> > We also cleaned slit valve sealing surface and cycled lifter
> > assy. up and down during leak check to varify that lifter
> > bellow is not leaking.
> > Cesar
> Vijit Sabnis
> vsabnis at snow.stanford.edu
> Stanford University
> Department of Electrical Engineering
> Solid State and Photonics Laboratory
> CISX B113-23
> 650/725-2774 office
> 723-4659 fax
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