RAITH FAQ No 5. Overlay alignment to optical and other EBL system generated features.

James Conway jwc at snf.stanford.edu
Tue Nov 15 09:53:05 PST 2005


I have noted that RAITH users working in Layer to Layer Overlay 
alignment have developed several procedures to perform this overlay 
registration task.

The following is the procedure I am using to align Layer 1 to Layer 2 on 
a structure that previously I had difficulty locating the alignment 
targets due to U and V offsets resulting from the size of the Working 
Area of the Chip's design.  I would appreciate comments from other users 
working in Overlay on their structures, specifically how their method 
differs from this one.

   1. Establish simple  GLOBAL U, V, W alignment to major flat of wafer 
      to adjust angle correction.
   2. Determine the center line of the wafer by taking the absolute
      value of the angle correction values and divide by 2.
   3. Move to the center line of the major flat and align cross hairs to
      the edge of the flat. Adjust this position to be 0 U, -50 mm V per
      std. 100 mm wafer layout.
   4. Establish new GLOBAL U, V, W alignment by locating  patterns or
      marks on the wafer from the previous layer that you know the
      actual U, V position.
      Often you can use the Position List (*. PLS) to obtain the U, V.
      Positions with the exposure module turned off  in the Scan menu
      you can drive to the marks.
      Normally this will just be a slight offset to the simple initial
      GLOBAL U, V, W alignment. Adjust as necessary using the Set Origin
      to Origin Correction Tab.
   5. Switch to LOCAL in the Adjust U, V, W window. Move the stage to
      the position of the first chip you will wish to perform Overlay
      alignment to. This chip should be consider a sacrificial chip as
      it will be exposed repeatedly during the target location and
      alignment routines by the SEM.
   6. Find the First Write Field alignment mark such as the lower left
      chip in the writefield. Position the SEM cross hairs over this
      chip. [READ] the X, Y position into the LOCAL U, V, W window and
      enter the design u, v coordinates into the U, V positions. Check
      off the first check in the dialog box and Press [Adjust].
      ( Alternately, using the GDSII viewer with the design in view, and
      with the title bar highlighted, you can drag into the viewer
      window the green flags from the top menu and these will enter both
      the X, Y and the design u, v positions into the dialog box. 
      Confirm these positions in the SEM view and if necessary adjust
      the X, Y positions by pressing [READ] in the dialog box.  Ensure
      that the U, V coordinates in the dialog box are correct and press
   7. Now located the Second and the Third Write Field Alignment marks
      repeating step 6 -- but do not adjust until all three marks and
      their positions have been entered in to the Adjust U, V, W dialog
      box.  Press [Adjust] to establish your final LOCAL U, V, W
      coordinate system.
   8. Move the Stage back to the actual U, V, W position of the first
      chip, if necessary.  Drag and drop the design into a New Position
      List and enter 0, 0 into the U, V position.  Then press the button
      on the right hand side of the exposure properties box named,
      'Adjust position to match Working Area'  This will establish the
      offsets to the actual center of the chip based on the working area
   9. Matrix Copy the new Local U, V value for the U, V array dimension
      and number of chips written in the previous layer.  (E.G., 10 'U'
      X 10 'V' X 1 mm)
  10. Adjust Brightness and Contrast in the SEM and then process Layer
      63; Manual Write field alignment to test the LOCAL U, V,
      adjustments and you should now be able to easily locate your
      targets.  If not you may wish to increase the size of the scan
      area in the target design for testing.
  11. Process Layer 63 for the initial chip, and if desired Layer 61 for
      subsequent chips along with the Layer you wish to write in Overlay
      turned on in the properties dialog box within the chip in the
      Position List.

  12. If you cannot locate targets in Layer 63 return to the chip design
      window and double check your target positions from the u, v
      positions in the design.
      Then double check the array number and dimensions. If you still
      cannot locate the targets acquire an image in the SEM and measure
      the offsets positions carefully and enter then into the New
      positions list carefully and repeat the Layer 63 Write Field
      Alignment. If this still doesn't work see me and I will help you.

        This method has now been tested on two designs over three runs 
and it seems to be working well for me.  Your comments are invited.

James Conway
Stanford Nanofabrication Facility
November 15, 2005

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://snf.stanford.edu/pipermail/raith/attachments/20051115/5b1547b1/attachment.html>

More information about the raith mailing list