Is Raith sample stage tilted ?

James Conway jwc at
Tue Apr 1 19:28:31 PDT 2008

Hello Shinichi Koseki and the RAITH community:

YES -- the standard sample holder does not land perfectly level due to
wear and scratches on the top surface and normal wear to the backside
kinetic mounts. I posted many emails to this effect several months
ago.This sample holder has become very worn from new users and abuse
from clipping additional fixture mounts and sliding wafers and gouges
from tweezer scratches on the soft AL surface.

My measurements last year indicated a total delta WD of between 124 and
174 um moving across a 90 mm distance across a 100 mm wafer clipped to
both clip 2 and clip 4 of the standard sample holder.
In my testing a delta WD of greater than 10 um /mm will result in loss
of resolution for a 100 nm single pixel lines and below. (refer: Origin
Target rings) using the 30 um aperture and 5 mm WD.
The 10 um aperture will show a even more pronounced effect. Please refer
to FAQ notebook NO 3 and 4 to review my measurements.

I mounted a wafer to this assembly yesterday and obtained ~ 0.380 mm
(380 um) total WD across 90 mm. I will repeat this measurement to assure
that I did not clip onto lint free fibers, or had anything on the back
side of my wafer as the magnitude is much larger than expected. I had
just cleaned the mount using a wiper and IPA just before loading.

The std. sample holder design specifications are greater that the +- 50
um that can be pushed up or pulled down from center position of the
piezo leveling post. It was never designed to be leveled using the piezo
post. However if you try to level a wafer you can obtain a suitable
result for most EBL applications. Start out with centered piezo
positions and follow the leveling procedure. My plan to to have this
fixture reconditioned during the July 4th break if I can obtain design
specifications and a blue print. I desire it to be fly cut and lapped to
a very smooth finish. I may also have the kinetic mounts re-machined if

For users whom have a critical focusing need there are two alternatives.:

We recently purchased for ~$15K USD a Universal Sample Holder that has
adjustable kinetic mounts and can be leveled to within 100 nm to 1 um
Silicon and GaAs substrates are much harder than Aluminum. You can make
huge scratches into the polished surface if you are not extremely careful.

For those working on full wafers I also have a full wafer electrostatic
chuck which can also be precisely leveled to with 10 - 180 nm routinely.
This assembly will work for wafers of 75, 100, 125 and 150 mm sizes.
Some training, escorted use for the first five mountings, and my
permission are required to employ this assembly. It too can be totally
wrecked by just a single scratch into the charging surface. Replacement
cost is on the order of $50K Euros. It can be a bit tricky to charge
this assembly up and it will not function for insulating substrates, to
my knowledge.

If you have specific questions please see me during my office hour.

Thank you for your support!

James Conway

PS I would like to personally commend Shinichi Koseki for his
observations on this issue and for his great participation in assisting
the RAITH community. Recently he carefully timed his write sessions and
I have observed them completing their tasking just as I enter the Ebeam
Lab to start my afternoon sessions. This is exactly what being a RAITH
Champion is all about. Thank you Koseki-san!

Shinichi Koseki wrote:
> Hi James,
> I have a question.
> It looks for me that the Raith sample stage is tilted.
> Please see the attached SEM images of my grating. (which I made last
> week)
> (~200nm grating period and 50/50 duty cycle, plasma etched
> for target grating depth = 50nm)
> This is written by Raith 30um aperture with dose 125uC on 2% 950K PMMA.
> The one near the origin (where I adjust the focus with the
> contamination dots)
> was well written, but the one at 5mm above the origin was not.
> My GaAs chip size is about 8mm x 10mm. I paid particular attention for
> the clamping (at clip #2 of old sample holder), so that no tilt was
> visible.
> Also, the back side of the chip is reasonablly clean.
> Yesterday, the WD was 4.95mm near the origin, 4.96mm at (6mm, 9mm),
> 10um difference !
> Are your writings going well these days ? Should I adjust piezo
> manually ?
> Thanks for your comment !
> Shinichi
> ------------------------------------------------------------------------
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